564 lines
21 KiB
C
564 lines
21 KiB
C
/***************************************************************************//**
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* @file
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* @brief Clock management unit (CMU) API for EFM32.
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* @author Energy Micro AS
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* @version 1.3.0
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* This source code is the property of Energy Micro AS. The source and compiled
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* code may only be used on Energy Micro "EFM32" microcontrollers.
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*
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* This copyright notice may not be removed from the source code nor changed.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#ifndef __EFM32_CMU_H
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#define __EFM32_CMU_H
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#include <stdbool.h>
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#include "efm32.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************************************************************//**
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* @addtogroup EFM32_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup CMU
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* @{
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******************************************************************************/
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/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
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/* Select register ids, for internal use */
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#define CMU_NOSEL_REG 0
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#define CMU_HFCLKSEL_REG 1
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#define CMU_LFACLKSEL_REG 2
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#define CMU_LFBCLKSEL_REG 3
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#define CMU_SEL_REG_POS 0
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#define CMU_SEL_REG_MASK 0xf
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/* Divisor register ids, for internal use */
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#define CMU_NODIV_REG 0
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#define CMU_HFPERCLKDIV_REG 1
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#define CMU_HFCORECLKDIV_REG 2
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#define CMU_LFAPRESC0_REG 3
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#define CMU_LFBPRESC0_REG 4
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#define CMU_DIV_REG_POS 4
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#define CMU_DIV_REG_MASK 0xf
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/* Enable register ids, for internal use */
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#define CMU_NO_EN_REG 0
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#define CMU_HFPERCLKDIV_EN_REG 1
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#define CMU_HFPERCLKEN0_EN_REG 2
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#define CMU_HFCORECLKEN0_EN_REG 3
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#define CMU_LFACLKEN0_EN_REG 4
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#define CMU_LFBCLKEN0_EN_REG 5
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#define CMU_PCNT_EN_REG 6
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#define CMU_EN_REG_POS 8
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#define CMU_EN_REG_MASK 0xf
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/* Enable register bit position, for internal use */
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#define CMU_EN_BIT_POS 12
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#define CMU_EN_BIT_MASK 0x1f
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/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */
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/*******************************************************************************
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******************************** ENUMS ************************************
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******************************************************************************/
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/** Clock divisors. */
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typedef enum
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{
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cmuClkDiv_1 = 0, /**< Divide clock by 1. */
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cmuClkDiv_2 = 1, /**< Divide clock by 2. */
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cmuClkDiv_4 = 2, /**< Divide clock by 4. */
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cmuClkDiv_8 = 3, /**< Divide clock by 8. */
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cmuClkDiv_16 = 4, /**< Divide clock by 16. */
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cmuClkDiv_32 = 5, /**< Divide clock by 32. */
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cmuClkDiv_64 = 6, /**< Divide clock by 64. */
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cmuClkDiv_128 = 7, /**< Divide clock by 128. */
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cmuClkDiv_256 = 8, /**< Divide clock by 256. */
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cmuClkDiv_512 = 9, /**< Divide clock by 512. */
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cmuClkDiv_1024 = 10, /**< Divide clock by 1024. */
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cmuClkDiv_2048 = 11, /**< Divide clock by 2048. */
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cmuClkDiv_4096 = 12, /**< Divide clock by 4096. */
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cmuClkDiv_8192 = 13, /**< Divide clock by 8192. */
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cmuClkDiv_16384 = 14, /**< Divide clock by 16384. */
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cmuClkDiv_32768 = 15 /**< Divide clock by 32768. */
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} CMU_ClkDiv_TypeDef;
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/** High frequency RC bands. */
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typedef enum
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{
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/** 1MHz RC band. */
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cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ,
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/** 7MHz RC band. */
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cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ,
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/** 11MHz RC band. */
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cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,
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/** 14MHz RC band. */
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cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,
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/** 21MHz RC band. */
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cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,
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/** 28MHz RC band. */
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cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ
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} CMU_HFRCOBand_TypeDef;
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/** Clock points in CMU. Please refer to CMU overview in reference manual. */
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typedef enum
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{
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/*******************/
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/* HF clock branch */
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/*******************/
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/** High frequency clock */
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cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
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(CMU_NO_EN_REG << CMU_EN_REG_POS) |
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(0 << CMU_EN_BIT_POS),
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/**********************************/
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/* HF peripheral clock sub-branch */
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/**********************************/
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/** High frequency peripheral clock */
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cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS),
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/** Universal sync/async receiver/transmitter 0 clock. */
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#if defined(USART_COUNT) && (USART_COUNT > 0)
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cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Universal sync/async receiver/transmitter 1 clock. */
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#if defined(USART_COUNT) && (USART_COUNT > 1)
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cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Universal sync/async receiver/transmitter 2 clock. */
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#if defined(USART_COUNT) && (USART_COUNT > 2)
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cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Universal async receiver/transmitter 0 clock. */
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#if defined(UART_COUNT) && (UART_COUNT > 0)
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cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Timer 0 clock. */
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#if defined(TIMER_COUNT) && (TIMER_COUNT > 0)
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cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Timer 1 clock. */
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#if defined(TIMER_COUNT) && (TIMER_COUNT > 1)
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cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Timer 2 clock. */
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#if defined(TIMER_COUNT) && (TIMER_COUNT > 2)
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cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Analog comparator 0 clock. */
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#if defined(ACMP_COUNT) && (ACMP_COUNT > 0)
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cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Analog comparator 1 clock. */
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#if defined(ACMP_COUNT) && (ACMP_COUNT > 1)
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cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Peripheral reflex system clock. */
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#if defined(PRS_PRESENT)
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cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Digital to analog converter 0 clock. */
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#if defined(DAC_COUNT) && (DAC_COUNT > 0)
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cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** General purpose input/output clock. */
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#if defined(GPIO_PRESENT)
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cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Voltage comparator clock. */
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#if defined(VCMP_PRESENT)
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cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Analog to digital converter 0 clock. */
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#if defined(ADC_COUNT) && (ADC_COUNT > 0)
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cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** I2C 0 clock. */
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#if defined(I2C_COUNT) && (I2C_COUNT > 0)
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cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS),
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#endif
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/**********************/
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/* HF core sub-branch */
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/**********************/
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/** Core clock */
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cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_NO_EN_REG << CMU_EN_REG_POS) |
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(0 << CMU_EN_BIT_POS),
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/** Advanced encryption standard accelerator clock. */
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#if defined(AES_PRESENT)
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cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Direct memory access controller clock. */
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#if defined(DMA_PRESENT)
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cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Low energy clocking module clock. */
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cmuClock_CORELE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS),
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/** External bus interface clock. */
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#if defined(EBI_PRESENT)
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cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS),
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#endif
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/***************/
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/* LF A branch */
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/***************/
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/** Low frequency A clock */
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cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) |
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(CMU_NO_EN_REG << CMU_EN_REG_POS) |
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(0 << CMU_EN_BIT_POS),
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/** Real time counter clock. */
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#if defined(RTC_PRESENT)
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cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Low energy timer 0 clock. */
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#if defined(LETIMER_COUNT) && (LETIMER_COUNT > 0)
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cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Liquid crystal display, pre FDIV clock. */
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#if defined(LCD_PRESENT)
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cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_NO_EN_REG << CMU_EN_REG_POS) |
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(0 << CMU_EN_BIT_POS),
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/** Liquid crystal display clock. Please notice that FDIV prescaler
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* must be set by special API. */
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cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Pulse counter 0 clock. */
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#if defined(PCNT_COUNT) && (PCNT_COUNT > 0)
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cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
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(_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Pulse counter 1 clock. */
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#if defined(PCNT_COUNT) && (PCNT_COUNT > 1)
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cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
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(_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Pulse counter 2 clock. */
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#if defined(PCNT_COUNT) && (PCNT_COUNT > 2)
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cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
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(_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS),
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#endif
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/***************/
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/* LF B branch */
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/***************/
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/** Low frequency B clock */
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cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
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(CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) |
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(CMU_NO_EN_REG << CMU_EN_REG_POS) |
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(0 << CMU_EN_BIT_POS),
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/** Low energy universal asynchronous receiver/transmitter 0 clock. */
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#if defined(LEUART_COUNT) && (LEUART_COUNT > 0)
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cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS),
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#endif
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/** Low energy universal asynchronous receiver/transmitter 1 clock. */
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#if defined(LEUART_COUNT) && (LEUART_COUNT > 1)
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cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
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(CMU_NOSEL_REG << CMU_SEL_REG_POS) |
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(CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
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(_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS),
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#endif
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} CMU_Clock_TypeDef;
|
|
|
|
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|
/** Oscillator types. */
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|
typedef enum
|
|
{
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|
cmuOsc_LFXO, /**< Low frequency crystal oscillator. */
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|
cmuOsc_LFRCO, /**< Low frequency RC oscillator. */
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|
cmuOsc_HFXO, /**< High frequency crystal oscillator. */
|
|
cmuOsc_HFRCO, /**< High frequency RC oscillator. */
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|
cmuOsc_AUXHFRCO /**< Auxiliary high frequency RC oscillator. */
|
|
} CMU_Osc_TypeDef;
|
|
|
|
|
|
/** Selectable clock sources. */
|
|
typedef enum
|
|
{
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|
cmuSelect_Error, /**< Usage error. */
|
|
cmuSelect_Disabled, /**< Clock selector disabled. */
|
|
cmuSelect_LFXO, /**< Low frequency crystal oscillator. */
|
|
cmuSelect_LFRCO, /**< Low frequency RC oscillator. */
|
|
cmuSelect_HFXO, /**< High frequency crystal oscillator. */
|
|
cmuSelect_HFRCO, /**< High frequency RC oscillator. */
|
|
cmuSelect_CORELEDIV2 /**< Core low energy clock divided by 2. */
|
|
} CMU_Select_TypeDef;
|
|
|
|
|
|
/*******************************************************************************
|
|
***************************** PROTOTYPES **********************************
|
|
******************************************************************************/
|
|
|
|
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
|
|
|
|
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
|
|
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
|
|
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
|
|
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
|
|
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
|
|
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
|
|
|
|
void CMU_FreezeEnable(bool enable);
|
|
|
|
CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
|
|
void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
|
|
uint32_t CMU_HFRCOStartupDelayGet(void);
|
|
void CMU_HFRCOStartupDelaySet(uint32_t delay);
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Clear one or more pending CMU interrupts.
|
|
*
|
|
* @param[in] flags
|
|
* CMU interrupt sources to clear.
|
|
******************************************************************************/
|
|
static __INLINE void CMU_IntClear(uint32_t flags)
|
|
{
|
|
CMU->IFC = flags;
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Disable one or more CMU interrupts.
|
|
*
|
|
* @param[in] flags
|
|
* CMU interrupt sources to disable.
|
|
******************************************************************************/
|
|
static __INLINE void CMU_IntDisable(uint32_t flags)
|
|
{
|
|
CMU->IEN &= ~flags;
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Enable one or more CMU interrupts.
|
|
*
|
|
* @note
|
|
* Depending on the use, a pending interrupt may already be set prior to
|
|
* enabling the interrupt. Consider using CMU_IntClear() prior to enabling
|
|
* if such a pending interrupt should be ignored.
|
|
*
|
|
* @param[in] flags
|
|
* CMU interrupt sources to enable.
|
|
******************************************************************************/
|
|
static __INLINE void CMU_IntEnable(uint32_t flags)
|
|
{
|
|
CMU->IEN |= flags;
|
|
}
|
|
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Get pending CMU interrupts.
|
|
*
|
|
* @return
|
|
* CMU interrupt sources pending.
|
|
******************************************************************************/
|
|
static __INLINE uint32_t CMU_IntGet(void)
|
|
{
|
|
return(CMU->IF);
|
|
}
|
|
|
|
|
|
/**************************************************************************//**
|
|
* @brief
|
|
* Set one or more pending CMU interrupts from SW.
|
|
*
|
|
* @param[in] flags
|
|
* CMU interrupt sources to set to pending.
|
|
*****************************************************************************/
|
|
static __INLINE void CMU_IntSet(uint32_t flags)
|
|
{
|
|
CMU->IFS = flags;
|
|
}
|
|
|
|
uint32_t CMU_LCDClkFDIVGet(void);
|
|
void CMU_LCDClkFDIVSet(uint32_t div);
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Lock the CMU in order to protect some of its registers against unintended
|
|
* modification.
|
|
*
|
|
* @details
|
|
* Please refer to the reference manual for CMU registers that will be
|
|
* locked.
|
|
*
|
|
* @note
|
|
* If locking the CMU registers, they must be unlocked prior to using any
|
|
* CMU API functions modifying CMU registers protected by the lock.
|
|
******************************************************************************/
|
|
static __INLINE void CMU_Lock(void)
|
|
{
|
|
CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
|
|
}
|
|
|
|
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
|
|
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
|
|
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
|
|
bool CMU_PCNTClockExternalGet(unsigned int inst);
|
|
void CMU_PCNTClockExternalSet(unsigned int inst, bool external);
|
|
|
|
/***************************************************************************//**
|
|
* @brief
|
|
* Unlock the CMU so that writing to locked registers again is possible.
|
|
******************************************************************************/
|
|
static __INLINE void CMU_Unlock(void)
|
|
{
|
|
CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
|
|
}
|
|
|
|
|
|
/** @} (end addtogroup CMU) */
|
|
/** @} (end addtogroup EFM32_Library) */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __EFM32_CMU_H */
|