Grissiom 19fe6251e7 rm48x50: optimize context_switch_interrupt_to by reuse registers ... When saving thread registers in context_switch_interrupt_to, we don't change them, just move them. So there is no need to always r0-r3 from stack to the real r0-r3. So just use the intermediate registers and eliminate 2 MOV.		2013-05-26 22:37:49 +08:00
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arm	rm48x50: optimize context_switch_interrupt_to by reuse registers	2013-05-26 22:37:49 +08:00
avr32/uc3	convert end of line	2013-01-08 05:05:02 -08:00
blackfin/bf53x	convert end of line	2013-01-08 05:05:02 -08:00
ia32	convert end of line	2013-01-08 05:05:02 -08:00
m16c/m16c62p	convert end of line	2013-01-08 05:05:02 -08:00
mips	update loongson 1B dev: Modify the interrupt interface implementations.	2013-03-31 17:32:25 +08:00
nios/nios_ii	convert end of line	2013-01-08 05:05:02 -08:00
ppc	fix interrupt compiling issue in PPC	2013-03-31 22:58:36 -04:00
sim	basic mingw support for simulator: kernel and finsh	2013-02-26 16:03:08 +08:00
v850/70f34	convert end of line	2013-01-08 05:05:02 -08:00
xilinx/microblaze	convert end of line	2013-01-08 05:05:02 -08:00
SConscript	basic mingw support for simulator: kernel and finsh	2013-02-26 16:03:08 +08:00