306 lines
13 KiB
C
306 lines
13 KiB
C
/*
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* @brief LPC5410X PLL driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licenser disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __PLL_5410X_H_
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#define __PLL_5410X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup PLL_5410X CHIP: LPC5410X PLL Driver
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* @ingroup CHIP_5410X_DRIVERS
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* The PLL in the LPC5410x is flexible, but can be complex to use. This driver
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* provides functions to help setup and use the PLL in it's various supported
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* modes.<br>
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*
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* This driver does not alter PLL clock source or system clocks outside the
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* PLL (like the main clock source) that may be referenced from the PLL. It
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* may optionally setup system voltages, wait for PLL lock, and power cycle
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* the PLL during setup based on setup flags.
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*
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* The driver works by first generating a PLL setup structure from a desired
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* PLL configuration structure. The PLL setup structure is then passed to the
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* PLL setup function to setup the PLL. In a user spplication, the PLL setup
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* structure can be pre-populated with PLL setup data to avoid using the PLL
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* configuration structure (or multiple PLL setup structures can be used to
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* more dynamically control PLL output rate).
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*
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* <b>How to use this driver</b><br>
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@verbatim
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// Setup PLL configuration
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PLL_CONFIG_T pllConfig = {
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75000000, // desiredRate = 75MHz
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0, // InputRate = 0Hz (not used)
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0 // No flags, function will determine best setup to get closest rate
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};
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// Get closest PLL setup to get the desired configuration
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PLL_SETUP_T pllSetup;
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uint32_t actualPllRate;
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PLL_ERROR_T pllError;
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pllError = Chip_Clock_SetupPLLData(&pllConfig, &pllSetup, &actualPllRate);
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if (pllError != PLL_ERROR_SUCCESS) {
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printf("PLL setup error #%x\r\n", (uint32_t) pllError);
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while (1);
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}
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else {
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printf("PLL config successful, actual config rate = %uHz\r\n", actualPllRate);
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}
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// Make sure main system clock is not using PLL, as the PLL setup
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// function will power off and optionally power on the PLL
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Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_IRC);
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// Setup PLL source
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Chip_Clock_SetSystemPLLSource(SYSCON_PLLCLKSRC_IRC);
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// Now to apply the configuration to the PLL
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pllSetup.flags = PLL_SETUPFLAG_WAITLOCK;
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Chip_Clock_SetupSystemPLLPrec(&pllSetup);
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// Switch main system clock to PLL
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Chip_Clock_SetMainClockSource(SYSCON_MAINCLKSRC_PLLOUT);
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@endverbatim
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*
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* @{
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*/
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/**
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* Clock sources for system PLLs
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*/
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typedef enum CHIP_SYSCON_PLLCLKSRC {
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SYSCON_PLLCLKSRC_IRC = 0, /*!< Internal oscillator */
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SYSCON_PLLCLKSRC_CLKIN, /*!< External clock input pin */
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SYSCON_PLLCLKSRC_WDTOSC, /*!< WDT oscillator */
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SYSCON_PLLCLKSRC_RTC, /*!< RTC 32KHz oscillator */
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} CHIP_SYSCON_PLLCLKSRC_T;
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/**
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* @brief Set System PLL clock source
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* @param src : Clock source for system PLL
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* @return Nothing
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* @note The PLL should be pwoered down prior to changing the source.
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*/
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STATIC INLINE void Chip_Clock_SetSystemPLLSource(CHIP_SYSCON_PLLCLKSRC_T src)
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{
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LPC_SYSCON->SYSPLLCLKSEL = (uint32_t) src;
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}
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/**
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* @brief Return System PLL input clock rate
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* @return System PLL input clock rate
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*/
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uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
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/**
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* @brief Return System PLL output clock rate
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* @param recompute : Forces a PLL rate recomputation if true
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* @return System PLL output clock rate
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* @note The PLL rate is cached in the driver in a variable as
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* the rate computation function can take some time to perform. It
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* is recommended to use 'false' with the 'recompute' parameter.
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*/
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uint32_t Chip_Clock_GetSystemPLLOutClockRate(bool recompute);
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/**
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* @brief Enables and disables PLL bypass mode
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* @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
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* @return System PLL output clock rate
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*/
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void Chip_Clock_SetBypassPLL(bool bypass);
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/**
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* @brief Check if PLL is locked or not
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* @return true if the PLL is locked, false if not locked
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*/
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STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
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{
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return (bool) ((LPC_SYSCON->SYSPLLSTAT & 1) != 0);
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}
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/** @brief PLL configuration structure flags for 'flags' field
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* These flags control how the PLL configuration function sets up the PLL setup structure.<br>
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*
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* When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
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* configuration structure must be assigned with the expected PLL frequency. If the
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* PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
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* function and the driver will determine the PLL rate from the currently selected
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* PLL source. This flag might be used to configure the PLL input clock more accurately
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* when using the WDT oscillator or a more dyanmic CLKIN source.<br>
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*
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* When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
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* automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
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* are not used.<br>
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*/
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#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */
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#define PLL_CONFIGFLAG_FORCENOFRACT (1 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */
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/** @brief PLL Spread Spectrum (SS) Programmable modulation frequency
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* See (MF) field in the SYSPLLSSCTRL1 register in the UM.
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*/
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typedef enum {
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SS_MF_512 = (0 << 20), /*!< Nss = 512 (fm <20> 3.9 - 7.8 kHz) */
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SS_MF_384 = (1 << 20), /*!< Nss <20>= 384 (fm <20> 5.2 - 10.4 kHz) */
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SS_MF_256 = (2 << 20), /*!< Nss = 256 (fm <20> 7.8 - 15.6 kHz) */
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SS_MF_128 = (3 << 20), /*!< Nss = 128 (fm <20> 15.6 - 31.3 kHz) */
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SS_MF_64 = (4 << 20), /*!< Nss = 64 (fm <20> 32.3 - 64.5 kHz) */
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SS_MF_32 = (5 << 20), /*!< Nss = 32 (fm <20> 62.5- 125 kHz) */
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SS_MF_24 = (6 << 20), /*!< Nss <20>= 24 (fm <20> 83.3- 166.6 kHz) */
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SS_MF_16 = (7 << 20) /*!< Nss = 16 (fm <20> 125- 250 kHz) */
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} SS_PROGMODFM_T;
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/** @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
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* See (MR) field in the SYSPLLSSCTRL1 register in the UM.
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*/
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typedef enum {
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SS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
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SS_MR_K1 = (1 << 23), /*!< k = 1 */
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SS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
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SS_MR_K2 = (3 << 23), /*!< k = 2 */
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SS_MR_K3 = (4 << 23), /*!< k = 3 */
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SS_MR_K4 = (5 << 23), /*!< k = 4 */
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SS_MR_K6 = (6 << 23), /*!< k = 6 */
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SS_MR_K8 = (7 << 23) /*!< k = 8 */
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} SS_PROGMODDP_T;
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/** @brief PLL Spread Spectrum (SS) Modulation waveform control
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* See (MC) field in the SYSPLLSSCTRL1 register in the UM.<br>
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* Compensation for low pass filtering of the PLL to get a triangular
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* modulation at the output of the PLL, giving a flat frequency spectrum.
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*/
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typedef enum {
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SS_MC_NOC = (0 << 26), /*!< no compensation */
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SS_MC_RECC = (2 << 26), /*!< recommended setting */
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SS_MC_MAXC = (3 << 26), /*!< max. compensation */
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} SS_MODWVCTRL_T;
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/** @brief PLL configuration structure
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* This structure can be used to configure the settings for a PLL
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* setup structure. Fill in the desired configuration for the PLL
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* and call the PLL setup function to fill in a PLL setup structure.
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*/
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typedef struct {
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uint32_t desiredRate; /*!< Desired PLL rate in Hz */
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uint32_t InputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
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uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
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SS_PROGMODFM_T ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
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SS_PROGMODDP_T ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
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SS_MODWVCTRL_T ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
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bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
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} PLL_CONFIG_T;
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/** @brief PLL setup structure flags for 'flags' field
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* These flags control how the PLL setup function sets up the PLL
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*/
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#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */
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#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
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#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */
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/** @brief PLL setup structure
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* This structure can be used to pre-build a PLL setup configuration
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* at run-time and quickly set the PLL to the configuration. It can be
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* populated with the PLL setup function. If powering up or waiting
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* for PLL lock, the PLL input clock source should be configured prior
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* to PLL setup.
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*/
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typedef struct {
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uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
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uint32_t SYSPLLCTRL; /*!< PLL control register */
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uint32_t SYSPLLNDEC; /*!< PLL NDEC register */
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uint32_t SYSPLLPDEC; /*!< PLL PDEC register */
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uint32_t SYSPLLSSCTRL[2]; /*!< PLL SSCTL registers */
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} PLL_SETUP_T;
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/** @brief PLL status definitions
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*/
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typedef enum {
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PLL_ERROR_SUCCESS = 0, /*!< PLL operation was successful */
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PLL_ERROR_OUTPUT_TOO_LOW, /*!< PLL output rate request was too low */
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PLL_ERROR_OUTPUT_TOO_HIGH, /*!< PLL output rate request was too high */
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PLL_ERROR_INPUT_TOO_LOW, /*!< PLL input rate is too low */
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PLL_ERROR_INPUT_TOO_HIGH, /*!< PLL input rate is too high */
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PLL_ERROR_OUTSIDE_INTLIMIT /*!< Requested output rate isn't possible */
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} PLL_ERROR_T;
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/**
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* @brief Return System PLL output clock rate from setup structure
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* @param pSetup : Pointer to a PLL setup structure
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* @return System PLL output clock rate the setup structure will generate
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*/
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uint32_t Chip_Clock_GetSystemPLLOutFromSetup(PLL_SETUP_T *pSetup);
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/**
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* @brief Set PLL output based on the passed PLL setup data
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* @param pControl : Pointer to populated PLL control structure to generate setup with
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* @param pSetup : Pointer to PLL setup structure to be filled
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* @return PLL_ERROR_SUCCESS on success, or PLL setup error code
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* @note Actual frequency for setup may vary from the desired frequency based on the
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* accuracy of input clocks, rounding, non-fractional PLL mode, etc.
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*/
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PLL_ERROR_T Chip_Clock_SetupPLLData(PLL_CONFIG_T *pControl, PLL_SETUP_T *pSetup);
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/**
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* @brief Set PLL output from PLL setup structure (precise frequency)
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* @param pSetup : Pointer to populated PLL setup structure
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* @return PLL_ERROR_SUCCESS on success, or PLL setup error code
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* @note This function will power off the PLL, setup the PLL with the
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* new setup data, and then optionally powerup the PLL, wait for PLL lock,
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* and adjust system voltages to the new PLL rate. The function will not
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* alter any source clocks (ie, main systen clock) that may use the PLL,
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* so these should be setup prior to and after exiting the function.
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*/
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PLL_ERROR_T Chip_Clock_SetupSystemPLLPrec(PLL_SETUP_T *pSetup);
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/**
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* @brief Set PLL output based on the multiplier and input frequency
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* @param multiply_by : multiplier
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* @param input_freq : Clock input frequency of the PLL
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* @return Nothing
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* @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
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* function does not disable or enable PLL power, wait for PLL lock,
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* or adjust system voltages. These must be done in the application.
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* The function will not alter any source clocks (ie, main systen clock)
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* that may use the PLL, so these should be setup prior to and after
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* exiting the function.
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*/
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void Chip_Clock_SetupSystemPLL(uint32_t multiply_by, uint32_t input_freq);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PLL_5410X_H_ */
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