565 lines
17 KiB
C
565 lines
17 KiB
C
//*****************************************************************************
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//
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// watchdog.c - Driver for the Watchdog Timer Module.
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//
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// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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//! \addtogroup watchdog_api
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//! @{
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//
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//*****************************************************************************
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#include "inc/hw_ints.h"
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#include "inc/hw_memmap.h"
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#include "inc/hw_types.h"
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#include "inc/hw_watchdog.h"
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#include "driverlib/debug.h"
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#include "driverlib/interrupt.h"
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#include "driverlib/watchdog.h"
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//*****************************************************************************
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//
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//! Determines if the watchdog timer is enabled.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This will check to see if the watchdog timer is enabled.
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//!
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//! \return Returns \b true if the watchdog timer is enabled, and \b false
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//! if it is not.
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//
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//*****************************************************************************
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tBoolean
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WatchdogRunning(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// See if the watchdog timer module is enabled, and return.
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//
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return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
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}
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//*****************************************************************************
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//
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//! Enables the watchdog timer.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This will enable the watchdog timer counter and interrupt.
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//!
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//! \note This function will have no effect if the watchdog timer has
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//! been locked.
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//!
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//! \sa WatchdogLock(), WatchdogUnlock()
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Enable the watchdog timer module.
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//
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HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
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}
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//*****************************************************************************
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//
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//! Enables the watchdog timer reset.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! Enables the capability of the watchdog timer to issue a reset to the
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//! processor upon a second timeout condition.
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//!
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//! \note This function will have no effect if the watchdog timer has
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//! been locked.
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//!
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//! \sa WatchdogLock(), WatchdogUnlock()
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogResetEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Enable the watchdog reset.
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//
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HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_RESEN;
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}
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//*****************************************************************************
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//
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//! Disables the watchdog timer reset.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! Disables the capability of the watchdog timer to issue a reset to the
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//! processor upon a second timeout condition.
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//!
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//! \note This function will have no effect if the watchdog timer has
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//! been locked.
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//!
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//! \sa WatchdogLock(), WatchdogUnlock()
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogResetDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Disable the watchdog reset.
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//
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HWREG(ulBase + WDT_O_CTL) &= ~(WDT_CTL_RESEN);
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}
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//*****************************************************************************
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//
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//! Enables the watchdog timer lock mechanism.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! Locks out write access to the watchdog timer configuration registers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogLock(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
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// register causes the lock to go into effect.
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//
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HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
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}
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//*****************************************************************************
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//
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//! Disables the watchdog timer lock mechanism.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! Enables write access to the watchdog timer configuration registers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogUnlock(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Unlock watchdog register writes.
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//
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HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
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}
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//*****************************************************************************
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//
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//! Gets the state of the watchdog timer lock mechanism.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! Returns the lock state of the watchdog timer registers.
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//!
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//! \return Returns \b true if the watchdog timer registers are locked, and
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//! \b false if they are not locked.
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//
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//*****************************************************************************
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tBoolean
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WatchdogLockState(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Get the lock state.
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//
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return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
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}
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//*****************************************************************************
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//
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//! Sets the watchdog timer reload value.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//! \param ulLoadVal is the load value for the watchdog timer.
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//!
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//! This function sets the value to load into the watchdog timer when the count
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//! reaches zero for the first time; if the watchdog timer is running when this
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//! function is called, then the value will be immediately loaded into the
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//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
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//! interrupt is immediately generated.
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//!
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//! \note This function will have no effect if the watchdog timer has
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//! been locked.
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//!
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//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Set the load register.
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//
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HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
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}
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//*****************************************************************************
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//
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//! Gets the watchdog timer reload value.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This function gets the value that is loaded into the watchdog timer when
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//! the count reaches zero for the first time.
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//!
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//! \sa WatchdogReloadSet()
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//!
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//! \return None.
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//
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//*****************************************************************************
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unsigned long
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WatchdogReloadGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Get the load register.
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//
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return(HWREG(ulBase + WDT_O_LOAD));
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}
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//*****************************************************************************
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//
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//! Gets the current watchdog timer value.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This function reads the current value of the watchdog timer.
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//!
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//! \return Returns the current value of the watchdog timer.
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//
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//*****************************************************************************
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unsigned long
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WatchdogValueGet(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Get the current watchdog timer register value.
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//
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return(HWREG(ulBase + WDT_O_VALUE));
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}
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//*****************************************************************************
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//
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//! Registers an interrupt handler for watchdog timer interrupt.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//! \param pfnHandler is a pointer to the function to be called when the
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//! watchdog timer interrupt occurs.
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//!
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//! This function does the actual registering of the interrupt handler. This
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//! will enable the global interrupt in the interrupt controller; the watchdog
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//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
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//! handler's responsibility to clear the interrupt source via
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//! WatchdogIntClear().
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Register the interrupt handler.
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//
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IntRegister(INT_WATCHDOG, pfnHandler);
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//
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// Enable the watchdog timer interrupt.
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//
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IntEnable(INT_WATCHDOG);
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}
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//*****************************************************************************
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//
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//! Unregisters an interrupt handler for the watchdog timer interrupt.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This function does the actual unregistering of the interrupt handler. This
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//! function will clear the handler to be called when a watchdog timer
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//! interrupt occurs. This will also mask off the interrupt in the interrupt
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//! controller so that the interrupt handler no longer is called.
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//!
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//! \sa IntRegister() for important information about registering interrupt
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//! handlers.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogIntUnregister(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Disable the interrupt.
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//
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IntDisable(INT_WATCHDOG);
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//
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// Unregister the interrupt handler.
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//
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IntUnregister(INT_WATCHDOG);
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}
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//*****************************************************************************
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//
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//! Enables the watchdog timer interrupt.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! Enables the watchdog timer interrupt.
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//!
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//! \note This function will have no effect if the watchdog timer has
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//! been locked.
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//!
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//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogEnable()
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogIntEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Enable the watchdog interrupt.
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//
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HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
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}
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//*****************************************************************************
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//
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//! Gets the current watchdog timer interrupt status.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//! \param bMasked is \b false if the raw interrupt status is required and
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//! \b true if the masked interrupt status is required.
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//!
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//! This returns the interrupt status for the watchdog timer module. Either
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//! the raw interrupt status or the status of interrupt that is allowed to
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//! reflect to the processor can be returned.
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//!
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//! \return Returns the current interrupt status, where a 1 indicates that the
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//! watchdog interrupt is active, and a 0 indicates that it is not active.
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//
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//*****************************************************************************
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unsigned long
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WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Return either the interrupt status or the raw interrupt status as
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// requested.
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//
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if(bMasked)
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{
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return(HWREG(ulBase + WDT_O_MIS));
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}
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else
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{
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return(HWREG(ulBase + WDT_O_RIS));
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}
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}
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//*****************************************************************************
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//
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//! Clears the watchdog timer interrupt.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! The watchdog timer interrupt source is cleared, so that it no longer
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//! asserts.
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//!
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//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
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//! several clock cycles before the interrupt source is actually cleared.
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//! Therefore, it is recommended that the interrupt source be cleared early in
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//! the interrupt handler (as opposed to the very last action) to avoid
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//! returning from the interrupt handler before the interrupt source is
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//! actually cleared. Failure to do so may result in the interrupt handler
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//! being immediately reentered (since NVIC still sees the interrupt source
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//! asserted).
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogIntClear(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Clear the interrupt source.
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//
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HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
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}
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//*****************************************************************************
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//
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//! Enables stalling of the watchdog timer during debug events.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This function allows the watchdog timer to stop counting when the processor
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//! is stopped by the debugger. By doing so, the watchdog is prevented from
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//! expiring (typically almost immediately from a human time perspective) and
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//! resetting the system (if reset is enabled). The watchdog will instead
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//! expired after the appropriate number of processor cycles have been executed
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//! while debugging (or at the appropriate time after the processor has been
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//! restarted).
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogStallEnable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Enable timer stalling.
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//
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HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
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}
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//*****************************************************************************
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//
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//! Disables stalling of the watchdog timer during debug events.
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//!
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//! \param ulBase is the base address of the watchdog timer module.
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//!
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//! This function disables the debug mode stall of the watchdog timer. By
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//! doing so, the watchdog timer continues to count regardless of the processor
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//! debug state.
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//!
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//! \return None.
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//
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//*****************************************************************************
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void
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WatchdogStallDisable(unsigned long ulBase)
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{
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//
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// Check the arguments.
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//
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ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE));
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//
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// Disable timer stalling.
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//
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HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
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}
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//*****************************************************************************
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//
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// Close the Doxygen group.
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//! @}
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//
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//*****************************************************************************
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