689 lines
36 KiB
C
689 lines
36 KiB
C
//*****************************************************************************
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//
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// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
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//
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// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 8264 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_ETHERNET_H__
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#define __HW_ETHERNET_H__
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//*****************************************************************************
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//
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// The following are defines for the Ethernet MAC register offsets.
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//
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//*****************************************************************************
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#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt
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// Status/Acknowledge
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#define MAC_O_IACK 0x00000000 // Ethernet MAC Raw Interrupt
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// Status/Acknowledge
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#define MAC_O_IM 0x00000004 // Ethernet MAC Interrupt Mask
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#define MAC_O_RCTL 0x00000008 // Ethernet MAC Receive Control
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#define MAC_O_TCTL 0x0000000C // Ethernet MAC Transmit Control
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#define MAC_O_DATA 0x00000010 // Ethernet MAC Data
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#define MAC_O_IA0 0x00000014 // Ethernet MAC Individual Address
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// 0
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#define MAC_O_IA1 0x00000018 // Ethernet MAC Individual Address
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// 1
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#define MAC_O_THR 0x0000001C // Ethernet MAC Threshold
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#define MAC_O_MCTL 0x00000020 // Ethernet MAC Management Control
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#define MAC_O_MDV 0x00000024 // Ethernet MAC Management Divider
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#define MAC_O_MADD 0x00000028 // Ethernet MAC Management Address
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#define MAC_O_MTXD 0x0000002C // Ethernet MAC Management Transmit
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// Data
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#define MAC_O_MRXD 0x00000030 // Ethernet MAC Management Receive
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// Data
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#define MAC_O_NP 0x00000034 // Ethernet MAC Number of Packets
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#define MAC_O_TR 0x00000038 // Ethernet MAC Transmission
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// Request
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#define MAC_O_TS 0x0000003C // Ethernet MAC Timer Support
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#define MAC_O_LED 0x00000040 // Ethernet MAC LED Encoding
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#define MAC_O_MDIX 0x00000044 // Ethernet PHY MDIX
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_RIS register.
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//
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//*****************************************************************************
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#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt
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#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete
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#define MAC_RIS_RXER 0x00000010 // Receive Error
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#define MAC_RIS_FOV 0x00000008 // FIFO Overrun
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#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty
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#define MAC_RIS_TXER 0x00000002 // Transmit Error
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#define MAC_RIS_RXINT 0x00000001 // Packet Received
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_IACK register.
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//
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//*****************************************************************************
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#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt
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#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete
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#define MAC_IACK_RXER 0x00000010 // Clear Receive Error
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#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun
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#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty
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#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error
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#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_IM register.
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//
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//*****************************************************************************
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#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt
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#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete
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#define MAC_IM_RXERM 0x00000010 // Mask Receive Error
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#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun
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#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty
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#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error
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#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_RCTL register.
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//
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//*****************************************************************************
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#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO
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#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC
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#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode
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#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames
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#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_TCTL register.
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//
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//*****************************************************************************
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#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode
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#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation
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#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding
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#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_DATA register.
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//
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//*****************************************************************************
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#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data
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#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data
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#define MAC_DATA_RXDATA_S 0
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#define MAC_DATA_TXDATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_IA0 register.
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//
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//*****************************************************************************
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#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4
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#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3
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#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2
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#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1
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#define MAC_IA0_MACOCT4_S 24
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#define MAC_IA0_MACOCT3_S 16
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#define MAC_IA0_MACOCT2_S 8
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#define MAC_IA0_MACOCT1_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_IA1 register.
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//
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//*****************************************************************************
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#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6
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#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5
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#define MAC_IA1_MACOCT6_S 8
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#define MAC_IA1_MACOCT5_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_THR register.
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//
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//*****************************************************************************
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#define MAC_THR_THRESH_M 0x0000003F // Threshold Value
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#define MAC_THR_THRESH_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_MCTL register.
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//
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//*****************************************************************************
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#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address
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#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type
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#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable
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#define MAC_MCTL_REGADR_S 3
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_MDV register.
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//
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//*****************************************************************************
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#define MAC_MDV_DIV_M 0x000000FF // Clock Divider
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#define MAC_MDV_DIV_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_MADD register.
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//
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//*****************************************************************************
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#define MAC_MADD_PHYADR_M 0x0000001F // PHY Address
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#define MAC_MADD_PHYADR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_MTXD register.
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//
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//*****************************************************************************
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#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data
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#define MAC_MTXD_MDTX_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_MRXD register.
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//
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//*****************************************************************************
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#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data
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#define MAC_MRXD_MDRX_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_NP register.
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//
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//*****************************************************************************
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#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
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// FIFO
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#define MAC_NP_NPR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_TR register.
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//
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//*****************************************************************************
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#define MAC_TR_NEWTX 0x00000001 // New Transmission
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_TS register.
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//
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//*****************************************************************************
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#define MAC_TS_TSEN 0x00000001 // Time Stamp Enable
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_LED register.
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//
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//*****************************************************************************
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#define MAC_LED_LED1_M 0x00000F00 // LED1 Source
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#define MAC_LED_LED1_LINK 0x00000000 // Link OK
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#define MAC_LED_LED1_RXTX 0x00000100 // RX or TX Activity (Default LED1)
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#define MAC_LED_LED1_100 0x00000500 // 100BASE-TX mode
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#define MAC_LED_LED1_10 0x00000600 // 10BASE-T mode
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#define MAC_LED_LED1_DUPLEX 0x00000700 // Full-Duplex
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#define MAC_LED_LED1_LINKACT 0x00000800 // Link OK & Blink=RX or TX
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// Activity
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#define MAC_LED_LED0_M 0x0000000F // LED0 Source
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#define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0)
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#define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity
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#define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode
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#define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode
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#define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex
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#define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
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// Activity
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the MAC_O_MDIX register.
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//
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//*****************************************************************************
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#define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable
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//*****************************************************************************
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//
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// The following are defines for the Ethernet Controller PHY registers.
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//
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//*****************************************************************************
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#define PHY_MR0 0x00000000 // Ethernet PHY Management Register
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// 0 - Control
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#define PHY_MR1 0x00000001 // Ethernet PHY Management Register
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// 1 - Status
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#define PHY_MR2 0x00000002 // Ethernet PHY Management Register
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// 2 - PHY Identifier 1
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#define PHY_MR3 0x00000003 // Ethernet PHY Management Register
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// 3 - PHY Identifier 2
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#define PHY_MR4 0x00000004 // Ethernet PHY Management Register
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// 4 - Auto-Negotiation
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// Advertisement
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#define PHY_MR5 0x00000005 // Ethernet PHY Management Register
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// 5 - Auto-Negotiation Link
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// Partner Base Page Ability
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#define PHY_MR6 0x00000006 // Ethernet PHY Management Register
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// 6 - Auto-Negotiation Expansion
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#define PHY_MR16 0x00000010 // Ethernet PHY Management Register
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// 16 - Vendor-Specific
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#define PHY_MR17 0x00000011 // Ethernet PHY Management Register
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// 17 - Mode Control/Status
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#define PHY_MR18 0x00000012 // Ethernet PHY Management Register
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// 18 - Diagnostic
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#define PHY_MR19 0x00000013 // Ethernet PHY Management Register
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// 19 - Transceiver Control
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#define PHY_MR23 0x00000017 // Ethernet PHY Management Register
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// 23 - LED Configuration
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#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
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// 24 -MDI/MDIX Control
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#define PHY_MR27 0x0000001B // Ethernet PHY Management Register
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// 27 - Special Control/Status
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#define PHY_MR29 0x0000001D // Ethernet PHY Management Register
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// 29 - Interrupt Status
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#define PHY_MR30 0x0000001E // Ethernet PHY Management Register
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// 30 - Interrupt Mask
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#define PHY_MR31 0x0000001F // Ethernet PHY Management Register
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// 31 - PHY Special Control/Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR0 register.
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//
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//*****************************************************************************
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#define PHY_MR0_RESET 0x00008000 // Reset Registers
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#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode
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#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select
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#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable
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#define PHY_MR0_PWRDN 0x00000800 // Power Down
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#define PHY_MR0_ISO 0x00000400 // Isolate
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#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation
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#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode
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#define PHY_MR0_COLT 0x00000080 // Collision Test
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR1 register.
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//
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//*****************************************************************************
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#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode
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#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode
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#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode
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#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode
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#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
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// Suppressed
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#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete
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#define PHY_MR1_RFAULT 0x00000010 // Remote Fault
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#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation
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#define PHY_MR1_LINK 0x00000004 // Link Made
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#define PHY_MR1_JAB 0x00000002 // Jabber Condition
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#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR2 register.
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//
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//*****************************************************************************
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#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
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// Identifier[21:6]
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#define PHY_MR2_OUI_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR3 register.
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//
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//*****************************************************************************
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#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
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// Identifier[5:0]
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#define PHY_MR3_MN_M 0x000003F0 // Model Number
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#define PHY_MR3_RN_M 0x0000000F // Revision Number
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#define PHY_MR3_OUI_S 10
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#define PHY_MR3_MN_S 4
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#define PHY_MR3_RN_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR4 register.
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//
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//*****************************************************************************
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#define PHY_MR4_NP 0x00008000 // Next Page
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#define PHY_MR4_RF 0x00002000 // Remote Fault
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#define PHY_MR4_A3 0x00000100 // Technology Ability Field [3]
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#define PHY_MR4_A2 0x00000080 // Technology Ability Field [2]
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#define PHY_MR4_A1 0x00000040 // Technology Ability Field [1]
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#define PHY_MR4_A0 0x00000020 // Technology Ability Field [0]
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#define PHY_MR4_S_M 0x0000001F // Selector Field
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#define PHY_MR4_S_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR5 register.
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//
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//*****************************************************************************
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#define PHY_MR5_NP 0x00008000 // Next Page
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#define PHY_MR5_ACK 0x00004000 // Acknowledge
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#define PHY_MR5_RF 0x00002000 // Remote Fault
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#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field
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#define PHY_MR5_S_M 0x0000001F // Selector Field
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#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
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#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
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#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
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#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
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#define PHY_MR5_A_S 5
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR6 register.
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//
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//*****************************************************************************
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#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault
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#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able
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#define PHY_MR6_PRX 0x00000002 // New Page Received
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#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
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// Able
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR16 register.
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//
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//*****************************************************************************
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#define PHY_MR16_RPTR 0x00008000 // Repeater Mode
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#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity
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#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode
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#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing
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#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode
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#define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier
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#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable
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#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity
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#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass
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#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control
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#define PHY_MR16_SR_S 6
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR17 register.
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//
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//*****************************************************************************
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#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable
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#define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable
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#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable
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#define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down
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#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable
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#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
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// Interrupt Enable
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#define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable
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#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable
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#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
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// Enable
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#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable
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#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
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// Interrupt Enable
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#define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode
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#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt
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#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt
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#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt
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#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
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// Interrupt
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#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt
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#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt
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#define PHY_MR17_FGLS 0x00000004 // Force Good Link Status
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#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt
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#define PHY_MR17_ENON 0x00000002 // Energy On
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#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
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// Interrupt
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR18 register.
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//
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//*****************************************************************************
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#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure
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#define PHY_MR18_DPLX 0x00000800 // Duplex Mode
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#define PHY_MR18_RATE 0x00000400 // Rate
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#define PHY_MR18_RXSD 0x00000200 // Receive Detection
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#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR19 register.
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//
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//*****************************************************************************
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#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection
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#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
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// loss
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#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
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// loss
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#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
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// loss
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#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
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// loss
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|
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR23 register.
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//
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//*****************************************************************************
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#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source
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#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
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#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
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#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
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#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
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#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
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#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
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// Activity
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#define PHY_MR23_LED0_M 0x0000000F // LED0 Source
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#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
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#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
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#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
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#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
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#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
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#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
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// Activity
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|
|
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR24 register.
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//
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//*****************************************************************************
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#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode
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#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable
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#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration
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#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete
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#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed
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#define PHY_MR24_MDIX_SD_S 0
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|
|
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the PHY_MR27 register.
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//
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//*****************************************************************************
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#define PHY_MR27_XPOL 0x00000010 // Polarity State of 10 BASE-T
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|
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//*****************************************************************************
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//
|
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// The following are defines for the bit fields in the PHY_MR29 register.
|
|
//
|
|
//*****************************************************************************
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#define PHY_MR29_EONIS 0x00000080 // ENERGYON Interrupt
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#define PHY_MR29_ANCOMPIS 0x00000040 // Auto-Negotiation Complete
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// Interrupt
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#define PHY_MR29_RFLTIS 0x00000020 // Remote Fault Interrupt
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#define PHY_MR29_LDIS 0x00000010 // Link Down Interrupt
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#define PHY_MR29_LPACKIS 0x00000008 // Auto-Negotiation LP Acknowledge
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#define PHY_MR29_PDFIS 0x00000004 // Parallel Detection Fault
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#define PHY_MR29_PRXIS 0x00000002 // Auto Negotiation Page Received
|
|
|
|
//*****************************************************************************
|
|
//
|
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// The following are defines for the bit fields in the PHY_MR30 register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PHY_MR30_EONIM 0x00000080 // ENERGYON Interrupt Enabled
|
|
#define PHY_MR30_ANCOMPIM 0x00000040 // Auto-Negotiation Complete
|
|
// Interrupt Enabled
|
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#define PHY_MR30_RFLTIM 0x00000020 // Remote Fault Interrupt Enabled
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|
#define PHY_MR30_LDIM 0x00000010 // Link Down Interrupt Enabled
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#define PHY_MR30_LPACKIM 0x00000008 // Auto-Negotiation LP Acknowledge
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|
// Enabled
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#define PHY_MR30_PDFIM 0x00000004 // Parallel Detection Fault Enabled
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#define PHY_MR30_PRXIM 0x00000002 // Auto Negotiation Page Received
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|
// Enabled
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are defines for the bit fields in the PHY_MR31 register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PHY_MR31_AUTODONE 0x00001000 // Auto Negotiation Done
|
|
#define PHY_MR31_SPEED_M 0x0000001C // HCD Speed Value
|
|
#define PHY_MR31_SPEED_10HD 0x00000004 // 10BASE-T half duplex
|
|
#define PHY_MR31_SPEED_100HD 0x00000008 // 100BASE-T half duplex
|
|
#define PHY_MR31_SPEED_10FD 0x00000014 // 10BASE-T full duplex
|
|
#define PHY_MR31_SPEED_100FD 0x00000018 // 100BASE-T full duplex
|
|
#define PHY_MR31_SCRDIS 0x00000001 // Scramble Disable
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following definitions are deprecated.
|
|
//
|
|
//*****************************************************************************
|
|
#ifndef DEPRECATED
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the Ethernet MAC register offsets.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_O_IS 0x00000000 // Interrupt Status Register
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the MAC_O_IS
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt
|
|
#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete
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|
#define MAC_IS_RXER 0x00000010 // RX Error
|
|
#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun
|
|
#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy
|
|
#define MAC_IS_TXER 0x00000002 // TX Error
|
|
#define MAC_IS_RXINT 0x00000001 // RX Packet Available
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the MAC_O_IA0
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address
|
|
#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address
|
|
#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address
|
|
#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the MAC_O_IA1
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address
|
|
#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the MAC_O_THR
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the MAC_O_MCTL
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the MAC_O_MDV
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the MAC_O_MTXD
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the MAC_O_MRXD
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the MAC_O_NP
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the bit fields in the PHY_MR23
|
|
// register.
|
|
//
|
|
//*****************************************************************************
|
|
#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
|
|
#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
|
|
#define PHY_MR23_LED1_COL 0x00000040 // Collision
|
|
#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
|
|
#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
|
|
#define PHY_MR23_LED0_COL 0x00000004 // Collision
|
|
|
|
//*****************************************************************************
|
|
//
|
|
// The following are deprecated defines for the reset values of the MAC
|
|
// registers.
|
|
//
|
|
//*****************************************************************************
|
|
#define MAC_RV_MDV 0x00000080
|
|
#define MAC_RV_IM 0x0000007F
|
|
#define MAC_RV_THR 0x0000003F
|
|
#define MAC_RV_RCTL 0x00000008
|
|
#define MAC_RV_IA0 0x00000000
|
|
#define MAC_RV_TCTL 0x00000000
|
|
#define MAC_RV_DATA 0x00000000
|
|
#define MAC_RV_MRXD 0x00000000
|
|
#define MAC_RV_TR 0x00000000
|
|
#define MAC_RV_IS 0x00000000
|
|
#define MAC_RV_NP 0x00000000
|
|
#define MAC_RV_MCTL 0x00000000
|
|
#define MAC_RV_MTXD 0x00000000
|
|
#define MAC_RV_IA1 0x00000000
|
|
#define MAC_RV_IACK 0x00000000
|
|
#define MAC_RV_MADD 0x00000000
|
|
|
|
#endif
|
|
|
|
#endif // __HW_ETHERNET_H__
|