185 lines
5.3 KiB
C
185 lines
5.3 KiB
C
/*
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* @brief LPC5410X Power Management declarations and functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __PMU_5410X_H_
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#define __PMU_5410X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup PMU_5410X CHIP: LPC5410X Power Management declarations and functions
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* @ingroup CHIP_5410X_DRIVERS
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* @{
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*/
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/**
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* @brief PMU register block structure
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* @note Most of the PMU support is handled by the PMU library.
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*/
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typedef struct {
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__I uint32_t RESERVED0[4];
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__I uint32_t RESERVED1[4];
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__I uint32_t RESERVED2[4];
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__I uint32_t RESERVED3[4];
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__I uint32_t RESERVED4;
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__IO uint32_t BODCTRL;
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__I uint32_t RESERVED5;
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__I uint32_t RESERVED6;
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__IO uint32_t DPDWAKESRC;
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} LPC_PMU_T;
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/**
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* Brown-out detector reset level
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*/
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typedef enum {
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PMU_BODRSTLVL_0, /*!< Brown-out reset at ~1.5v */
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PMU_BODRSTLVL_1_50V = PMU_BODRSTLVL_0,
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PMU_BODRSTLVL_1, /*!< Brown-out reset at ~1.85v */
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PMU_BODRSTLVL_1_85V = PMU_BODRSTLVL_1,
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PMU_BODRSTLVL_2, /*!< Brown-out reset at ~2.0v */
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PMU_BODRSTLVL_2_00V = PMU_BODRSTLVL_2,
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PMU_BODRSTLVL_3, /*!< Brown-out reset at ~2.3v */
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PMU_BODRSTLVL_2_30V = PMU_BODRSTLVL_3
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} CHIP_PMU_BODRSTLVL_T;
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/**
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* Brown-out detector interrupt level
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*/
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typedef enum CHIP_PMU_BODRINTVAL {
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PMU_BODINTVAL_LVL0, /*!< Brown-out interrupt at ~2.05v */
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PMU_BODINTVAL_2_05v = PMU_BODINTVAL_LVL0,
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PMU_BODINTVAL_LVL1, /*!< Brown-out interrupt at ~2.45v */
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PMU_BODINTVAL_2_45v = PMU_BODINTVAL_LVL1,
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PMU_BODINTVAL_LVL2, /*!< Brown-out interrupt at ~2.75v */
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PMU_BODINTVAL_2_75v = PMU_BODINTVAL_LVL2,
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PMU_BODINTVAL_LVL3, /*!< Brown-out interrupt at ~3.05v */
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PMU_BODINTVAL_3_05v = PMU_BODINTVAL_LVL3
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} CHIP_PMU_BODRINTVAL_T;
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/**
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* brown-out detection reset status (in BODCTRL register)
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*/
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#define PMU_BOD_RST (1 << 6)
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/**
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* brown-out detection interrupt status (in BODCTRL register)
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*/
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#define PMU_BOD_INT (1 << 7)
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/**
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* @brief Set brown-out detection interrupt and reset levels
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* @param rstlvl : Brown-out detector reset level
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* @param intlvl : Brown-out interrupt level
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* @return Nothing
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* @note Brown-out detection reset will be disabled upon exiting this function.
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* Use Chip_PMU_EnableBODReset() to re-enable.
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*/
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STATIC INLINE void Chip_PMU_SetBODLevels(CHIP_PMU_BODRSTLVL_T rstlvl,
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CHIP_PMU_BODRINTVAL_T intlvl)
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{
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LPC_PMU->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
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}
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/**
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* @brief Enable brown-out detection reset
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* @return Nothing
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*/
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STATIC INLINE void Chip_PMU_EnableBODReset(void)
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{
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LPC_PMU->BODCTRL |= (1 << 4);
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}
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/**
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* @brief Disable brown-out detection reset
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* @return Nothing
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*/
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STATIC INLINE void Chip_PMU_DisableBODReset(void)
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{
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LPC_PMU->BODCTRL &= ~(1 << 4);
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}
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/**
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* @brief Enable brown-out detection interrupt
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* @return Nothing
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*/
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STATIC INLINE void Chip_PMU_EnableBODInt(void)
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{
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LPC_PMU->BODCTRL |= (1 << 5);
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}
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/**
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* @brief Disable brown-out detection interrupt
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* @return Nothing
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*/
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STATIC INLINE void Chip_PMU_DisableBODInt(void)
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{
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LPC_PMU->BODCTRL &= ~(1 << 5);
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}
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/**
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* Deep power down reset sources
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*/
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#define PMU_DPDWU_RESET (1 << 0) /*!< Deep powerdown wakeup by reset pin */
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#define PMU_DPDWU_RTC (1 << 1) /*!< Deep powerdown wakeup by RTC */
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#define PMU_DPDWU_BODRESET (1 << 2) /*!< Deep powerdown wakeup by brown out reset*/
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#define PMU_DPDWU_BODINTR (1 << 3) /*!< Deep powerdown wakeup by brown out interrupt */
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/**
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* @brief Return wakeup sources from deep power down mode
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* @return Deep power down mode wakeup sources
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* @note Mask the return value with a PMU_DPDWU_* value to determine
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* the wakeup source from deep power down.
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*/
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STATIC INLINE uint32_t Chip_PMU_GetDPDWUSource(void)
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{
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return LPC_PMU->DPDWAKESRC;
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}
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/**
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* @brief Clear a deep power down mode wakeup source
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* @param mask : Or'ed PMU_DPDWU_* values to clear
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* @return Nothing
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*/
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STATIC INLINE void Chip_PMU_ClearDPDWUSource(uint32_t mask)
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{
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LPC_PMU->DPDWAKESRC = mask;
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}
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PMU_5410X_H_ */
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