307 lines
9.6 KiB
C
307 lines
9.6 KiB
C
/*
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* @brief LPC5410X System FIFO chip driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "chip.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/** SPI FIFO read FIFO statuses */
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#define LPC_SPIRXFIFO_STAT_SSEL0N (1 << 16) /*!< Slave select for receive on SSEL0 (active low) */
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#define LPC_SPIRXFIFO_STAT_SSEL1N (1 << 17) /*!< Slave select for receive on SSEL1 (active low) */
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#define LPC_SPIRXFIFO_STAT_SSEL2N (1 << 18) /*!< Slave select for receive on SSEL2 (active low) */
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#define LPC_SPIRXFIFO_STAT_SSEL3N (1 << 19) /*!< Slave select for receive on SSEL3 (active low) */
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#define LPC_SPIRXFIFO_STAT_SOT (1 << 20) /*!< This flag will be 1 if this is the first data after the SSELs went from deasserted to asserted */
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/** SPI FIFO write FIFO control */
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#define LPC_SPITXFIFO_CTRL_SSEL0N (1 << 16) /*!< Master assert for receive on SSEL0 (active low) */
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#define LPC_SPITXFIFO_CTRL_SSEL1N (1 << 17) /*!< Master assert for receive on SSEL1 (active low) */
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#define LPC_SPITXFIFO_CTRL_SSEL2N (1 << 18) /*!< Master assert for receive on SSEL2 (active low) */
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#define LPC_SPITXFIFO_CTRL_SSEL3N (1 << 19) /*!< Master assert for receive on SSEL3 (active low) */
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#define LPC_SPITXFIFO_CTRL_EOT (1 << 20) /*!< End of Transfer. The asserted SSEL will be deasserted at the end of a transfer */
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#define LPC_SPITXFIFO_CTRL_EOF (1 << 21) /*!< End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value in the DLY register */
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#define LPC_SPITXFIFO_CTRL_RXIGNORE (1 << 22) /*!< Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver */
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#define LPC_SPITXFIFO_CTRL_LEN(n) ((n) << 24) /*!< Data Length. Specifies the data length from 1 to 16 bits ((n-1) encoded) */
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Initializes the system FIFO */
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void Chip_FIFO_Init(LPC_FIFO_T *pFIFO)
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{
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Chip_Clock_EnablePeriphClock(SYSCON_CLOCK_FIFO);
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Chip_SYSCON_PeriphReset(RESET_FIFO);
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}
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/* Deinitializes the system FIFO */
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void Chip_FIFO_Deinit(LPC_FIFO_T *pFIFO)
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{
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Chip_Clock_DisablePeriphClock(SYSCON_CLOCK_FIFO);
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}
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/* Get the FIFO space available for the USART/SPI direction */
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uint32_t Chip_FIFO_GetFifoSpace(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir)
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{
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uint32_t pcfg;
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if (periphId == FIFO_USART) {
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pcfg = pFIFO->common.FIFOCTLUSART;
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}
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else {
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pcfg = pFIFO->common.FIFOCTLSPI;
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}
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if (dir == FIFO_RX) {
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pcfg = pcfg >> 16;
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}
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else {
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pcfg = pcfg >> 24;
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}
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return pcfg & 0xFF;
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}
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/* Pause a peripheral FIFO */
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void Chip_FIFO_PauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir)
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{
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if (periphId == FIFO_USART) {
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if (dir == FIFO_RX) {
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pFIFO->common.FIFOCTLUSART |= (1 << 0);
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}
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else {
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pFIFO->common.FIFOCTLUSART |= (1 << 8);
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}
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}
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else {
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if (dir == FIFO_RX) {
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pFIFO->common.FIFOCTLSPI |= (1 << 0);
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}
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else {
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pFIFO->common.FIFOCTLSPI |= (1 << 8);
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}
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}
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}
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/* Unpause a peripheral FIFO */
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void Chip_FIFO_UnpauseFifo(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_DIR_T dir)
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{
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if (periphId == FIFO_USART) {
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if (dir == FIFO_RX) {
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pFIFO->common.FIFOCTLUSART &= ~(1 << 0);
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}
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else {
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pFIFO->common.FIFOCTLUSART &= ~(1 << 8);
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}
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}
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else {
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if (dir == FIFO_RX) {
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pFIFO->common.FIFOCTLSPI &= ~(1 << 0);
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}
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else {
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pFIFO->common.FIFOCTLSPI &= ~(1 << 8);
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}
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}
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}
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/* Configure a peripheral's FIFO sizes */
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void Chip_FIFO_ConfigFifoSize(LPC_FIFO_T *pFIFO, LPC_FIFO_PERIPHID_T periphId, LPC_FIFO_CFGSIZE_T *pSizes)
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{
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int maxP, i;
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uint32_t upDateMask;
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volatile uint32_t *updateReg, *pFifoSizes, *pFifoPause;
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/* Pause FIFOs */
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Chip_FIFO_PauseFifo(LPC_FIFO, periphId, FIFO_RX);
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Chip_FIFO_PauseFifo(LPC_FIFO, periphId, FIFO_TX);
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/* Maximum peripheral FIFOs supported */
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if (periphId == FIFO_USART) {
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maxP = LPC_FIFO_USART_MAX;
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updateReg = &pFIFO->common.FIFOUPDATEUSART;
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upDateMask = 0xF | (0xF << 16);
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pFifoSizes = &pFIFO->common.FIFOCFGUSART[0];
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pFifoPause = &pFIFO->common.FIFOCTLUSART;
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}
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else {
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maxP = LPC_FIFO_SPI_MAX;
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updateReg = &pFIFO->common.FIFOUPDATESPI;
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upDateMask = 0x3 | (0x3 << 16);
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pFifoSizes = &pFIFO->common.FIFOCFGSPI[0];
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pFifoPause = &pFIFO->common.FIFOCTLSPI;
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}
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/* Wait for FIFO pause */
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while ((*pFifoPause & ((1 << 0) | (1 << 8))) != ((1 << 0) | (1 << 8))) {}
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/* Update FIFO sizes */
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for (i = 0; i < maxP; i++) {
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pFifoSizes[i] = ((uint32_t) (pSizes->fifoRXSize[i]) << 0) |
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((uint32_t) (pSizes->fifoTXSize[i]) << 8);
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}
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/* Update all peripheral FIFO sizes */
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*updateReg = upDateMask;
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}
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/* Configure the USART system FIFO */
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void Chip_FIFOUSART_Configure(LPC_FIFO_T *pFIFO, int usartIndex, LPC_FIFO_CFG_T *pUSARTCfg)
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{
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pFIFO->usart[usartIndex].CFG =
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(pUSARTCfg->noTimeoutContWrite << 4) |
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(pUSARTCfg->noTimeoutContEmpty << 5) |
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(pUSARTCfg->timeoutBase << 8) |
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(pUSARTCfg->timeoutValue << 12) |
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(pUSARTCfg->rxThreshold << 16) |
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(pUSARTCfg->txThreshold << 24);
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}
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/* Write data to a system FIFO (non-blocking) */
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int Chip_FIFOUSART_WriteTX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData)
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{
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int datumWritten, sz16;
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uint8_t *p8 = (uint8_t *) buff;
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uint16_t *p16 = (uint16_t *) buff;
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/* Get configured FIFO size to determine write size, limit to buffer size */
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sz16 = (pFIFO->usart[usartIndex].STAT >> 24) & 0xFF;
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if (sz16 > numData) {
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sz16 = numData;
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}
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datumWritten = sz16;
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/* Write from buffer */
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while (sz16 > 0) {
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if (sz8) {
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pFIFO->usart[usartIndex].TXDAT = (uint32_t) *p8;
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p8++;
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}
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else {
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pFIFO->usart[usartIndex].TXDAT = (uint32_t) *p16;
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p16++;
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}
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sz16--;
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}
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return datumWritten;
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}
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/* Read data from a system FIFO (non-blocking) */
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int Chip_FIFOUSART_ReadRX(LPC_FIFO_T *pFIFO, int usartIndex, bool sz8, void *buff, int numData)
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{
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int datumRead, sz16;
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uint8_t *p8 = (uint8_t *) buff;
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uint16_t *p16 = (uint16_t *) buff;
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/* Get configured FIFO size to determine read size, limit to buffer size */
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sz16 = (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF;
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if (sz16 > numData) {
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sz16 = numData;
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}
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datumRead = sz16;
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/* Read into buffer */
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while (sz16 > 0) {
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if (sz8) {
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*p8 = (uint8_t) (pFIFO->usart[usartIndex].RXDAT & 0xFF);
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p8++;
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}
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else {
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*p16 = (uint16_t) (pFIFO->usart[usartIndex].RXDAT & 0x1FF);
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p16++;
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}
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sz16--;
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}
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return datumRead;
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}
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/* Read data from a system FIFO with status (non-blocking) */
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int Chip_FIFOUSART_ReadRXStatus(LPC_FIFO_T *pFIFO, int usartIndex, uint16_t *buff, int numData)
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{
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int datumRead, sz16;
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uint16_t *p16 = (uint16_t *) buff;
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/* Get configured FIFO size to determine read size, limit to buffer size */
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sz16 = (pFIFO->usart[usartIndex].STAT >> 16) & 0xFF;
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if (sz16 > numData) {
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sz16 = numData;
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}
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datumRead = sz16;
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/* Read into buffer */
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while (sz16 > 0) {
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*p16 = (uint16_t) (pFIFO->usart[usartIndex].RXDATSTAT & 0xFFFF);
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p16++;
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sz16--;
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}
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return datumRead;
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}
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#if 0 /* Sorry, not yet support */
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/* Configure the USART system FIFO */
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void Chip_FIFOSPI_Configure(LPC_FIFO_T *pFIFO, int spiIndex, LPC_FIFO_CFG_T *pSPICfg)
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{
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pFIFO->spi[spiIndex].CFG =
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(pSPICfg->noTimeoutContWrite << 4) |
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(pSPICfg->noTimeoutContEmpty << 5) |
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(pSPICfg->timeoutBase << 6) |
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(pSPICfg->timeoutValue << 12) |
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(pSPICfg->rxThreshold << 16) |
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(pSPICfg->txThreshold << 24);
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}
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/* Start a data transfer (non-blocking) */
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void Chip_FIFOSPI_StartTransfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData)
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{
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pSetupData->start = 1;
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Chip_FIFOSPI_Transfer(pFIFO, pSetupData);
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}
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/* Feed a SPI data transfer (non-blocking) */
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void Chip_FIFOSPI_Transfer(LPC_FIFO_T *pFIFO, LPC_FIFO_SPICTL_T *pSetupData)
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{
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// FIXME - not yet ready
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}
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#endif
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