490 lines
12 KiB
C
490 lines
12 KiB
C
/*
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* File : serial.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2013, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-06 Bernard the first version
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* 2014-01-11 RTsien support UART0 to UART5 straightly
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <am33xx.h>
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#include <interrupt.h>
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#include "serial.h"
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#include "serial_reg.h"
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struct am33xx_uart
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{
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unsigned long base;
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int irq;
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};
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static void am33xx_uart_isr(int irqno, void* param)
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{
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rt_uint32_t iir;
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struct am33xx_uart* uart;
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struct rt_serial_device *serial;
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serial = (struct rt_serial_device*)param;
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uart = (struct am33xx_uart *)serial->parent.user_data;
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iir = UART_IIR_REG(uart->base);
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if ((iir & (0x02 << 1)) || (iir & (0x6 << 1)))
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{
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
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}
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}
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#define NOT_IMPLEMENTED() RT_ASSERT(0)
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static rt_err_t am33xx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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struct am33xx_uart* uart;
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unsigned long base;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct am33xx_uart *)serial->parent.user_data;
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RT_ASSERT(uart);
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base = uart->base;
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#define __LCR UART_LCR_REG(base)
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if (cfg->data_bits == DATA_BITS_8)
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__LCR |= 3;
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else
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NOT_IMPLEMENTED();
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if (cfg->stop_bits == STOP_BITS_1)
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__LCR &= ~(1<<2);
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else
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__LCR |= (1<<2);
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if (cfg->parity == PARITY_NONE)
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__LCR &= ~(1<<3);
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else
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__LCR |= (1<<3);
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__LCR |= (1<<7);
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if (cfg->baud_rate == BAUD_RATE_115200)
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{
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UART_DLL_REG(base) = 26;
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UART_DLH_REG(base) = 0;
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}
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else
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{
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NOT_IMPLEMENTED();
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}
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__LCR &= ~(1<<7);
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UART_MDR1_REG(base) = 0;
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UART_MDR2_REG(base) = 0;
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#undef __LCR
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return RT_EOK;
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}
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static rt_err_t am33xx_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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struct am33xx_uart* uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct am33xx_uart *)serial->parent.user_data;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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rt_hw_interrupt_mask(uart->irq);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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rt_hw_interrupt_umask(uart->irq);
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break;
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}
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return RT_EOK;
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}
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int printkc(char c)
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{
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int base = 0xf9e09000;
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while (!(UART_LSR_REG(base) & 0x20));
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UART_THR_REG(base) = c;
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return 1;
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}
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static int am33xx_putc(struct rt_serial_device *serial, char c)
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{
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struct am33xx_uart* uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct am33xx_uart *)serial->parent.user_data;
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while (!(UART_LSR_REG(uart->base) & 0x20));
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UART_THR_REG(uart->base) = c;
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return 1;
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}
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static int am33xx_getc(struct rt_serial_device *serial)
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{
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int ch;
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struct am33xx_uart* uart;
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RT_ASSERT(serial != RT_NULL);
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uart = (struct am33xx_uart *)serial->parent.user_data;
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ch = -1;
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if (UART_LSR_REG(uart->base) & 0x01)
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{
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ch = UART_RHR_REG(uart->base) & 0xff;
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}
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return ch;
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}
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static const struct rt_uart_ops am33xx_uart_ops =
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{
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am33xx_configure,
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am33xx_control,
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am33xx_putc,
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am33xx_getc,
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};
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/* UART device driver structure */
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#ifdef RT_USING_UART0
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struct am33xx_uart uart0 =
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{
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UART0_BASE,
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UART0_INT,
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};
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struct rt_serial_device serial0;
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#endif
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#ifdef RT_USING_UART1
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struct am33xx_uart uart1 =
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{
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UART1_BASE,
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UART1_INT,
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};
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struct rt_serial_device serial1;
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#endif
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#ifdef RT_USING_UART2
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struct am33xx_uart uart2 =
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{
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UART2_BASE,
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UART2_INT,
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};
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struct rt_serial_device serial2;
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#endif
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#ifdef RT_USING_UART3
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struct am33xx_uart uart3 =
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{
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UART3_BASE,
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UART3_INT,
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};
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struct rt_serial_device serial3;
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#endif
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#ifdef RT_USING_UART4
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struct am33xx_uart uart4 =
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{
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UART4_BASE,
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UART4_INT,
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};
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struct rt_serial_device serial4;
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#endif
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#ifdef RT_USING_UART5
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struct am33xx_uart uart5 =
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{
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UART5_BASE,
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UART5_INT,
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};
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struct rt_serial_device serial5;
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#endif
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#define write_reg(base, value) *(int*)(base) = value
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#define read_reg(base) *(int*)(base)
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#define PRM_PER_INTRANSLATION (1 << 20)
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#define PRM_PER_POWSTATEOFF (0)
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#define PRM_PER_PERMEMSTATEOFF (0)
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static void poweron_per_domain(void)
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{
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unsigned long prcm_base;
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unsigned long prm_state;
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prcm_base = AM33XX_PRCM_REGS;
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/* wait for ongoing translations */
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for (prm_state = PRM_PER_PWRSTST_REG(prcm_base);
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prm_state & PRM_PER_INTRANSLATION;
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prm_state = PRM_PER_PWRSTST_REG(prcm_base))
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;
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/* check power state */
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if ((prm_state & 0x03) == PRM_PER_POWSTATEOFF)
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/* power on PER domain */
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PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3;
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/* check per mem state */
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if ((prm_state & 0x03) == PRM_PER_PERMEMSTATEOFF)
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/* power on PER domain */
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PRM_PER_PWRSTCTRL_REG(prcm_base) |= 0x3 << 25;
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while (PRM_PER_PWRSTST_REG(prcm_base) & PRM_PER_INTRANSLATION)
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;
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}
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static void start_uart_clk(void)
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{
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unsigned long prcm_base;
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prcm_base = AM33XX_PRCM_REGS;
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/* software forced wakeup */
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CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) |= 0x2;
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/* Waiting for the L4LS clock */
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while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
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;
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/* enable uart1 */
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#ifdef RT_USING_UART1
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CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart1 clk */
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while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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#ifdef RT_USING_UART2
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CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart2 clk */
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while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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#ifdef RT_USING_UART3
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CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart3 clk */
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while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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#ifdef RT_USING_UART4
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CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart4 clk */
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while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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#ifdef RT_USING_UART5
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CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2;
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/* wait for uart5 clk */
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while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0)
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;
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#endif
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/* Waiting for the L4LS UART clock */
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while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10)))
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;
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}
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static void config_pinmux(void)
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{
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unsigned long ctlm_base;
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ctlm_base = AM33XX_CTLM_REGS;
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/* make sure the pin mux is OK for uart */
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#ifdef RT_USING_UART1
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REG32(ctlm_base + 0x800 + 0x180) = 0x20;
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REG32(ctlm_base + 0x800 + 0x184) = 0x00;
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#endif
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#ifdef RT_USING_UART2
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REG32(ctlm_base + 0x800 + 0x150) = 0x20;
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REG32(ctlm_base + 0x800 + 0x154) = 0x00;
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#endif
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#ifdef RT_USING_UART3
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REG32(ctlm_base + 0x800 + 0x164) = 0x01;
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#endif
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#ifdef RT_USING_UART4
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REG32(ctlm_base + 0x800 + 0x070) = 0x26;
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REG32(ctlm_base + 0x800 + 0x074) = 0x06;
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#endif
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#ifdef RT_USING_UART5
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REG32(ctlm_base + 0x800 + 0x0C4) = 0x24;
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REG32(ctlm_base + 0x800 + 0x0C0) = 0x04;
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#endif
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}
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int rt_hw_serial_init(void)
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{
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struct serial_configure config;
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poweron_per_domain();
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start_uart_clk();
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config_pinmux();
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#ifdef RT_USING_UART0
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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serial0.ops = &am33xx_uart_ops;
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serial0.config = config;
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/* enable RX interrupt */
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UART_IER_REG(uart0.base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart0.irq, am33xx_uart_isr, &serial0, "uart0");
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rt_hw_interrupt_control(uart0.irq, 0, 0);
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rt_hw_interrupt_mask(uart0.irq);
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/* register UART0 device */
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rt_hw_serial_register(&serial0, "uart0",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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&uart0);
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#endif
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#ifdef RT_USING_UART1
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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serial1.ops = &am33xx_uart_ops;
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serial1.config = config;
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/* enable RX interrupt */
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UART_IER_REG(uart1.base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart1.irq, am33xx_uart_isr, &serial1, "uart1");
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rt_hw_interrupt_control(uart1.irq, 0, 0);
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rt_hw_interrupt_mask(uart1.irq);
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/* register UART0 device */
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rt_hw_serial_register(&serial1, "uart1",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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&uart1);
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#endif
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#ifdef RT_USING_UART2
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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serial2.ops = &am33xx_uart_ops;
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serial2.config = config;
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/* enable RX interrupt */
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UART_IER_REG(uart2.base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart2.irq, am33xx_uart_isr, &serial2, "uart2");
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rt_hw_interrupt_control(uart2.irq, 0, 0);
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rt_hw_interrupt_mask(uart2.irq);
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/* register UART2 device */
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rt_hw_serial_register(&serial2, "uart2",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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&uart2);
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#endif
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#ifdef RT_USING_UART3
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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serial3.ops = &am33xx_uart_ops;
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serial3.config = config;
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/* enable RX interrupt */
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UART_IER_REG(uart3.base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart3.irq, am33xx_uart_isr, &serial3, "uart3");
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rt_hw_interrupt_control(uart3.irq, 0, 0);
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rt_hw_interrupt_mask(uart3.irq);
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/* register UART3 device */
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rt_hw_serial_register(&serial3, "uart3",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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&uart3);
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#endif
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#ifdef RT_USING_UART4
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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serial4.ops = &am33xx_uart_ops;
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serial4.config = config;
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/* enable RX interrupt */
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UART_IER_REG(uart4.base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart4.irq, am33xx_uart_isr, &serial4, "uart4");
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rt_hw_interrupt_control(uart4.irq, 0, 0);
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rt_hw_interrupt_mask(uart4.irq);
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/* register UART4 device */
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rt_hw_serial_register(&serial4, "uart4",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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&uart4);
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#endif
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#ifdef RT_USING_UART5
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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config.bufsz = RT_SERIAL_RB_BUFSZ;
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serial5.ops = &am33xx_uart_ops;
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serial5.config = config;
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/* enable RX interrupt */
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UART_IER_REG(uart5.base) = 0x01;
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/* install ISR */
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rt_hw_interrupt_install(uart5.irq, am33xx_uart_isr, &serial5, "uart5");
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rt_hw_interrupt_control(uart5.irq, 0, 0);
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rt_hw_interrupt_mask(uart5.irq);
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/* register UART4 device */
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rt_hw_serial_register(&serial5, "uart5",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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&uart5);
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#endif
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_serial_init);
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