372 lines
10 KiB
C
372 lines
10 KiB
C
#include <rthw.h>
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#include <rtthread.h>
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#include <jz4755.h>
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/**
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* @addtogroup Jz47xx
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*/
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/*@{*/
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#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
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#define UART_BAUDRATE 57600
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#define DEV_CLK 12000000
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/*
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* Define macros for UARTIER
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* UART Interrupt Enable Register
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*/
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#define UARTIER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
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#define UARTIER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
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#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
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#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
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#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
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/*
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* Define macros for UARTISR
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* UART Interrupt Status Register
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*/
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#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
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#define UARTISR_IID (7 << 1) /* Source of Interrupt */
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#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */
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#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
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#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */
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#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
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#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
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#define UARTISR_FFMS_NO_FIFO (0 << 6)
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#define UARTISR_FFMS_FIFO_MODE (3 << 6)
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/*
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* Define macros for UARTFCR
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* UART FIFO Control Register
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*/
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#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
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#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
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#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
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#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
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#define UARTFCR_UUE (1 << 4) /* 0: disable UART */
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#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
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#define UARTFCR_RTRG_1 (0 << 6)
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#define UARTFCR_RTRG_4 (1 << 6)
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#define UARTFCR_RTRG_8 (2 << 6)
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#define UARTFCR_RTRG_15 (3 << 6)
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/*
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* Define macros for UARTLCR
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* UART Line Control Register
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*/
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#define UARTLCR_WLEN (3 << 0) /* word length */
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#define UARTLCR_WLEN_5 (0 << 0)
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#define UARTLCR_WLEN_6 (1 << 0)
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#define UARTLCR_WLEN_7 (2 << 0)
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#define UARTLCR_WLEN_8 (3 << 0)
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#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
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1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
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#define UARTLCR_PE (1 << 3) /* 0: parity disable */
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#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
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#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */
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#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
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#define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */
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/*
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* Define macros for UARTLSR
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* UART Line Status Register
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*/
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#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
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#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */
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#define UARTLSR_PER (1 << 2) /* 0: no parity error */
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#define UARTLSR_FER (1 << 3) /* 0; no framing error */
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#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
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#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
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#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
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#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
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/*
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* Define macros for UARTMCR
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* UART Modem Control Register
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*/
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#define UARTMCR_DTR (1 << 0) /* 0: DTR_ ouput high */
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#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high */
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#define UARTMCR_OUT1 (1 << 2) /* 0: UARTMSR.RI is set to 0 and RI_ input high */
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#define UARTMCR_OUT2 (1 << 3) /* 0: UARTMSR.DCD is set to 0 and DCD_ input high */
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#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
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#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
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/*
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* Define macros for UARTMSR
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* UART Modem Status Register
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*/
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#define UARTMSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UARTMSR */
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#define UARTMSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UARTMSR */
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#define UARTMSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UARTMSR */
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#define UARTMSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UARTMSR */
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#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
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#define UARTMSR_DSR (1 << 5) /* 0: DSR_ pin is high */
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#define UARTMSR_RI (1 << 6) /* 0: RI_ pin is high */
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#define UARTMSR_DCD (1 << 7) /* 0: DCD_ pin is high */
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/*
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* Define macros for SIRCR
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* Slow IrDA Control Register
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*/
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#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
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#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
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#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
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1: 0 pulse width is 1.6us for 115.2Kbps */
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#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
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#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
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struct rt_uart_jz
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{
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struct rt_device parent;
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rt_uint32_t hw_base;
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rt_uint32_t irq;
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/* buffer for reception */
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rt_uint8_t read_index, save_index;
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rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
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}uart_device;
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static void rt_uart_irqhandler(int vector, void* param)
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{
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rt_ubase_t level, isr;
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struct rt_uart_jz* uart = param;
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/* read interrupt status and clear it */
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isr = UART_ISR(uart->hw_base);
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if (isr & UARTISR_IID_RDI) /* Receive Data Available */
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{
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/* Receive Data Available */
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while (UART_LSR(uart->hw_base) & UARTLSR_DR)
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{
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uart->rx_buffer[uart->save_index] = UART_RDR(uart->hw_base);
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level = rt_hw_interrupt_disable();
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uart->save_index ++;
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if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
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uart->save_index = 0;
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rt_hw_interrupt_enable(level);
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}
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/* invoke callback */
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if(uart->parent.rx_indicate != RT_NULL)
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{
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rt_size_t length;
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if (uart->read_index > uart->save_index)
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length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
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else
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length = uart->save_index - uart->read_index;
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uart->parent.rx_indicate(&uart->parent, length);
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}
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}
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return;
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}
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static rt_err_t rt_uart_init (rt_device_t dev)
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{
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rt_uint32_t baud_div;
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struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
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RT_ASSERT(uart != RT_NULL);
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/* Init UART Hardware */
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UART_IER(uart->hw_base) = 0; /* clear interrupt */
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UART_FCR(uart->hw_base) = ~UARTFCR_UUE; /* disable UART unite */
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/* Enable UART clock */
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/* Set both receiver and transmitter in UART mode (not SIR) */
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UART_SIRCR(uart->hw_base) = ~(SIRCR_RSIRE | SIRCR_TSIRE);
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/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
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UART_LCR(uart->hw_base) = UARTLCR_WLEN_8;
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/* set baudrate */
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baud_div = DEV_CLK / 16 / UART_BAUDRATE;
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UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
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UART_DLHR(uart->hw_base) = (baud_div >> 8) & 0xff;
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UART_DLLR(uart->hw_base) = baud_div & 0xff;
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UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
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/* Enable UART unit, enable and clear FIFO */
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UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
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return RT_EOK;
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}
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static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
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{
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struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
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RT_ASSERT(uart != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Enable the UART Interrupt */
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UART_IER(uart->hw_base) |= (UARTIER_RIE | UARTIER_RTIE);
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/* install interrupt */
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rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, uart, "uart");
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rt_hw_interrupt_umask(uart->irq);
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}
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return RT_EOK;
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}
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static rt_err_t rt_uart_close(rt_device_t dev)
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{
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struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
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RT_ASSERT(uart != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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/* Disable the UART Interrupt */
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UART_IER(uart->hw_base) &= ~(UARTIER_RIE | UARTIER_RTIE);
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}
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return RT_EOK;
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}
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static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_uint8_t* ptr;
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struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
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RT_ASSERT(uart != RT_NULL);
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/* point to buffer */
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ptr = (rt_uint8_t*) buffer;
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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while (size)
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{
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/* interrupt receive */
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rt_base_t level;
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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if (uart->read_index != uart->save_index)
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{
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*ptr = uart->rx_buffer[uart->read_index];
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uart->read_index ++;
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if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
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uart->read_index = 0;
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}
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else
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{
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/* no data in rx buffer */
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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break;
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}
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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ptr ++;
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size --;
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}
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return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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}
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return 0;
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}
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static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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char *ptr;
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struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
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RT_ASSERT(uart != RT_NULL);
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ptr = (char*)buffer;
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if (dev->flag & RT_DEVICE_FLAG_STREAM)
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{
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/* stream mode */
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while (size)
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{
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if (*ptr == '\n')
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{
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/* FIFO status, contain valid data */
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while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
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/* write data */
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UART_TDR(uart->hw_base) = '\r';
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}
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/* FIFO status, contain valid data */
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while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
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/* write data */
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UART_TDR(uart->hw_base) = *ptr;
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ptr ++;
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size --;
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}
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}
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else
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{
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while ( size != 0 )
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{
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/* FIFO status, contain valid data */
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while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
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/* write data */
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UART_TDR(uart->hw_base) = *ptr;
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ptr++;
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size--;
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}
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}
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return (rt_size_t) ptr - (rt_size_t) buffer;
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}
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void rt_hw_uart_init(void)
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{
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struct rt_uart_jz* uart;
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/* get uart device */
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uart = &uart_device;
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/* device initialization */
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uart->parent.type = RT_Device_Class_Char;
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rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
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uart->read_index = uart->save_index = 0;
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#if defined(RT_USING_UART0)
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uart->hw_base = UART0_BASE;
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uart->irq = IRQ_UART0;
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#elif defined(RT_USING_UART1)
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uart->hw_base = UART1_BASE;
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uart->irq = IRQ_UART1;
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#elif defined(RT_USING_UART2)
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uart->hw_base = UART2_BASE;
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uart->irq = IRQ_UART2;
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#elif defined(RT_USING_UART3)
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uart->hw_base = UART3_BASE;
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uart->irq = IRQ_UART3;
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#endif
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/* device interface */
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uart->parent.init = rt_uart_init;
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uart->parent.open = rt_uart_open;
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uart->parent.close = rt_uart_close;
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uart->parent.read = rt_uart_read;
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uart->parent.write = rt_uart_write;
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uart->parent.control = RT_NULL;
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uart->parent.user_data = RT_NULL;
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rt_device_register(&uart->parent,
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"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
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}
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#endif /* end of UART */
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/*@}*/
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