454 lines
19 KiB
C
454 lines
19 KiB
C
/**********************************************************************
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* $Id$ lpc_gpdma.c 2011-06-02
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*//**
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* @file lpc_gpdma.c
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* @brief Contains all functions support for GPDMA firmware library
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* on LPC
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* @version 1.0
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* @date 02. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors'
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @addtogroup GPDMA
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* @{
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*/
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#ifdef __BUILD_WITH_EXAMPLE__
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#include "lpc_libcfg.h"
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#else
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#include "lpc_libcfg_default.h"
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#endif /* __BUILD_WITH_EXAMPLE__ */
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#ifdef _GPDMA
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/* Includes ------------------------------------------------------------------- */
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#include "lpc_gpdma.h"
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#include "lpc_clkpwr.h"
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/* Private Variables ---------------------------------------------------------- */
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/** @defgroup GPDMA_Private_Variables GPDMA Private Variables
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* @{
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*/
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/**
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* @brief Lookup Table of Connection Type matched with
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* Peripheral Data (FIFO) register base address
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*/
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volatile const void *GPDMA_LUTPerAddr[] = {
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0, // Revered
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(&LPC_MCI->FIFO), // SD Card
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(&LPC_SSP0->DR), // SSP0 Tx
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(&LPC_SSP0->DR), // SSP0 Rx
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(&LPC_SSP1->DR), // SSP1 Tx
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(&LPC_SSP1->DR), // SSP1 Rx
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(&LPC_SSP2->DR), // SSP2 Tx
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(&LPC_SSP2->DR), // SSP2 Rx
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(&LPC_ADC->GDR), // ADC
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(&LPC_DAC->CR), // DAC
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(&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
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(&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
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(&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
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(&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
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(&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
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(&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
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(&LPC_TIM0->MR0), // MAT0.0
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(&LPC_TIM0->MR1), // MAT0.1
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(&LPC_TIM1->MR0), // MAT1.0
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(&LPC_TIM1->MR1), // MAT1.1
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(&LPC_TIM2->MR0), // MAT2.0
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(&LPC_TIM2->MR1), // MAT2.1
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(&LPC_I2S->TXFIFO), // I2S Tx
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(&LPC_I2S->RXFIFO), // I2S Rx
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0, // Reverse
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0, // Reverse
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(&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
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(&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
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(&LPC_UART4->/*RBTHDLR.*/THR), // UART4 Tx
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(&LPC_UART4->/*RBTHDLR.*/RBR), // UART4 Rx
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(&LPC_TIM3->MR0), // MAT3.0
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(&LPC_TIM3->MR1), // MAT3.1
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};
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/**
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* @brief Lookup Table of GPDMA Channel Number matched with
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* GPDMA channel pointer
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*/
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const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
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LPC_GPDMACH0, // GPDMA Channel 0
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LPC_GPDMACH1, // GPDMA Channel 1
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LPC_GPDMACH2, // GPDMA Channel 2
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LPC_GPDMACH3, // GPDMA Channel 3
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LPC_GPDMACH4, // GPDMA Channel 4
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LPC_GPDMACH5, // GPDMA Channel 5
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LPC_GPDMACH6, // GPDMA Channel 6
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LPC_GPDMACH7, // GPDMA Channel 7
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};
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/**
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* @brief Optimized Peripheral Source and Destination burst size
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*/
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const uint8_t GPDMA_LUTPerBurst[] = {
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0, // Reserved
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GPDMA_BSIZE_8, // SD Card
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GPDMA_BSIZE_4, // SSP0 Tx
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GPDMA_BSIZE_4, // SSP0 Rx
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GPDMA_BSIZE_4, // SSP1 Tx
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GPDMA_BSIZE_4, // SSP1 Rx
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GPDMA_BSIZE_4, // SSP2 Tx
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GPDMA_BSIZE_4, // SSP2 Rx
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GPDMA_BSIZE_1, // ADC
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GPDMA_BSIZE_1, // DAC
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GPDMA_BSIZE_1, // UART0 Tx
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GPDMA_BSIZE_1, // UART0 Rx
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GPDMA_BSIZE_1, // UART1 Tx
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GPDMA_BSIZE_1, // UART1 Rx
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GPDMA_BSIZE_1, // UART2 Tx
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GPDMA_BSIZE_1, // UART2 Rx
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GPDMA_BSIZE_1, // MAT0.0
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GPDMA_BSIZE_1, // MAT0.1
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GPDMA_BSIZE_1, // MAT1.0
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GPDMA_BSIZE_1, // MAT1.1
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GPDMA_BSIZE_1, // MAT2.0
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GPDMA_BSIZE_1, // MAT2.1
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GPDMA_BSIZE_32, // I2S channel 0
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GPDMA_BSIZE_32, // I2S channel 1
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0, // Reserved
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0, // Reserved
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GPDMA_BSIZE_1, // UART3 Tx
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GPDMA_BSIZE_1, // UART3 Rx
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GPDMA_BSIZE_1, // UART4 Tx
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GPDMA_BSIZE_1, // UART4 Rx
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GPDMA_BSIZE_1, // MAT3.0
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GPDMA_BSIZE_1, // MAT3.1
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};
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/**
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* @brief Optimized Peripheral Source and Destination transfer width
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*/
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const uint8_t GPDMA_LUTPerWid[] = {
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0, // Reserved
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GPDMA_WIDTH_WORD, // SD Card
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GPDMA_WIDTH_BYTE, // SSP0 Tx
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GPDMA_WIDTH_BYTE, // SSP0 Rx
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GPDMA_WIDTH_BYTE, // SSP1 Tx
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GPDMA_WIDTH_BYTE, // SSP1 Rx
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GPDMA_WIDTH_BYTE, // SSP2 Tx
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GPDMA_WIDTH_BYTE, // SSP2 Rx
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GPDMA_WIDTH_WORD, // ADC
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GPDMA_WIDTH_BYTE, // DAC
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GPDMA_WIDTH_BYTE, // UART0 Tx
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GPDMA_WIDTH_BYTE, // UART0 Rx
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GPDMA_WIDTH_BYTE, // UART1 Tx
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GPDMA_WIDTH_BYTE, // UART1 Rx
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GPDMA_WIDTH_BYTE, // UART2 Tx
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GPDMA_WIDTH_BYTE, // UART2 Rx
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GPDMA_WIDTH_WORD, // MAT0.0
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GPDMA_WIDTH_WORD, // MAT0.1
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GPDMA_WIDTH_WORD, // MAT1.0
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GPDMA_WIDTH_WORD, // MAT1.1
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GPDMA_WIDTH_WORD, // MAT2.0
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GPDMA_WIDTH_WORD, // MAT2.1
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GPDMA_WIDTH_WORD, // I2S channel 0
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GPDMA_WIDTH_WORD, // I2S channel 1
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0, // Reserved
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0, // Reserved
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GPDMA_WIDTH_BYTE, // UART3 Tx
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GPDMA_WIDTH_BYTE, // UART3 Rx
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GPDMA_WIDTH_BYTE, // UART4 Tx
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GPDMA_WIDTH_BYTE, // UART4 Rx
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GPDMA_WIDTH_WORD, // MAT3.0
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GPDMA_WIDTH_WORD, // MAT3.1
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};
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @addtogroup GPDMA_Public_Functions
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* @{
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*/
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/********************************************************************//**
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* @brief Initialize GPDMA controller
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* @param None
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* @return None
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*********************************************************************/
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void GPDMA_Init(void)
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{
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/* Enable GPDMA clock */
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CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
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// Reset all channel configuration register
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LPC_GPDMACH0->CConfig = 0;
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LPC_GPDMACH1->CConfig = 0;
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LPC_GPDMACH2->CConfig = 0;
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LPC_GPDMACH3->CConfig = 0;
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LPC_GPDMACH4->CConfig = 0;
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LPC_GPDMACH5->CConfig = 0;
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LPC_GPDMACH6->CConfig = 0;
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LPC_GPDMACH7->CConfig = 0;
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/* Clear all DMA interrupt and error flag */
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LPC_GPDMA->IntTCClear = 0xFF;
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LPC_GPDMA->IntErrClr = 0xFF;
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}
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/********************************************************************//**
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* @brief Setup GPDMA channel peripheral according to the specified
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* parameters in the GPDMAChannelConfig.
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* @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
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* structure that contains the configuration
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* information for the specified GPDMA channel peripheral.
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* @return ERROR if selected channel is enabled before
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* or SUCCESS if channel is configured successfully
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*********************************************************************/
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Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
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{
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LPC_GPDMACH_TypeDef *pDMAch;
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uint32_t tmp1, tmp2;
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if (LPC_GPDMA->EnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
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// This channel is enabled, return ERROR, need to release this channel first
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return ERROR;
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}
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// Get Channel pointer
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pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
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// Reset the Interrupt status
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LPC_GPDMA->IntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
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LPC_GPDMA->IntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
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// Clear DMA configure
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pDMAch->CControl = 0x00;
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pDMAch->CConfig = 0x00;
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/* Assign Linker List Item value */
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pDMAch->CLLI = GPDMAChannelConfig->DMALLI;
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/* Set value to Channel Control Registers */
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switch (GPDMAChannelConfig->TransferType)
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{
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// Memory to memory
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case GPDMA_TRANSFERTYPE_M2M:
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// Assign physical source and destination address
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pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
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pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
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pDMAch->CControl
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= GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
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| GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
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| GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
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| GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
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| GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
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| GPDMA_DMACCxControl_SI \
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| GPDMA_DMACCxControl_DI \
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| GPDMA_DMACCxControl_I;
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break;
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// Memory to peripheral
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case GPDMA_TRANSFERTYPE_M2P:
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case GPDMA_TRANSFERTYPE_M2P_DEST_CTRL:
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// Assign physical source
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pDMAch->CSrcAddr = GPDMAChannelConfig->SrcMemAddr;
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// Assign peripheral destination address
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pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
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pDMAch->CControl
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= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
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| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
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| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
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| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
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| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
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| GPDMA_DMACCxControl_SI \
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| GPDMA_DMACCxControl_I;
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break;
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// Peripheral to memory
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case GPDMA_TRANSFERTYPE_P2M:
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case GPDMA_TRANSFERTYPE_P2M_SRC_CTRL:
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// Assign peripheral source address
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pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
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// Assign memory destination address
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pDMAch->CDestAddr = GPDMAChannelConfig->DstMemAddr;
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pDMAch->CControl
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= GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
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| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
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| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
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| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
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| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
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| GPDMA_DMACCxControl_DI \
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| GPDMA_DMACCxControl_I;
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break;
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// Peripheral to peripheral
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case GPDMA_TRANSFERTYPE_P2P:
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// Assign peripheral source address
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pDMAch->CSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
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// Assign peripheral destination address
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pDMAch->CDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
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pDMAch->CControl = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
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| GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
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| GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
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| GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
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| GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
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| GPDMA_DMACCxControl_I;
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break;
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// Do not support any more transfer type, return ERROR
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default:
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return ERROR;
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}
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/* Re-Configure DMA Request Select for source peripheral */
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if((GPDMAChannelConfig->SrcConn != 8)&&(GPDMAChannelConfig->SrcConn != 9))
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{
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if (GPDMAChannelConfig->SrcConn > 15)
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{
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LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16));
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} else {
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LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn));
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}
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}
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/* Re-Configure DMA Request Select for Destination peripheral */
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if((GPDMAChannelConfig->DstConn != 8)&&(GPDMAChannelConfig->DstConn != 9))
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{
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if (GPDMAChannelConfig->DstConn > 15)
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{
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LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16));
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} else {
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LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn));
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}
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}
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/* Enable DMA channels, little endian */
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LPC_GPDMA->Config = GPDMA_DMACConfig_E;
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while (!(LPC_GPDMA->Config & GPDMA_DMACConfig_E));
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// Calculate absolute value for Connection number
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tmp1 = GPDMAChannelConfig->SrcConn;
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tmp1 = ((tmp1 > 15) ? (tmp1 - 16) : tmp1);
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tmp2 = GPDMAChannelConfig->DstConn;
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tmp2 = ((tmp2 > 15) ? (tmp2 - 16) : tmp2);
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// Configure DMA Channel, enable Error Counter and Terminate counter
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pDMAch->CConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
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| GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
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| GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
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| GPDMA_DMACCxConfig_DestPeripheral(tmp2);
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return SUCCESS;
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}
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/*********************************************************************//**
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* @brief Enable/Disable DMA channel
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* @param[in] channelNum GPDMA channel, should be in range from 0 to 7
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* @param[in] NewState New State of this command, should be:
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* - ENABLE.
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* - DISABLE.
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* @return None
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**********************************************************************/
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void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
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{
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LPC_GPDMACH_TypeDef *pDMAch;
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// Get Channel pointer
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pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
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if (NewState == ENABLE) {
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pDMAch->CConfig |= GPDMA_DMACCxConfig_E;
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} else {
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pDMAch->CConfig &= ~GPDMA_DMACCxConfig_E;
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}
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}
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/*********************************************************************//**
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* @brief Check if corresponding channel does have an active interrupt
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* request or not
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* @param[in] type type of status, should be:
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* - GPDMA_STAT_INT: GPDMA Interrupt Status
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* - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status
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* - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status
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* - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status
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* - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status
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* - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
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* @param[in] channel GPDMA channel, should be in range from 0 to 7
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* @return IntStatus status of DMA channel interrupt after masking
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* Should be:
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* - SET: the corresponding channel has no active interrupt request
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* - RESET: the corresponding channel does have an active interrupt request
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**********************************************************************/
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IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
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{
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switch (type)
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{
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case GPDMA_STAT_INT: //check status of DMA channel interrupts
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if (LPC_GPDMA->IntStat & (GPDMA_DMACIntStat_Ch(channel)))
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return SET;
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return RESET;
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case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
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if (LPC_GPDMA->IntTCStat & GPDMA_DMACIntTCStat_Ch(channel))
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return SET;
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return RESET;
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case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
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if (LPC_GPDMA->IntErrStat & GPDMA_DMACIntTCClear_Ch(channel))
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return SET;
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return RESET;
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case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
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if (LPC_GPDMA->RawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel))
|
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return SET;
|
|
return RESET;
|
|
case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
|
|
if (LPC_GPDMA->RawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel))
|
|
return SET;
|
|
return RESET;
|
|
default: //check enable status for DMA channels
|
|
if (LPC_GPDMA->EnbldChns & GPDMA_DMACEnbldChns_Ch(channel))
|
|
return SET;
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Clear one or more interrupt requests on DMA channels
|
|
* @param[in] type type of interrupt request, should be:
|
|
* - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear
|
|
* - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
|
|
* @param[in] channel GPDMA channel, should be in range from 0 to 7
|
|
* @return None
|
|
**********************************************************************/
|
|
void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
|
|
{
|
|
if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
|
|
LPC_GPDMA->IntTCClear = GPDMA_DMACIntTCClear_Ch(channel);
|
|
else // clear the error interrupt request
|
|
LPC_GPDMA->IntErrClr = GPDMA_DMACIntErrClr_Ch(channel);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* _GPDMA */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/* --------------------------------- End Of File ------------------------------ */
|
|
|