6 Commits

Author	SHA1	Message	Date
zhangjun	a5305c05df	fix bug in context_gcc.s and start_gcc.s: ... save mie into stack msh running normaly	2017-07-31 10:59:59 +08:00
zhangjun	b032dff161	fix bug in rt_hw_context_switch_interrupt_do ... save sp to old thread clear rt_thread_switch_interrupt_flag always enable interrupt after rt_hw_context_switch judeg the type of interrupt in trap_entry, then call handler(Machine timer interrupt of Machine external interrupt)	2017-07-30 19:46:28 +08:00
zhangjun	2d56a27c20	修改： ../../libcpu/risc-v/e310/context_gcc.S ... enable interrupt after return form rt_hw_context_switch	2017-07-30 15:34:32 +08:00
zhangjun	3c51848d33	fix trap_entry	2017-07-29 15:37:20 +08:00
zhangjun	98a6896cfa	remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable(); ... it will lead to interrupt again in interrupt	2017-07-26 16:07:01 +08:00
zhangjun	e01455155a	add context_gcc.s	2017-07-17 15:44:00 +08:00