zhangjun
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2d56a27c20
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修改： ../../libcpu/risc-v/e310/context_gcc.S
enable interrupt after return form rt_hw_context_switch
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2017-07-30 15:34:32 +08:00 |
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zhangjun
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3c51848d33
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fix trap_entry
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2017-07-29 15:37:20 +08:00 |
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zhangjun
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b80f83f360
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modified: ../../libcpu/risc-v/e310/context_gcc.S
fix open timer intrrupt
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2017-07-26 16:27:54 +08:00 |
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zhangjun
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98a6896cfa
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remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();
it will lead to interrupt again in interrupt
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2017-07-26 16:07:01 +08:00 |
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zhangjun
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b334347a24
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deleted: rtthread.s /*just for debug*/
modified: ../../libcpu/risc-v/e310/context_gcc.S
change ret to mret and switch to new task with mepc
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2017-07-17 16:55:33 +08:00 |
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zhangjun
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e01455155a
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add context_gcc.s
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2017-07-17 15:44:00 +08:00 |
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zhangjun
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f147f3398a
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new bsp for risc-v
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2017-07-16 20:37:03 +08:00 |