modified start_gcc.s, and added lowlevel_init.S to initialize sdram.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@493 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
gary.li.wenchao.4
parent
8967a4d298
commit
e9e205a29c
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@ -0,0 +1,137 @@
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-03-16 Gary Lee the first version
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*/
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#define BWSCON 0x48000000
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/* BWSCON */
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#define DW8 (0x0)
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#define DW16 (0x1)
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#define DW32 (0x2)
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#define WAIT (0x1<<2)
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#define UBLB (0x1<<3)
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#define B1_BWSCON (DW16)
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#define B2_BWSCON (DW16)
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#define B3_BWSCON (DW16 + WAIT + UBLB)
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#define B4_BWSCON (DW16)
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#define B5_BWSCON (DW16)
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#define B6_BWSCON (DW32)
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#define B7_BWSCON (DW32)
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#define B0_Tacs 0x0
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#define B0_Tcos 0x0
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#define B0_Tacc 0x7
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#define B0_Tcoh 0x0
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#define B0_Tah 0x0
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#define B0_Tacp 0x0
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#define B0_PMC 0x0
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#define B1_Tacs 0x0
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#define B1_Tcos 0x0
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#define B1_Tacc 0x7
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#define B1_Tcoh 0x0
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#define B1_Tah 0x0
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#define B1_Tacp 0x0
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#define B1_PMC 0x0
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#define B2_Tacs 0x0
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#define B2_Tcos 0x0
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#define B2_Tacc 0x7
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#define B2_Tcoh 0x0
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#define B2_Tah 0x0
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#define B2_Tacp 0x0
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#define B2_PMC 0x0
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#define B3_Tacs 0xc
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#define B3_Tcos 0x7
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#define B3_Tacc 0xf
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#define B3_Tcoh 0x1
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#define B3_Tah 0x0
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#define B3_Tacp 0x0
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#define B3_PMC 0x0
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#define B4_Tacs 0x0
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#define B4_Tcos 0x0
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#define B4_Tacc 0x7
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#define B4_Tcoh 0x0
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#define B4_Tah 0x0
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#define B4_Tacp 0x0
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#define B4_PMC 0x0
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#define B5_Tacs 0xc
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#define B5_Tcos 0x7
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#define B5_Tacc 0xf
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#define B5_Tcoh 0x1
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#define B5_Tah 0x0
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#define B5_Tacp 0x0
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#define B5_PMC 0x0
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#define B6_MT 0x3 /* SDRAM */
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#define B6_Trcd 0x1
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#define B6_SCAN 0x1 /* 9bit */
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#define B7_MT 0x3 /* SDRAM */
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#define B7_Trcd 0x1 /* 3clk */
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#define B7_SCAN 0x1 /* 9bit */
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/* REFRESH parameter */
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#define REFEN 0x1 /* Refresh enable */
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#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
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#define Trc 0x3 /* 7clk */
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#define Tchr 0x2 /* 3clk */
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#define Trp 0x2 /* 4clk */
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#define REFCNT 1012
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/**************************************/
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.globl lowlevel_init
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lowlevel_init:
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/* memory control configuration */
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/* make r0 relative the current location so that it */
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/* reads SMRDATA out of FLASH rather than memory ! */
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ldr r0, =SMRDATA
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ldr r1, =lowlevel_init
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sub r0, r0, r1
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adr r3, lowlevel_init /* r3 <- current position of code */
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add r0, r0, r3
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ldr r1, =BWSCON /* Bus Width Status Controller */
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add r2, r0, #13*4
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0:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r2, r0
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bne 0b
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/* everything is fine now */
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mov pc, lr
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.ltorg
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/* the literal pools origin */
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SMRDATA:
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.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
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.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
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.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
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.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
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.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
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.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
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.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
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.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
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.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
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.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
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.word 0xb2
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.word 0x30
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.word 0x30
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@ -12,6 +12,7 @@
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* 2006-03-13 Bernard first version
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* 2006-10-05 Alsor.Z for s3c2440 initialize
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* 2008-01-29 Yi.Qiu for QEMU emulator
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* 2010-03-15 Gary Lee Modified the structure of startcode
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*/
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#define CONFIG_STACKSIZE 512
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@ -37,6 +38,10 @@
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#define S_R1 4
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#define S_R0 0
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#define CLK_CTL_BASE 0x4C000000 /* Gary Lee */
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#define MDIV_405 0x7f << 12 /* Gary Lee */
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#define PSDIV_405 0x21 /* Gary Lee */
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.equ USERMODE, 0x10
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.equ FIQMODE, 0x11
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.equ IRQMODE, 0x12
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@ -105,7 +110,7 @@ _vector_resv: .word vector_resv
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_vector_irq: .word vector_irq
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_vector_fiq: .word vector_fiq
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.balignl 16,0xdeadbeef
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.balignl 16, 0xdeadbeef
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/*
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*************************************************************************
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@ -117,25 +122,20 @@ _vector_fiq: .word vector_fiq
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*
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*************************************************************************
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*/
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_TEXT_BASE:
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_TEXT_BASE: /* TEXT_BASE was defined in rtconfig.py */
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.word TEXT_BASE
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/*
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* rtthread kernel start and end
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* which are defined in linker script
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*/
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/* rtthread kernel start and end which are defined in linker script */
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.globl _rtthread_start
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_rtthread_start:
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.word _start
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/* _end was defined in link script */
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.globl _rtthread_end
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_rtthread_end:
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.word _end
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/*
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* rtthread bss start and end which are defined in linker script
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*/
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/* rtthread bss start and end which are defined in linker script */
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.globl _bss_start
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_bss_start:
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.word __bss_start
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_STACK_START:
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.word _svc_stack_start + 4096
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/* ----------------------------------entry------------------------------*/
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reset:
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.globl _load_address
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#if defined (__FLASH_BUILD__)
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_load_address:
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.word ROM_BASE + _TEXT_BASE
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#else
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_load_address:
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.word RAM_BASE + _TEXT_BASE
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#endif
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/*
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*************************************************************************
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* Actual start (entry point)
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*************************************************************************
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*/
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reset:
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bl mode_svn32
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bl watchdog_disable
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bl interrupt_disable
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bl sys_clock_setup
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bl cpu_crit_init
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bl interrupt_vector_setup
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bl stack_setup
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bl bss_clear
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq kernel_start
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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kernel_start:
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup:
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.word rtthread_startup
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/*
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*************************************************************************
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* Subroutines
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*************************************************************************
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*/
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/* set the cpu to SVC32 mode */
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mrs r0,cpsr
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bic r0,r0,#MODEMASK
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orr r0,r0,#SVCMODE
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msr cpsr,r0
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mode_svn32:
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mrs r0, cpsr
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bic r0, r0,#MODEMASK
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orr r0, r0,#SVCMODE
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msr cpsr, r0
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mov pc, lr
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/* watch dog disable */
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ldr r0,=WTCON
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ldr r1,=0x0
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str r1,[r0]
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watchdog_disable:
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ldr r0, =WTCON
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ldr r1, =0x0
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str r1, [r0]
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mov pc, lr
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/* mask all IRQs by clearing all bits in the INTMRs */
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interrupt_disable:
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ldr r1, =INTMSK
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ldr r0, =0xffffffff
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str r0, [r1]
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@ -187,8 +239,50 @@ reset:
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ldr r0, =0x7fff /*all sub interrupt disable */
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str r0, [r1]
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mov pc, lr
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sys_clock_setup: /* FCLK:HCLK:PCLK = 1:4:8 */
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ldr r0, =CLKDIVN
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mov r1, #5
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str r1, [r0]
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mrc p15, 0, r1, c1, c0, 0 /* switch to asynchronous mode */
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orr r1, r1, #0xc0000000
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mcr p15, 0, r1, c1, c0, 0
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mov r1, #CLK_CTL_BASE
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mov r2, #MDIV_405
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add r2, r2, #PSDIV_405
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str r2, [r1, #0x04] /* MPLLCON Gary Lee */
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mov pc, lr
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/*==============================================================================*/
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cpu_crit_init:
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/* flush v4 I/D caches */
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/* disable MMU stuff and caches */
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
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bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
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orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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mov ip, lr
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bl lowlevel_init
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mov lr, ip
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mov pc, lr
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/* set interrupt vector */
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ldr r0, _load_address
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interrupt_vector_setup:
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ldr r0, _load_address /* _load_address = 0x30000000 */
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mov r1, #0x0 /* target address */
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add r2, r0, #0x20 /* size, 32bytes */
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@ -198,10 +292,39 @@ copy_loop:
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cmp r0, r2 /* until source end addreee [r2] */
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ble copy_loop
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/* setup stack */
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bl stack_setup
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mov pc, lr
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stack_setup:
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mrs r0, cpsr
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bic r0, r0, #MODEMASK
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orr r1, r0, #UNDEFMODE|NOINT
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msr cpsr_cxsf, r1 /* undef mode */
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ldr sp, UNDEFINED_STACK_START
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orr r1,r0,#ABORTMODE|NOINT
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msr cpsr_cxsf,r1 /* abort mode */
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ldr sp, ABORT_STACK_START
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orr r1,r0,#IRQMODE|NOINT
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msr cpsr_cxsf,r1 /* IRQ mode */
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ldr sp, IRQ_STACK_START
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orr r1,r0,#FIQMODE|NOINT
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msr cpsr_cxsf,r1 /* FIQ mode */
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ldr sp, FIQ_STACK_START
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bic r0,r0,#MODEMASK
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orr r1,r0,#SVCMODE|NOINT
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msr cpsr_cxsf,r1 /* SVC mode */
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ldr sp, _STACK_START
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/* USER mode is not initialized. */
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mov pc,lr /* The LR register may be not valid for the mode changes.*/
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/* clear .bss */
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bss_clear:
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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@ -211,34 +334,7 @@ bss_loop:
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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_rtthread_startup:
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.word rtthread_startup
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#if defined (__FLASH_BUILD__)
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_load_address:
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.word ROM_BASE + _TEXT_BASE
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#else
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_load_address:
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.word RAM_BASE + _TEXT_BASE
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#endif
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mov pc, lr
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/*
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*************************************************************************
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@ -358,33 +454,4 @@ _interrupt_thread_switch:
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ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
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stack_setup:
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mrs r0, cpsr
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bic r0, r0, #MODEMASK
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orr r1, r0, #UNDEFMODE|NOINT
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msr cpsr_cxsf, r1 /* undef mode */
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ldr sp, UNDEFINED_STACK_START
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orr r1,r0,#ABORTMODE|NOINT
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msr cpsr_cxsf,r1 /* abort mode */
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ldr sp, ABORT_STACK_START
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orr r1,r0,#IRQMODE|NOINT
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msr cpsr_cxsf,r1 /* IRQ mode */
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ldr sp, IRQ_STACK_START
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orr r1,r0,#FIQMODE|NOINT
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msr cpsr_cxsf,r1 /* FIQ mode */
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ldr sp, FIQ_STACK_START
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bic r0,r0,#MODEMASK
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orr r1,r0,#SVCMODE|NOINT
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msr cpsr_cxsf,r1 /* SVC mode */
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ldr sp, _STACK_START
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/* USER mode is not initialized. */
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mov pc,lr /* The LR register may be not valid for the mode changes.*/
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/*/*}*/
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