chinky/rtt-f030
chinky/rtt-f030
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Merge branch 'master' into develop

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This commit is contained in:
chinky 2018-08-28 00:53:20 +08:00
commit dd5a60885c
85 changed files with 7348 additions and 1467 deletions
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1263
bsp/ls1cdev/drivers/net/synopGMAC.c
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File diff suppressed because it is too large Load Diff

20
bsp/qemu-vexpress-a9/.config
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@ -74,6 +74,7 @@ CONFIG_ARCH_ARM_CORTEX_A9=y
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
@ -107,6 +108,7 @@ CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
@ -251,11 +253,18 @@ CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_DEBUG is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
@ -293,7 +302,6 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
#
# Wi-Fi
@ -311,9 +319,15 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
#
# security packages
#
@ -362,10 +376,12 @@ CONFIG_LOG_TRACE_USING_LEVEL_INFO=y
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set

96
bsp/qemu-vexpress-a9/.vscode/launch.json vendored Normal file
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@ -0,0 +1,96 @@
{
"version": "0.2.0",
"configurations": [
{
"name": "Debug @ Mac/Linux",
"type": "cppdbg",
"request": "launch",
"program": "${workspaceRoot}/rtthread.elf",
"args": [],
"stopAtEntry": true,
"cwd": "${workspaceRoot}",
"environment": [],
"externalConsole": true,
"miDebuggerServerAddress": "localhost:1234",
"serverLaunchTimeout": 2000,
"targetArchitecture": "ARM",
"setupCommands": [
{
"text": "cd ${workspaceRoot}"
},
{
"text": "shell qemu-dbg.sh"
},
{
"text": "target remote localhost:1234"
},
{
"text": "file rtthread.elf"
},
{
"text": "break application_start"
}
],
"customLaunchSetupCommands": [],
"launchCompleteCommand": "exec-run",
"preLaunchTask": "qemu debug",
"osx": {
"MIMode": "gdb",
"miDebuggerPath": "arm-none-eabi-gdb"
},
"linux": {
"MIMode": "gdb",
"miDebuggerPath": "arm-none-eabi-gdb"
},
"windows": {
"MIMode": "gdb",
"miDebuggerPath": "arm-none-eabi-gdb.exe"
}
},
{
"name": "Debug @ Windows",
"type": "cppdbg",
"request": "launch",
"program": "${workspaceRoot}\\rtthread.elf",
"args": [],
"stopAtEntry": true,
"cwd": "${workspaceRoot}",
"environment": [],
"externalConsole": true,
"miDebuggerServerAddress": "localhost:1234",
"serverLaunchTimeout": 2000,
"targetArchitecture": "ARM",
"setupCommands": [
{
"text": "cd ${workspaceRoot}"
},
{
"text": "shell qemu-dbg.bat"
},
{
"text": "target remote localhost:1234"
},
{
"text": "file rtthread.elf"
},
{
"text": "break main"
}
],
"customLaunchSetupCommands": [],
"launchCompleteCommand": "exec-run",
"osx": {
"MIMode": "gdb",
"miDebuggerPath": "arm-none-eabi-gdb"
},
"linux": {
"MIMode": "gdb",
"miDebuggerPath": "arm-none-eabi-gdb"
},
"windows": {
"MIMode": "gdb",
"miDebuggerPath": "arm-none-eabi-gdb.exe"
}
},
]
}

10
bsp/qemu-vexpress-a9/.vscode/settings.json vendored Normal file
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@ -0,0 +1,10 @@
{
"C_Cpp.dimInactiveRegions": false,
"files.exclude": {
"**/.git": true,
"**/GPUCache" : true,
"**/build" : true,
"**/*.pyc" : true
},
"editor.renderWhitespace": "all"
}

45
bsp/qemu-vexpress-a9/.vscode/tasks.json vendored Normal file
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@ -0,0 +1,45 @@
{
// See https://go.microsoft.com/fwlink/?LinkId=733558
// for the documentation about the tasks.json format
"version": "2.0.0",
"tasks": [
{
"label": "build",
"type": "shell",
"command": "scons",
"problemMatcher": [
"$gcc"
],
"presentation": {
"echo": true,
"reveal": "always",
"focus": true,
"panel": "shared",
"showReuseMessage": true
},
"group": {
"kind": "build",
"isDefault": true
}
},
{
"label": "clean",
"type": "shell",
"command": "scons -c",
"problemMatcher": [],
"presentation": {
"echo": true,
"reveal": "always",
"focus": true,
"panel": "shared",
"showReuseMessage": true
}
},
{
"label": "qemu simulator",
"type": "shell",
"command": "qemu.bat",
"problemMatcher" : []
}
]
}

38
bsp/qemu-vexpress-a9/README.md
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@ -60,10 +60,46 @@ msh />
| Mouse | 支持 | |
| EMAC | 支持 | |
### 4.1 使用VSCode编辑、编译、调试
在qemu-vexpress-a9中已经携带了部分vscode的配置，需要配合着env一起来使用。步骤包括：
先使用env打开console，然后在console中切换都qemu-vexpress-a9 bsp的目录下，
```bash
scons --target=vsc -s
```
更新vscode需要用到的C/C++头文件搜索路径信息（不是每次都需要更新，只有在使用了menuconfig重新配置了RT-Thread或更改了rtconfig.h头文件时才需要）
然后在console下输入
```bash
code .
```
启动vscode。使用vscode，目前包含如下的一些功能：
* 编译 `Ctrl+Shift+B` - 开启vscode内置终端，调用scons进行编译；如果有编译错误也会侦测问题，双击问题跳到指定代码文件、代码行；
* 包含执行`qemu`模拟器，`scons -c`进行目标文件清理的任务
* `F5` 一键开启QEMU调试模式，并断点停留在`main`函数上；(需要更改下qemu-dbg.bat文件，在qemu-system-arm前加入`start`)，即
```batch
@echo off
if exist sd.bin goto run
qemu-img create -f raw sd.bin 64M
:run
start qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial stdio -sd sd.bin -S -s
```
**已知问题** 如果在vscode的目录中额外添加了文件夹，会导致调试不能够启动。
## 5. 联系人信息
维护人：bernard
维护人：[bernard][4]
[1]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.boards.express/index.html
[2]: https://www.rt-thread.org/page/download.html
[3]: https://launchpad.net/gcc-arm-embedded/5.0/5-2016-q3-update/+download/gcc-arm-none-eabi-5_4-2016q3-20160926-linux.tar.bz2
[4]: https://github.com/BernardXiong

2
bsp/qemu-vexpress-a9/qemu-dbg.bat
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@ -3,4 +3,4 @@ if exist sd.bin goto run
qemu-img create -f raw sd.bin 64M
:run
qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial vc -serial vc -sd sd.bin -S -s
qemu-system-arm -M vexpress-a9 -kernel rtthread.elf -serial stdio -sd sd.bin -S -s

7
bsp/qemu-vexpress-a9/rtconfig.h
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@ -53,6 +53,7 @@
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
@ -188,6 +189,9 @@
/* Modbus master and slave stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
@ -210,6 +214,9 @@
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */

290
bsp/raspi2/.config Normal file
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@ -0,0 +1,290 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Project Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
# CONFIG_RT_USING_MODULE is not set
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_A=y
CONFIG_ARCH_ARM_CORTEX_A7=y
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PIN is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
#
# sample package
#
# CONFIG_PKG_USING_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
CONFIG_BCM2836_SOC=y
CONFIG_RT_USING_UART1=y

26
bsp/raspi2/Kconfig Normal file
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@ -0,0 +1,26 @@
mainmenu "RT-Thread Project Configuration"
config $BSP_DIR
string
option env="BSP_ROOT"
default "."
config $RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config $PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config BCM2836_SOC
bool
select ARCH_ARM_CORTEX_A7
default y
source "driver/Kconfig"

106
bsp/raspi2/README.md Normal file
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@ -0,0 +1,106 @@
# Raspberry PI 2B板级支持包说明
## 1. 简介
树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派2采用4核Broadcom BCM2836 (ARMv7-A)芯片、双核VideoCore IV GPU和1GB内存。
这份RT-Thread BSP是针对 Raspberry Pi 2B 的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
![raspi2](figures/raspi2.png)
当前Raspberry Pi 2B对应的硬件特性：
| 硬件 | 描述 |
|------- | ------------------------------- |
| CPU | ARM Cortex-A7（4核心） |
| 主频 | 900M |
| Memory | 1GB (0x0000000 - 0x40000000) |
| | 其中0x3f000000 - 0x40000000为peripheral |
## 2. 编译说明
Windows环境下推荐使用[env工具][1]进行编译。
Linux下推荐使用gcc工具 [gcc-arm-none-eabi-4_8-2014q1_linux][2]，如果还没有编译工具，下载后，解开文件。
```
tar vxf gcc-arm-none-eabi-4_8-2014q1_linux.tar.bz2
```
Linux环境下需要修改编译器目录设置，修改`bsp/raspi2/rtconfig.py`中的
```
EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
```
为编译工具的实际所在目录，这里注意要加上后缀 `/bin`
进入到`rt-thread/bsp/raspi2`目录中，运行以下命令：
```
scons
```
来编译这个板级支持包。如果编译正确无误，会产生kernel.elf、kernel.img文件。
kernel.img即是要cp到raspberry SD卡中根目录的文件
## 3. 执行
### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
解开下载的镜像文件, linux下使用如下的命令
```
unzip 2018-06-27-raspbian-stretch-lite.zip
```
准备一张空SD卡，linux环境下，插入电脑并执行
```
sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
```
**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
最后把kernel7.img放入SD boot分区，覆盖原来的文件。
### 3.2 准备好串口线
目前版本是使用raspi2的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
![raspi2](figures/raspi_uart.png)
串口参数： 115200 8N1 ，硬件和软件流控为关。
按上面的方法做好SD卡后，插入树莓派2B，通电可以在串口上看到如下所示的输出信息：
```text
heap: 0x00020b20 - 0x00400000
\ | /
- RT - Thread Operating System
/ | \ 3.1.0 build Aug 23 2018
2006 - 2018 Copyright by rt-thread team
Hello RT-Thread!
msh >
```
## 4. 支持情况
| 驱动 | 支持情况 | 备注 |
| ------ | ---- | :------: |
| UART | 支持 | UART0|
## 5. 联系人信息
维护人：[bernard][5]
[1]: https://www.rt-thread.org/page/download.html
[2]: https://launchpad.net/gcc-arm-embedded/4.8/4.8-2014-q1-update/+download/gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2
[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
[4]: https://etcher.io
[5]: https://github.com/BernardXiong

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bsp/raspi2/SConscript Normal file
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@ -0,0 +1,14 @@
# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

27
bsp/raspi2/SConstruct Normal file
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import os
import sys
import rtconfig
from rtconfig import RTT_ROOT
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
# make a building
DoBuilding(TARGET, objs)

9
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* File : main.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <rtthread.h>
int main(int argc, char** argv)
{
rt_kprintf("Hello RT-Thread!\n");
return 0;
}

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/*
* File : mnt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
*/
#include <rtthread.h>
int mnt_init(void)
{
return 0;
}

9
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
CPPPATH = [cwd]
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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#ifndef __ARMV7_H__
#define __ARMV7_H__
/* the exception stack without VFP registers */
struct rt_hw_exp_stack
{
unsigned long r0;
unsigned long r1;
unsigned long r2;
unsigned long r3;
unsigned long r4;
unsigned long r5;
unsigned long r6;
unsigned long r7;
unsigned long r8;
unsigned long r9;
unsigned long r10;
unsigned long fp;
unsigned long ip;
unsigned long sp;
unsigned long lr;
unsigned long pc;
unsigned long cpsr;
};
struct rt_hw_stack
{
unsigned long cpsr;
unsigned long r0;
unsigned long r1;
unsigned long r2;
unsigned long r3;
unsigned long r4;
unsigned long r5;
unsigned long r6;
unsigned long r7;
unsigned long r8;
unsigned long r9;
unsigned long r10;
unsigned long fp;
unsigned long ip;
unsigned long lr;
unsigned long pc;
};
#define USERMODE 0x10
#define FIQMODE 0x11
#define IRQMODE 0x12
#define SVCMODE 0x13
#define MONITORMODE 0x16
#define ABORTMODE 0x17
#define HYPMODE 0x1b
#define UNDEFMODE 0x1b
#define MODEMASK 0x1f
#define NOINT 0xc0
#define T_Bit (1<<5)
#define F_Bit (1<<6)
#define I_Bit (1<<7)
#define A_Bit (1<<8)
#define E_Bit (1<<9)
#define J_Bit (1<<24)
#endif

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/*
* File : context.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2013, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
.section .text, "ax"
/*
* rt_base_t rt_hw_interrupt_disable();
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mrs r0, cpsr
cpsid i
bx lr
/*
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
msr cpsr_c, r0
bx lr
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* r0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
ldr sp, [r0] @ get new task stack pointer
ldmfd sp!, {r4} @ pop new task spsr
msr spsr_cxsf, r4
ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc
.section .bss.share.isr
_guest_switch_lvl:
.word 0
.globl vmm_virq_update
.section .text.isr, "ax"
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
* r0 --> from
* r1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
stmfd sp!, {r0-r12, lr} @ push lr & register file
mrs r4, cpsr
tst lr, #0x01
orrne r4, r4, #0x20 @ it's thumb code
stmfd sp!, {r4} @ push cpsr
str sp, [r0] @ store sp in preempted tasks TCB
ldr sp, [r1] @ get new task stack pointer
ldmfd sp!, {r4} @ pop new task cpsr to spsr
msr spsr_cxsf, r4
ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
ldr r2, =rt_thread_switch_interrupt_flag
ldr r3, [r2]
cmp r3, #1
beq _reswitch
ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1
str r0, [ip]
str r3, [r2]
_reswitch:
ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
str r1, [r2]
bx lr

12
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#ifndef __CP15_H__
#define __CP15_H__
unsigned long rt_cpu_get_smp_id(void);
void rt_cpu_mmu_disable(void);
void rt_cpu_mmu_enable(void);
void rt_cpu_tlb_set(volatile unsigned long*);
void rt_cpu_vector_set_base(unsigned int addr);
#endif

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/*
* File : cp15_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2013, RT-Thread Development Team
* http://www.rt-thread.org
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
.globl rt_cpu_get_smp_id
rt_cpu_get_smp_id:
mrc p15, #0, r0, c0, c0, #5
bx lr
.globl rt_cpu_vector_set_base
rt_cpu_vector_set_base:
mcr p15, #0, r0, c12, c0, #0
dsb
bx lr
.globl rt_hw_cpu_dcache_enable
rt_hw_cpu_dcache_enable:
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x00000004
mcr p15, #0, r0, c1, c0, #0
bx lr
.globl rt_hw_cpu_icache_enable
rt_hw_cpu_icache_enable:
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x00001000
mcr p15, #0, r0, c1, c0, #0
bx lr
_FLD_MAX_WAY:
.word 0x3ff
_FLD_MAX_IDX:
.word 0x7ff
.globl rt_cpu_dcache_clean_flush
rt_cpu_dcache_clean_flush:
push {r4-r11}
dmb
mrc p15, #1, r0, c0, c0, #1 @ read clid register
ands r3, r0, #0x7000000 @ get level of coherency
mov r3, r3, lsr #23
beq finished
mov r10, #0
loop1:
add r2, r10, r10, lsr #1
mov r1, r0, lsr r2
and r1, r1, #7
cmp r1, #2
blt skip
mcr p15, #2, r10, c0, c0, #0
isb
mrc p15, #1, r1, c0, c0, #0
and r2, r1, #7
add r2, r2, #4
ldr r4, _FLD_MAX_WAY
ands r4, r4, r1, lsr #3
clz r5, r4
ldr r7, _FLD_MAX_IDX
ands r7, r7, r1, lsr #13
loop2:
mov r9, r4
loop3:
orr r11, r10, r9, lsl r5
orr r11, r11, r7, lsl r2
mcr p15, #0, r11, c7, c14, #2
subs r9, r9, #1
bge loop3
subs r7, r7, #1
bge loop2
skip:
add r10, r10, #2
cmp r3, r10
bgt loop1
finished:
dsb
isb
pop {r4-r11}
bx lr
.globl rt_hw_cpu_dcache_disable
rt_hw_cpu_dcache_disable:
push {r4-r11, lr}
bl rt_cpu_dcache_clean_flush
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #0x00000004
mcr p15, #0, r0, c1, c0, #0
pop {r4-r11, lr}
bx lr
.globl rt_hw_cpu_icache_disable
rt_hw_cpu_icache_disable:
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #0x00001000
mcr p15, #0, r0, c1, c0, #0
bx lr
.globl rt_cpu_mmu_disable
rt_cpu_mmu_disable:
mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb
mrc p15, #0, r0, c1, c0, #0
bic r0, r0, #1
mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit
dsb
bx lr
.globl rt_cpu_mmu_enable
rt_cpu_mmu_enable:
mrc p15, #0, r0, c1, c0, #0
orr r0, r0, #0x001
mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit
dsb
bx lr
.globl rt_cpu_tlb_set
rt_cpu_tlb_set:
mcr p15, #0, r0, c2, c0, #0
dmb
bx lr

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/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
/**
* @addtogroup AM33xx
*/
/*@{*/
/** shutdown CPU */
void rt_hw_cpu_shutdown()
{
rt_uint32_t level;
rt_kprintf("shutdown...\n");
level = rt_hw_interrupt_disable();
while (level)
{
RT_ASSERT(0);
}
}
/*@}*/

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/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2013-2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2018/5/3 Bernard first version
*/
#include <rthw.h>
#include <rtthread.h>
#include "cp15.h"
#include <board.h>
#define MAX_HANDLERS 64
extern volatile rt_uint8_t rt_interrupt_nest;
/* exception and interrupt handler table */
struct rt_irq_desc isr_table[MAX_HANDLERS];
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
extern int system_vectors;
static void default_isr_handler(int vector, void *param)
{
rt_kprintf("unhandled irq: %d\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
uint32_t index;
/* mask all of interrupts */
IRQ_DISABLE_BASIC = 0x000000ff;
IRQ_DISABLE1 = 0xffffffff;
IRQ_DISABLE2 = 0xffffffff;
for (index = 0; index < MAX_HANDLERS; index ++)
{
isr_table[index].handler = default_isr_handler;
isr_table[index].param = NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
isr_table[index].counter = 0;
#endif
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
if (vector < 8)
{
IRQ_DISABLE_BASIC = (1 << vector);
}
else if (vector < 32)
{
IRQ_DISABLE1 = (1 << vector);
}
else
{
vector = vector % 32;
IRQ_DISABLE2 = (1 << vector);
}
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
if (vector < 8)
{
IRQ_ENABLE_BASIC = (1 << vector);
}
else if (vector < 32)
{
IRQ_ENABLE1 = (1 << vector);
}
else
{
vector = vector % 32;
IRQ_ENABLE2 = (1 << vector);
}
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < MAX_HANDLERS)
{
old_handler = isr_table[vector].handler;
if (handler != RT_NULL)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
isr_table[vector].handler = handler;
isr_table[vector].param = param;
}
}
return old_handler;
}

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/*
* File : mmu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2012-01-10 bernard porting to AM1808
*/
#include <rtthread.h>
#include <rthw.h>
#include <board.h>
#include "cp15.h"
#define DESC_SEC (0x2)
#define CB (3<<2) //cache_on, write_back
#define CNB (2<<2) //cache_on, write_through
#define NCB (1<<2) //cache_off,WR_BUF on
#define NCNB (0<<2) //cache_off,WR_BUF off
#define AP_RW (3<<10) //supervisor=RW, user=RW
#define AP_RO (2<<10) //supervisor=RW, user=RO
#define XN (1<<4) // eXecute Never
#define DOMAIN_FAULT (0x0)
#define DOMAIN_CHK (0x1)
#define DOMAIN_NOTCHK (0x3)
#define DOMAIN0 (0x0<<5)
#define DOMAIN1 (0x1<<5)
#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
/* Read/Write, cache, write back */
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
/* Read/Write, cache, write through */
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
/* Read/Write without cache and write buffer */
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
/* Read/Write without cache and write buffer, no execute */
#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
/* Read/Write without cache and write buffer */
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
/* dump 2nd level page table */
void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
{
int i;
int fcnt = 0;
for (i = 0; i < 256; i++)
{
rt_uint32_t pte2 = ptb[i];
if ((pte2 & 0x3) == 0)
{
if (fcnt == 0)
rt_kprintf(" ");
rt_kprintf("%04x: ", i);
fcnt++;
if (fcnt == 16)
{
rt_kprintf("fault\n");
fcnt = 0;
}
continue;
}
if (fcnt != 0)
{
rt_kprintf("fault\n");
fcnt = 0;
}
rt_kprintf(" %04x: %x: ", i, pte2);
if ((pte2 & 0x3) == 0x1)
{
rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
((pte2 >> 7) | (pte2 >> 4))& 0xf,
(pte2 >> 15) & 0x1,
((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
}
else
{
rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
}
}
}
void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
{
int i;
int fcnt = 0;
rt_kprintf("page table@%p\n", ptb);
for (i = 0; i < 1024*4; i++)
{
rt_uint32_t pte1 = ptb[i];
if ((pte1 & 0x3) == 0)
{
rt_kprintf("%03x: ", i);
fcnt++;
if (fcnt == 16)
{
rt_kprintf("fault\n");
fcnt = 0;
}
continue;
}
if (fcnt != 0)
{
rt_kprintf("fault\n");
fcnt = 0;
}
rt_kprintf("%03x: %08x: ", i, pte1);
if ((pte1 & 0x3) == 0x3)
{
rt_kprintf("LPAE\n");
}
else if ((pte1 & 0x3) == 0x1)
{
rt_kprintf("pte,ns:%d,domain:%d\n",
(pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
/*
*rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
* - 0x80000000 + 0xC0000000));
*/
}
else if (pte1 & (1 << 18))
{
rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
(pte1 >> 19) & 0x1,
((pte1 >> 13) | (pte1 >> 10))& 0xf,
(pte1 >> 4) & 0x1,
((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
}
else
{
rt_kprintf("section,ns:%d,ap:%x,"
"xn:%d,texcb:%02x,domain:%d\n",
(pte1 >> 19) & 0x1,
((pte1 >> 13) | (pte1 >> 10))& 0xf,
(pte1 >> 4) & 0x1,
(((pte1 & (0x7 << 12)) >> 10) |
((pte1 & 0x0c) >> 2)) & 0x1f,
(pte1 >> 5) & 0xf);
}
}
}
/* level1 page table, each entry for 1MB memory. */
volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
rt_uint32_t vaddrEnd,
rt_uint32_t paddrStart,
rt_uint32_t attr)
{
volatile rt_uint32_t *pTT;
volatile int i, nSec;
pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
for(i = 0; i <= nSec; i++)
{
*pTT = attr | (((paddrStart >> 20) + i) << 20);
pTT++;
}
}
unsigned long rt_hw_set_domain_register(unsigned long domain_val)
{
unsigned long old_domain;
asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
return old_domain;
}
void rt_hw_mmu_init(void)
{
rt_hw_cpu_dcache_disable();
rt_hw_cpu_icache_disable();
rt_cpu_mmu_disable();
/* set page table */
/* 4G 1:1 memory */
rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
/* IO memory region */
rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
/*rt_hw_cpu_dump_page_table(MMUTable);*/
rt_hw_set_domain_register(0x55555555);
rt_cpu_tlb_set(MMUTable);
rt_cpu_mmu_enable();
rt_hw_cpu_icache_enable();
rt_hw_cpu_dcache_enable();
}

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/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-09-23 Bernard the first version
* 2011-10-05 Bernard add thumb mode
*/
#include <rtthread.h>
#include <board.h>
#include <armv7.h>
/**
* @addtogroup AM33xx
*/
/*@{*/
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
stack_addr += sizeof(rt_uint32_t);
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint32_t *)stack_addr;
*(--stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* lr */
*(--stk) = 0xdeadbeef; /* r12 */
*(--stk) = 0xdeadbeef; /* r11 */
*(--stk) = 0xdeadbeef; /* r10 */
*(--stk) = 0xdeadbeef; /* r9 */
*(--stk) = 0xdeadbeef; /* r8 */
*(--stk) = 0xdeadbeef; /* r7 */
*(--stk) = 0xdeadbeef; /* r6 */
*(--stk) = 0xdeadbeef; /* r5 */
*(--stk) = 0xdeadbeef; /* r4 */
*(--stk) = 0xdeadbeef; /* r3 */
*(--stk) = 0xdeadbeef; /* r2 */
*(--stk) = 0xdeadbeef; /* r1 */
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
/* cpsr */
if ((rt_uint32_t)tentry & 0x01)
*(--stk) = SVCMODE | 0x20; /* thumb mode */
else
*(--stk) = SVCMODE; /* arm mode */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

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/*
* File : start_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2013-2014, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
.equ Mode_USR, 0x10
.equ Mode_FIQ, 0x11
.equ Mode_IRQ, 0x12
.equ Mode_SVC, 0x13
.equ Mode_ABT, 0x17
.equ Mode_UND, 0x1B
.equ Mode_SYS, 0x1F
.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
.equ UND_Stack_Size, 0x00000000
.equ SVC_Stack_Size, 0x00000100
.equ ABT_Stack_Size, 0x00000000
.equ RT_FIQ_STACK_PGSZ, 0x00000000
.equ RT_IRQ_STACK_PGSZ, 0x00000100
.equ USR_Stack_Size, 0x00000100
#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
.section .data.share.isr
/* stack */
.globl stack_start
.globl stack_top
stack_start:
.rept ISR_Stack_Size
.byte 0
.endr
stack_top:
.text
/* reset entry */
.globl _reset
_reset:
/* Disable IRQ & FIQ */
cpsid if
/* Check for HYP mode */
mrs r0, cpsr_all
and r0, r0, #0x1F
mov r8, #0x1A
cmp r0, r8
beq overHyped
b continue
overHyped: /* Get out of HYP mode */
ldr r1, =continue
msr ELR_hyp, r1
mrs r1, cpsr_all
and r1, r1, #0x1f ;@ CPSR_MODE_MASK
orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR
msr SPSR_hyp, r1
eret
continue:
/* disable smp */
bl arm_smp_disable
/* disable mmu */
bl rt_cpu_mmu_disable
/* set the cpu to SVC32 mode and disable interrupt */
mrs r0, cpsr
bic r0, r0, #0x1f
orr r0, r0, #0x13
msr cpsr_c, r0
/* setup stack */
bl stack_setup
/* clear .bss */
mov r0,#0 /* get a zero */
ldr r1,=__bss_start /* bss start */
ldr r2,=__bss_end /* bss end */
bss_loop:
cmp r1,r2 /* check if data to clear */
strlo r0,[r1],#4 /* clear 4 bytes */
blo bss_loop /* loop until done */
/* start RT-Thread Kernel */
ldr pc, _rtthread_startup
_rtthread_startup:
.word rtthread_startup
stack_setup:
ldr r0, =stack_top
@ Set the startup stack for svc
mov sp, r0
sub r0, r0, #SVC_Stack_Size
@ Enter Undefined Instruction Mode and set its Stack Pointer
msr cpsr_c, #Mode_UND|I_Bit|F_Bit
mov sp, r0
sub r0, r0, #UND_Stack_Size
@ Enter Abort Mode and set its Stack Pointer
msr cpsr_c, #Mode_ABT|I_Bit|F_Bit
mov sp, r0
sub r0, r0, #ABT_Stack_Size
@ Enter FIQ Mode and set its Stack Pointer
msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit
mov sp, r0
sub r0, r0, #RT_FIQ_STACK_PGSZ
@ Enter IRQ Mode and set its Stack Pointer
msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit
mov sp, r0
sub r0, r0, #RT_IRQ_STACK_PGSZ
/* come back to SVC mode */
msr cpsr_c, #Mode_SVC|I_Bit|F_Bit
bx lr
.text
;@ void arm_smp_enable(void);
.globl arm_smp_enable
arm_smp_enable:
mrc p15, 0, r0, c1, c0, 1 ;@ set SMP bit in ACTLR
orr r0, r0, #0x40
mcr p15, 0, r0, c1, c0, 1
bx lr
.text
;@ void arm_smp_disable(void);
.globl arm_smp_disable
arm_smp_disable:
mrc p15, 0, r0, c1, c0, 1 ;@ clear SMP bit in ACTLR
bic r0, r0, #0x40
mcr p15, 0, r0, c1, c0, 1
bx lr
/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */
.section .text.isr, "ax"
.align 5
.globl vector_fiq
vector_fiq:
stmfd sp!,{r0-r7,lr}
bl rt_hw_trap_fiq
ldmfd sp!,{r0-r7,lr}
subs pc, lr, #4
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_current_thread
.globl vmm_thread
.globl vmm_virq_check
.align 5
.globl vector_irq
vector_irq:
stmfd sp!, {r0-r12,lr}
bl rt_interrupt_enter
bl rt_hw_trap_irq
bl rt_interrupt_leave
@ if rt_thread_switch_interrupt_flag set, jump to
@ rt_hw_context_switch_interrupt_do and don't return
ldr r0, =rt_thread_switch_interrupt_flag
ldr r1, [r0]
cmp r1, #1
beq rt_hw_context_switch_interrupt_do
ldmfd sp!, {r0-r12,lr}
subs pc, lr, #4
rt_hw_context_switch_interrupt_do:
mov r1, #0 @ clear flag
str r1, [r0]
mov r1, sp @ r1 point to {r0-r3} in stack
add sp, sp, #4*4
ldmfd sp!, {r4-r12,lr}@ reload saved registers
mrs r0, spsr @ get cpsr of interrupt thread
sub r2, lr, #4 @ save old task's pc to r2
@ Switch to SVC mode with no interrupt. If the usr mode guest is
@ interrupted, this will just switch to the stack of kernel space.
@ save the registers in kernel space won't trigger data abort.
msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
stmfd sp!, {r2} @ push old task's pc
stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4
ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread
stmfd sp!, {r1-r4} @ push old task's r0-r3
stmfd sp!, {r0} @ push old task's cpsr
ldr r4, =rt_interrupt_from_thread
ldr r5, [r4]
str sp, [r5] @ store sp in preempted tasks's TCB
ldr r6, =rt_interrupt_to_thread
ldr r6, [r6]
ldr sp, [r6] @ get new task's stack pointer
ldmfd sp!, {r4} @ pop new task's cpsr to spsr
msr spsr_cxsf, r4
ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
.macro push_svc_reg
sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */
stmia sp, {r0 - r12} @/* Calling r0-r12 */
mov r0, sp
mrs r6, spsr @/* Save CPSR */
str lr, [r0, #15*4] @/* Push PC */
str r6, [r0, #16*4] @/* Push CPSR */
cps #Mode_SVC
str sp, [r0, #13*4] @/* Save calling SP */
str lr, [r0, #14*4] @/* Save calling PC */
.endm
.align 5
.globl vector_swi
vector_swi:
push_svc_reg
bl rt_hw_trap_swi
b .
.align 5
.globl vector_undef
vector_undef:
push_svc_reg
bl rt_hw_trap_undef
b .
.align 5
.globl vector_pabt
vector_pabt:
push_svc_reg
bl rt_hw_trap_pabt
b .
.align 5
.globl vector_dabt
vector_dabt:
push_svc_reg
bl rt_hw_trap_dabt
b .
.align 5
.globl vector_resv
vector_resv:
push_svc_reg
bl rt_hw_trap_resv
b .

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/*
* File : trap.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2013, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2013-07-20 Bernard first version
*/
#include <rthw.h>
#include <board.h>
#include <rtthread.h>
#include "armv7.h"
extern struct rt_thread *rt_current_thread;
#ifdef RT_USING_FINSH
extern long list_thread(void);
#endif
/**
* this function will show registers of CPU
*
* @param regs the registers point
*/
void rt_hw_show_register(struct rt_hw_exp_stack *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
}
/**
* When comes across an instruction which it cannot handle,
* it takes the undefined instruction trap.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
{
rt_kprintf("undefined instruction:\n");
rt_hw_show_register(regs);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
/**
* The software interrupt instruction (SWI) is used for entering
* Supervisor mode, usually to request a particular supervisor
* function.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
{
rt_kprintf("software interrupt:\n");
rt_hw_show_register(regs);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
/**
* An abort indicates that the current memory access cannot be completed,
* which occurs during an instruction prefetch.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
{
rt_kprintf("prefetch abort:\n");
rt_hw_show_register(regs);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
/**
* An abort indicates that the current memory access cannot be completed,
* which occurs during a data access.
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
{
rt_kprintf("data abort:");
rt_hw_show_register(regs);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
/**
* Normally, system will never reach here
*
* @param regs system registers
*
* @note never invoke this function in application
*/
void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
{
rt_kprintf("reserved trap:\n");
rt_hw_show_register(regs);
#ifdef RT_USING_FINSH
list_thread();
#endif
rt_hw_cpu_shutdown();
}
void rt_hw_trap_irq(void)
{
void *param;
rt_isr_handler_t isr_func;
extern struct rt_irq_desc isr_table[];
uint32_t value = 0;
// rt_kprintf("pend basic: 0x%08x\n", IRQ_PEND_BASIC);
// rt_kprintf(" pend1: 0x%08x\n", IRQ_PEND1);
// rt_kprintf(" pend2: 0x%08x\n", IRQ_PEND2);
value = IRQ_PEND_BASIC & 0x3ff;
if (value)
{
uint32_t irq;
if (value & (1 << 8))
{
value = IRQ_PEND1;
irq = __rt_ffs(value) - 1;
}
else if (value & (1 << 9))
{
value = IRQ_PEND2;
irq = __rt_ffs(value) + 31;
}
else
{
value &= 0x0f;
irq = __rt_ffs(value) - 1;
}
/* get interrupt service routine */
isr_func = isr_table[irq].handler;
#ifdef RT_USING_INTERRUPT_INFO
isr_table[irq].counter++;
#endif
if (isr_func)
{
/* Interrupt for myself. */
param = isr_table[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
}
}
}
void rt_hw_trap_fiq(void)
{
/* TODO */
}

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/*
* File : vector_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2013, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
.section .vectors, "ax"
.code 32
.globl system_vectors
system_vectors:
ldr pc, _vector_reset
ldr pc, _vector_undef
ldr pc, _vector_swi
ldr pc, _vector_pabt
ldr pc, _vector_dabt
ldr pc, _vector_resv
ldr pc, _vector_irq
ldr pc, _vector_fiq
.globl _reset
.globl vector_undef
.globl vector_swi
.globl vector_pabt
.globl vector_dabt
.globl vector_resv
.globl vector_irq
.globl vector_fiq
_vector_reset:
.word _reset
_vector_undef:
.word vector_undef
_vector_swi:
.word vector_swi
_vector_pabt:
.word vector_pabt
_vector_dabt:
.word vector_dabt
_vector_resv:
.word vector_resv
_vector_irq:
.word vector_irq
_vector_fiq:
.word vector_fiq
.balignl 16,0xdeadbeef

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config RT_USING_UART1
bool "Enable UART1"
default y

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# RT-Thread building script for component
from building import *
cwd = GetCurrentDir()
src = Split('''
board.c
drv_uart.c
''')
CPPPATH = [cwd]
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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#ifndef BCM283X_H__
#define BCM283X_H__
#include <rthw.h>
#define PER_BASE (0x3F000000)
#define PER_BASE_40000000 (0x40000000)
/*
* GPIO
*/
#define GPIO_BASE (PER_BASE + 0x200000)
#define GPIO_GPFSEL0 HWREG32(GPIO_BASE + 0x00) /* GPIO Function Select 0 32bit R/W */
#define GPIO_GPFSEL1 HWREG32(GPIO_BASE + 0x04) /* GPIO Function Select 1 32bit R/W */
#define GPIO_GPFSEL2 HWREG32(GPIO_BASE + 0x08) /* GPIO Function Select 2 32bit R/W */
#define GPIO_GPFSEL4 HWREG32(GPIO_BASE + 0x10) /* GPIO Function Select 4 32bit R/W */
#define GPIO_GPSET0 HWREG32(GPIO_BASE + 0x1C)
#define GPIO_GPCLR0 HWREG32(GPIO_BASE + 0x28)
#define GPIO_GPPUD HWREG32(GPIO_BASE + 0x94) /* GPIO Pin Pull-up/down Enable */
#define GPIO_GPPUDCLK0 HWREG32(GPIO_BASE + 0x98) /* GPIO Pin Pull-up/down Enable Clock 0 */
#define GPIO_GPPUDCLK1 HWREG32(GPIO_BASE + 0x9C) /* GPIO Pin Pull-up/down Enable Clock 1 */
/*
* Interrupt Controler
*/
#define IRQ_BASE (PER_BASE + 0xB200)
#define IRQ_PEND_BASIC HWREG32(IRQ_BASE + 0x00)
#define IRQ_PEND1 HWREG32(IRQ_BASE + 0x04)
#define IRQ_PEND2 HWREG32(IRQ_BASE + 0x08)
#define IRQ_FIQ_CONTROL HWREG32(IRQ_BASE + 0x0C)
#define IRQ_ENABLE1 HWREG32(IRQ_BASE + 0x10)
#define IRQ_ENABLE2 HWREG32(IRQ_BASE + 0x14)
#define IRQ_ENABLE_BASIC HWREG32(IRQ_BASE + 0x18)
#define IRQ_DISABLE1 HWREG32(IRQ_BASE + 0x1C)
#define IRQ_DISABLE2 HWREG32(IRQ_BASE + 0x20)
#define IRQ_DISABLE_BASIC HWREG32(IRQ_BASE + 0x24)
/*
* System Timer
*/
#define STIMER_BASE (PER_BASE + 0x3000)
#define STIMER_CS HWREG32(STIMER_BASE + 0x00)
#define STIMER_CLO HWREG32(STIMER_BASE + 0x04)
#define STIMER_CHI HWREG32(STIMER_BASE + 0x08)
#define STIMER_C0 HWREG32(STIMER_BASE + 0x0C)
#define STIMER_C1 HWREG32(STIMER_BASE + 0x10)
#define STIMER_C2 HWREG32(STIMER_BASE + 0x14)
#define STIMER_C3 HWREG32(STIMER_BASE + 0x18)
/*
* ARM Timer
*/
#define ARM_TIMER_BASE (PER_BASE + 0xB000)
#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400)
#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404)
#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408)
#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C)
#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410)
#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414)
#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418)
#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C)
#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420)
/*
* Core Timer
*/
#define CTIMER_CTL HWREG32(PER_BASE_40000000 + 0x00) /* Control register */
#define CTIMER_PRE HWREG32(PER_BASE_40000000 + 0x08) /* Core timer prescaler */
#define CTIMER_LS32B HWREG32(PER_BASE_40000000 + 0x1C) /* Core timer access LS 32 bits */
#define CTIMER_MS32B HWREG32(PER_BASE_40000000 + 0x20) /* Core timer access MS 32 bits */
/*
* ARM Core Timer
*/
#define C0TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x40) /* Core0 timers Interrupt control */
#define C1TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x44) /* Core1 timers Interrupt control */
#define C2TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x48) /* Core2 timers Interrupt control */
#define C3TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x4C) /* Core3 timers Interrupt control */
/*
* ARM Core Mailbox interrupt
*/
#define C0MB_INTCTL HWREG32(PER_BASE_40000000 + 0x50) /* Core0 Mailboxes Interrupt control */
#define C1MB_INTCTL HWREG32(PER_BASE_40000000 + 0x54) /* Core1 Mailboxes Interrupt control */
#define C2MB_INTCTL HWREG32(PER_BASE_40000000 + 0x58) /* Core2 Mailboxes Interrupt control */
#define C3MB_INTCTL HWREG32(PER_BASE_40000000 + 0x5C) /* Core3 Mailboxes Interrupt control */
/*
* ARM Core IRQ/FIQ status
*/
#define C0_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x60) /* Core0 IRQ Source */
#define C1_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x64) /* Core1 IRQ Source */
#define C2_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x68) /* Core2 IRQ Source */
#define C3_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x6C) /* Core3 IRQ Source */
#define C0_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x70) /* Core0 FIQ Source */
#define C1_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x74) /* Core1 FIQ Source */
#define C2_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x78) /* Core2 FIQ Source */
#define C3_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x7C) /* Core3 FIQ Source */
#define IRQ_ARM_TIMER 0
#define IRQ_ARM_MAILBOX 1
#define IRQ_ARM_DB0 2
#define IRQ_ARM_DB1 3
#define IRQ_ARM_GPU0_HALT 4
#define IRQ_ARM_GPU1_HALT 5
#define IRQ_ARM_ILLEGAL_ACC1 6
#define IRQ_ARM_ILLEGAL_ACC0 7
#define IRQ_AUX 29
#define IRQ_IIC_SPI_SLV 43
#define IRQ_PWA0 45
#define IRQ_PWA1 46
#define IRQ_SMI 48
#define IRQ_GPIO0 49
#define IRQ_GPIO1 50
#define IRQ_GPIO2 51
#define IRQ_GPIO3 52
#define IRQ_IIC 53
#define IRQ_SPI 54
#define IRQ_PCM 55
#define IRQ_UART 57
#endif

90
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/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "drv_uart.h"
void rt_hw_timer_isr(int vector, void *parameter)
{
ARM_TIMER_IRQCLR = 0;
rt_tick_increase();
}
int rt_hw_timer_init(void)
{
/* timer_clock = apb_clock/(pre_divider + 1) */
ARM_TIMER_PREDIV = (250 - 1);
ARM_TIMER_RELOAD = 0;
ARM_TIMER_LOAD = 0;
ARM_TIMER_IRQCLR = 0;
ARM_TIMER_CTRL = 0;
ARM_TIMER_RELOAD = 10000;
ARM_TIMER_LOAD = 10000;
/* 23-bit counter, enable interrupt, enable timer */
ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
rt_hw_interrupt_umask(IRQ_ARM_TIMER);
return 0;
}
void vector_copy(void)
{
rt_memcpy((void*)0x0, (void*)0x8000, 64);
}
void rt_hw_board_init(void)
{
/* initialize hardware interrupt */
rt_hw_interrupt_init();
vector_copy();
/* initialize uart */
rt_hw_uart_init();
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif /* RT_USING_CONSOLE */
#ifdef RT_USING_HEAP
/* initialize memory system */
rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
#endif
/* initialize timer for os tick */
// rt_hw_timer_init();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

42
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/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef BOARD_H__
#define BOARD_H__
#include <stdint.h>
#include <rthw.h>
#include <bcm283x.h>
extern unsigned char __bss_start;
extern unsigned char __bss_end;
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
#define RT_HW_HEAP_END (void*)(0x0 + 4 * 1024 * 1024)
void rt_hw_board_init(void);
#endif

199
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/*
* File : drv_uart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2018/5/5 Bernard The first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_uart.h"
#include <rtdevice.h>
#define AUX_BASE (0x3F000000 + 0x215000)
struct hw_uart_device
{
rt_uint32_t hw_base;
rt_uint32_t irqno;
};
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
if (uart->hw_base == AUX_BASE)
{
uint32_t value;
/* GPIO function set */
value = GPIO_GPFSEL1;
value &= ~(7<<12); /* GPIO14 */
value |= 2<<12 ; /* ALT5 */
value &= ~(7<<15); /* GPIO15 */
value |= 2<<15 ; /* ALT5 */
GPIO_GPFSEL1 = value;
/* PullUD disable */
GPIO_GPPUD = 0;
GPIO_GPPUDCLK0 = (1 << 14) | (1 << 15);
GPIO_GPPUDCLK0 = 0;
AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */
AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */
AUX_MU_CNTL_REG(uart->hw_base) = 0; /* Disable Transmitter and Receiver */
AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */
AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */
AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */
AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */
}
return RT_EOK;
}
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
AUX_MU_IER_REG(uart->hw_base) = 0x0;
rt_hw_interrupt_mask(uart->irqno);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
AUX_MU_IER_REG(uart->hw_base) = 0x1;
rt_hw_interrupt_umask(uart->irqno);
break;
}
return RT_EOK;
}
static int uart_putc(struct rt_serial_device *serial, char c)
{
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
AUX_MU_IO_REG(uart->hw_base) = c;
return 1;
}
static int uart_getc(struct rt_serial_device *serial)
{
int ch = -1;
struct hw_uart_device *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct hw_uart_device *)serial->parent.user_data;
if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
{
ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
}
return ch;
}
static const struct rt_uart_ops _uart_ops =
{
uart_configure,
uart_control,
uart_putc,
uart_getc,
};
static void rt_hw_uart_isr(int irqno, void *param)
{
struct rt_serial_device *serial = (struct rt_serial_device*)param;
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
#ifdef RT_USING_UART0
/* UART device driver structure */
static struct hw_uart_device _uart0_device =
{
RPI_UART0_BASE,
IRQ_PBA8_UART0,
};
static struct rt_serial_device _serial0;
#endif
#ifdef RT_USING_UART1
/* UART1 device driver structure */
static struct hw_uart_device _uart1_device =
{
AUX_BASE,
IRQ_AUX,
};
static struct rt_serial_device _serial1;
#endif
int rt_hw_uart_init(void)
{
struct hw_uart_device *uart;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef RT_USING_UART0
uart = &_uart0_device;
_serial0.ops = &_uart_ops;
_serial0.config = config;
/* register UART1 device */
rt_hw_serial_register(&_serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
#endif
#ifdef RT_USING_UART1
uart = &_uart1_device;
_serial1.ops = &_uart_ops;
_serial1.config = config;
/* register UART1 device */
rt_hw_serial_register(&_serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
/* enable Rx and Tx of UART */
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1");
#endif
return 0;
}

56
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/*
* File : drv_uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-5-30 Bernard the first version
*/
#ifndef DRV_UART_H__
#define DRV_UART_H__
/*
* Auxiliary
*/
#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */
#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */
#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */
#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */
#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */
#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */
#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */
#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */
#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */
#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */
#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */
#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */
#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */
#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */
#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */
#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */
#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */
#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */
#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */
#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */
int rt_hw_uart_init(void);
#endif /* DRV_UART_H__ */

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149
bsp/raspi2/link.lds Normal file
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/*
* File : link.lds
* COPYRIGHT (C) 2017, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* 2017-5-30 bernard first version
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SECTIONS
{
. = 0x00008000;
. = ALIGN(4);
.text :
{
*(.vectors)
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
}
.eh_frame_hdr :
{
*(.eh_frame_hdr)
*(.eh_frame_entry)
}
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.data1)
*(.data1.*)
. = ALIGN(8);
_gp = ABSOLUTE(.); /* Base of small data */
*(.sdata)
*(.sdata.*)
}
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(4);
.bss :
{
PROVIDE(__bss_start = .);
*(.bss)
*(.bss.*)
*(.dynbss)
*(COMMON)
PROVIDE(__bss_end = .);
}
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

257
bsp/raspi2/rtconfig.h Normal file
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#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Project Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
/* RT_THREAD_PRIORITY_8 is not set */
#define RT_THREAD_PRIORITY_32
/* RT_THREAD_PRIORITY_256 is not set */
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 100
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_IDEL_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
/* RT_USING_TIMER_SOFT is not set */
#define RT_DEBUG
/* RT_DEBUG_INIT_CONFIG is not set */
/* RT_DEBUG_THREAD_CONFIG is not set */
/* RT_DEBUG_SCHEDULER_CONFIG is not set */
/* RT_DEBUG_IPC_CONFIG is not set */
/* RT_DEBUG_TIMER_CONFIG is not set */
/* RT_DEBUG_IRQ_CONFIG is not set */
/* RT_DEBUG_MEM_CONFIG is not set */
/* RT_DEBUG_SLAB_CONFIG is not set */
/* RT_DEBUG_MEMHEAP_CONFIG is not set */
/* RT_DEBUG_MODULE_CONFIG is not set */
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
/* RT_USING_SIGNALS is not set */
/* Memory Management */
#define RT_USING_MEMPOOL
/* RT_USING_MEMHEAP is not set */
/* RT_USING_NOHEAP is not set */
#define RT_USING_SMALL_MEM
/* RT_USING_SLAB is not set */
/* RT_USING_MEMTRACE is not set */
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
/* RT_USING_DEVICE_OPS is not set */
/* RT_USING_INTERRUPT_INFO is not set */
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
/* RT_USING_MODULE is not set */
#define ARCH_ARM
#define ARCH_ARM_CORTEX_A
#define ARCH_ARM_CORTEX_A7
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
/* C++ features */
/* RT_USING_CPLUSPLUS is not set */
/* Command shell */
#define RT_USING_FINSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
/* FINSH_ECHO_DISABLE_DEFAULT is not set */
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
/* FINSH_USING_AUTH is not set */
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_USING_MSH_ONLY
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* RT_USING_DFS is not set */
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
/* RT_USING_CAN is not set */
/* RT_USING_HWTIMER is not set */
/* RT_USING_CPUTIME is not set */
/* RT_USING_I2C is not set */
/* RT_USING_PIN is not set */
/* RT_USING_PWM is not set */
/* RT_USING_MTD_NOR is not set */
/* RT_USING_MTD_NAND is not set */
/* RT_USING_RTC is not set */
/* RT_USING_SDIO is not set */
/* RT_USING_SPI is not set */
/* RT_USING_WDT is not set */
/* RT_USING_WIFI is not set */
/* RT_USING_AUDIO is not set */
/* Using USB */
/* RT_USING_USB_HOST is not set */
/* RT_USING_USB_DEVICE is not set */
/* POSIX layer and C standard library */
/* RT_USING_LIBC is not set */
/* RT_USING_PTHREADS is not set */
/* Network */
/* Socket abstraction layer */
/* RT_USING_SAL is not set */
/* light weight TCP/IP stack */
/* RT_USING_LWIP is not set */
/* Modbus master and slave stack */
/* RT_USING_MODBUS is not set */
/* AT commands */
/* RT_USING_AT is not set */
/* VBUS(Virtual Software BUS) */
/* RT_USING_VBUS is not set */
/* Utilities */
/* RT_USING_LOGTRACE is not set */
/* RT_USING_RYM is not set */
/* RT-Thread online packages */
/* IoT - internet of things */
/* PKG_USING_PAHOMQTT is not set */
/* PKG_USING_WEBCLIENT is not set */
/* PKG_USING_MONGOOSE is not set */
/* PKG_USING_WEBTERMINAL is not set */
/* PKG_USING_CJSON is not set */
/* PKG_USING_JSMN is not set */
/* PKG_USING_LJSON is not set */
/* PKG_USING_EZXML is not set */
/* PKG_USING_NANOPB is not set */
/* Wi-Fi */
/* Marvell WiFi */
/* PKG_USING_WLANMARVELL is not set */
/* Wiced WiFi */
/* PKG_USING_WLAN_WICED is not set */
/* PKG_USING_COAP is not set */
/* PKG_USING_NOPOLL is not set */
/* PKG_USING_NETUTILS is not set */
/* PKG_USING_AT_DEVICE is not set */
/* IoT Cloud */
/* PKG_USING_ONENET is not set */
/* PKG_USING_GAGENT_CLOUD is not set */
/* PKG_USING_ALI_IOTKIT is not set */
/* PKG_USING_AZURE is not set */
/* security packages */
/* PKG_USING_MBEDTLS is not set */
/* PKG_USING_libsodium is not set */
/* PKG_USING_TINYCRYPT is not set */
/* language packages */
/* PKG_USING_LUA is not set */
/* PKG_USING_JERRYSCRIPT is not set */
/* PKG_USING_MICROPYTHON is not set */
/* multimedia packages */
/* PKG_USING_OPENMV is not set */
/* PKG_USING_MUPDF is not set */
/* tools packages */
/* PKG_USING_CMBACKTRACE is not set */
/* PKG_USING_EASYFLASH is not set */
/* PKG_USING_EASYLOGGER is not set */
/* PKG_USING_SYSTEMVIEW is not set */
/* system packages */
/* PKG_USING_GUIENGINE is not set */
/* PKG_USING_PERSIMMON is not set */
/* PKG_USING_CAIRO is not set */
/* PKG_USING_PIXMAN is not set */
/* PKG_USING_LWEXT4 is not set */
/* PKG_USING_PARTITION is not set */
/* PKG_USING_FAL is not set */
/* PKG_USING_SQLITE is not set */
/* PKG_USING_RTI is not set */
/* PKG_USING_LITTLEVGL2RTT is not set */
/* peripheral libraries and drivers */
/* PKG_USING_STM32F4_HAL is not set */
/* PKG_USING_STM32F4_DRIVERS is not set */
/* PKG_USING_REALTEK_AMEBA is not set */
/* PKG_USING_SHT2X is not set */
/* PKG_USING_AHT10 is not set */
/* miscellaneous packages */
/* PKG_USING_LIBCSV is not set */
/* PKG_USING_OPTPARSE is not set */
/* PKG_USING_FASTLZ is not set */
/* PKG_USING_MINILZO is not set */
/* PKG_USING_QUICKLZ is not set */
/* PKG_USING_MULTIBUTTON is not set */
/* PKG_USING_CANFESTIVAL is not set */
/* PKG_USING_ZLIB is not set */
/* PKG_USING_DSTR is not set */
/* sample package */
/* PKG_USING_SAMPLES is not set */
/* example package: hello */
/* PKG_USING_HELLO is not set */
#define BCM2836_SOC
#define RT_USING_UART1
#endif

53
bsp/raspi2/rtconfig.py Normal file
View File

@ -0,0 +1,53 @@
import os
# toolchains options
ARCH ='arm'
CPU ='cortex-a7'
CROSS_TOOL ='gcc'
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = r'../..'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
PLATFORM = 'gcc'
EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mfpu=neon-vfpv4 -mfloat-abi=softfp -march=armv7-a -mtune=cortex-a7 -ftree-vectorize -ffast-math'
CFLAGS = DEVICE + ' -Wall'
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
CXXFLAGS = CFLAGS
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n'

372
bsp/stm32f107/.config Normal file
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@ -0,0 +1,372 @@
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_MEMHEAP=y
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
# CONFIG_RT_USING_MODULE is not set
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M3=y
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
# CONFIG_RT_USING_USER_MAIN is not set
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
CONFIG_RT_DFS_ELM_USE_LFN_3=y
CONFIG_RT_DFS_ELM_USE_LFN=3
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_POSIX is not set
# CONFIG_RT_USING_LWP is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# light weight TCP/IP stack
#
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
# CONFIG_RT_LWIP_RAW is not set
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=16
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_DEBUG is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
#
# ARM CMSIS
#
# CONFIG_RT_USING_CMSIS_OS is not set
CONFIG_RT_USING_RTT_CMSIS=y
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
#
# sample package
#
# CONFIG_PKG_USING_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
CONFIG_SOC_STM32F1=y
# CONFIG_RT_USING_UART1 is not set
CONFIG_RT_USING_UART2=y
# CONFIG_RT_USING_UART3 is not set

36
bsp/stm32f107/Kconfig Normal file
View File

@ -0,0 +1,36 @@
mainmenu "RT-Thread Configuration"
config $BSP_DIR
string
option env="BSP_ROOT"
default "."
config $RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example: default "F:/git_repositories/rt-thread"
config $PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
config $ENV_DIR
string
option env="ENV_ROOT"
default "/"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_STM32F1
bool
select ARCH_ARM_CORTEX_M3
default y
source "$BSP_DIR/drivers/Kconfig"

11
bsp/stm32f107/applications/application.c
View File

@ -10,6 +10,7 @@
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2018-08-17 whj remove finsh_set_device add components
*/
/**
@ -38,6 +39,11 @@ extern int lwip_system_init(void);
void rt_init_thread_entry(void* parameter)
{
#ifdef RT_USING_COMPONENTS_INIT
/* initialization RT-Thread Components */
rt_components_init();
#endif
{
extern void rt_platform_init(void);
rt_platform_init();
@ -72,11 +78,6 @@ void rt_init_thread_entry(void* parameter)
rt_kprintf("TCP/IP initialized!\n");
#endif
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
finsh_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
int rt_application_init(void)

21
bsp/stm32f107/drivers/Kconfig Normal file
View File

@ -0,0 +1,21 @@
config RT_USING_UART1
bool "Enable UART1 (PA9/10)"
default n
config RT_USING_UART2
bool "Enable UART2 (PD5/6)"
default y
config RT_USING_UART3
bool "Enable UART3 (PC10/11)"
default n
config BSP_USING_RTC
bool "Enable RTC"
select RT_USING_RTC
default n
config BSP_USING_PIN
bool "Enable PIN device for GPIO"
select RT_USING_PIN
default y

7
bsp/stm32f107/drivers/SConscript
View File

@ -16,6 +16,13 @@ platform.c
if GetDepend('RT_USING_LWIP'):
src += ['stm32_eth.c']
if GetDepend(['RT_USING_PIN']):
src += ['gpio.c']
# add Ethernet drivers.
if GetDepend('RT_USING_RTC'):
src += ['stm32f1_rtc.c']
if GetDepend('RT_USING_SPI'):
src += ['rt_stm32f10x_spi.c']

7
bsp/stm32f107/drivers/board.c
View File

@ -10,6 +10,7 @@
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2018-08-17 whj add to new rt_console_set_device
*/
#include <rthw.h>
@ -67,8 +68,14 @@ void rt_hw_board_init(void)
/* Configure the SysTick */
SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND );
rt_components_board_init();
rt_hw_usart_init();
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
/*@}*/

865
bsp/stm32f107/drivers/gpio.c Normal file
View File

@ -0,0 +1,865 @@
/*
* File : gpio.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2015-03-24 Bright the first version
* 2016-05-23 Margguo@gmail.com Add 48 pins IC define
*/
#include <rthw.h>
#include <rtdevice.h>
#include <board.h>
#ifdef RT_USING_PIN
#define STM32F10X_PIN_NUMBERS 100 //[48, 64, 100, 144 ]
#define __STM32_PIN(index, rcc, gpio, gpio_index) { 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index, GPIO_PortSourceGPIO##gpio, GPIO_PinSource##gpio_index}
#define __STM32_PIN_DEFAULT {-1, 0, 0, 0, 0, 0}
/* STM32 GPIO driver */
struct pin_index
{
int index;
uint32_t rcc;
GPIO_TypeDef *gpio;
uint32_t pin;
uint8_t port_source;
uint8_t pin_source;
};
static const struct pin_index pins[] =
{
#if (STM32F10X_PIN_NUMBERS == 48)
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(2, APB2, C, 13),
__STM32_PIN(3, APB2, C, 14),
__STM32_PIN(4, APB2, C, 15),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(10, APB2, A, 0),
__STM32_PIN(11, APB2, A, 1),
__STM32_PIN(12, APB2, A, 2),
__STM32_PIN(13, APB2, A, 3),
__STM32_PIN(14, APB2, A, 4),
__STM32_PIN(15, APB2, A, 5),
__STM32_PIN(16, APB2, A, 6),
__STM32_PIN(17, APB2, A, 7),
__STM32_PIN(18, APB2, B, 0),
__STM32_PIN(19, APB2, B, 1),
__STM32_PIN(20, APB2, B, 2),
__STM32_PIN(21, APB2, B, 10),
__STM32_PIN(22, APB2, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(25, APB2, B, 12),
__STM32_PIN(26, APB2, B, 13),
__STM32_PIN(27, APB2, B, 14),
__STM32_PIN(28, APB2, B, 15),
__STM32_PIN(29, APB2, A, 8),
__STM32_PIN(30, APB2, A, 9),
__STM32_PIN(31, APB2, A, 10),
__STM32_PIN(32, APB2, A, 11),
__STM32_PIN(33, APB2, A, 12),
__STM32_PIN(34, APB2, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(37, APB2, A, 14),
__STM32_PIN(38, APB2, A, 15),
__STM32_PIN(39, APB2, B, 3),
__STM32_PIN(40, APB2, B, 4),
__STM32_PIN(41, APB2, B, 5),
__STM32_PIN(42, APB2, B, 6),
__STM32_PIN(43, APB2, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(45, APB2, B, 8),
__STM32_PIN(46, APB2, B, 9),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
#if (STM32F10X_PIN_NUMBERS == 64)
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(2, APB2, C, 13),
__STM32_PIN(3, APB2, C, 14),
__STM32_PIN(4, APB2, C, 15),
__STM32_PIN(5, APB2, D, 0),
__STM32_PIN(6, APB2, D, 1),
__STM32_PIN_DEFAULT,
__STM32_PIN(8, APB2, C, 0),
__STM32_PIN(9, APB2, C, 1),
__STM32_PIN(10, APB2, C, 2),
__STM32_PIN(11, APB2, C, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(14, APB2, A, 0),
__STM32_PIN(15, APB2, A, 1),
__STM32_PIN(16, APB2, A, 2),
__STM32_PIN(17, APB2, A, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(20, APB2, A, 4),
__STM32_PIN(21, APB2, A, 5),
__STM32_PIN(22, APB2, A, 6),
__STM32_PIN(23, APB2, A, 7),
__STM32_PIN(24, APB2, C, 4),
__STM32_PIN(25, APB2, C, 5),
__STM32_PIN(26, APB2, B, 0),
__STM32_PIN(27, APB2, B, 1),
__STM32_PIN(28, APB2, B, 2),
__STM32_PIN(29, APB2, B, 10),
__STM32_PIN(30, APB2, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(33, APB2, B, 12),
__STM32_PIN(34, APB2, B, 13),
__STM32_PIN(35, APB2, B, 14),
__STM32_PIN(36, APB2, B, 15),
__STM32_PIN(37, APB2, C, 6),
__STM32_PIN(38, APB2, C, 7),
__STM32_PIN(39, APB2, C, 8),
__STM32_PIN(40, APB2, C, 9),
__STM32_PIN(41, APB2, A, 8),
__STM32_PIN(42, APB2, A, 9),
__STM32_PIN(43, APB2, A, 10),
__STM32_PIN(44, APB2, A, 11),
__STM32_PIN(45, APB2, A, 12),
__STM32_PIN(46, APB2, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(49, APB2, A, 14),
__STM32_PIN(50, APB2, A, 15),
__STM32_PIN(51, APB2, C, 10),
__STM32_PIN(52, APB2, C, 11),
__STM32_PIN(53, APB2, C, 12),
__STM32_PIN(54, APB2, D, 2),
__STM32_PIN(55, APB2, B, 3),
__STM32_PIN(56, APB2, B, 4),
__STM32_PIN(57, APB2, B, 5),
__STM32_PIN(58, APB2, B, 6),
__STM32_PIN(59, APB2, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(61, APB2, B, 8),
__STM32_PIN(62, APB2, B, 9),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
#if (STM32F10X_PIN_NUMBERS == 100)
__STM32_PIN_DEFAULT,
__STM32_PIN(1, APB2, E, 2),
__STM32_PIN(2, APB2, E, 3),
__STM32_PIN(3, APB2, E, 4),
__STM32_PIN(4, APB2, E, 5),
__STM32_PIN(5, APB2, E, 6),
__STM32_PIN_DEFAULT,
__STM32_PIN(7, APB2, C, 13),
__STM32_PIN(8, APB2, C, 14),
__STM32_PIN(9, APB2, C, 15),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(15, APB2, C, 0),
__STM32_PIN(16, APB2, C, 1),
__STM32_PIN(17, APB2, C, 2),
__STM32_PIN(18, APB2, C, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(23, APB2, A, 0),
__STM32_PIN(24, APB2, A, 1),
__STM32_PIN(25, APB2, A, 2),
__STM32_PIN(26, APB2, A, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(29, APB2, A, 4),
__STM32_PIN(30, APB2, A, 5),
__STM32_PIN(31, APB2, A, 6),
__STM32_PIN(32, APB2, A, 7),
__STM32_PIN(33, APB2, C, 4),
__STM32_PIN(34, APB2, C, 5),
__STM32_PIN(35, APB2, B, 0),
__STM32_PIN(36, APB2, B, 1),
__STM32_PIN(37, APB2, B, 2),
__STM32_PIN(38, APB2, E, 7),
__STM32_PIN(39, APB2, E, 8),
__STM32_PIN(40, APB2, E, 9),
__STM32_PIN(41, APB2, E, 10),
__STM32_PIN(42, APB2, E, 11),
__STM32_PIN(43, APB2, E, 12),
__STM32_PIN(44, APB2, E, 13),
__STM32_PIN(45, APB2, E, 14),
__STM32_PIN(46, APB2, E, 15),
__STM32_PIN(47, APB2, B, 10),
__STM32_PIN(48, APB2, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(51, APB2, B, 12),
__STM32_PIN(52, APB2, B, 13),
__STM32_PIN(53, APB2, B, 14),
__STM32_PIN(54, APB2, B, 15),
__STM32_PIN(55, APB2, D, 8),
__STM32_PIN(56, APB2, D, 9),
__STM32_PIN(57, APB2, D, 10),
__STM32_PIN(58, APB2, D, 11),
__STM32_PIN(59, APB2, D, 12),
__STM32_PIN(60, APB2, D, 13),
__STM32_PIN(61, APB2, D, 14),
__STM32_PIN(62, APB2, D, 15),
__STM32_PIN(63, APB2, C, 6),
__STM32_PIN(64, APB2, C, 7),
__STM32_PIN(65, APB2, C, 8),
__STM32_PIN(66, APB2, C, 9),
__STM32_PIN(67, APB2, A, 8),
__STM32_PIN(68, APB2, A, 9),
__STM32_PIN(69, APB2, A, 10),
__STM32_PIN(70, APB2, A, 11),
__STM32_PIN(71, APB2, A, 12),
__STM32_PIN(72, APB2, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(76, APB2, A, 14),
__STM32_PIN(77, APB2, A, 15),
__STM32_PIN(78, APB2, C, 10),
__STM32_PIN(79, APB2, C, 11),
__STM32_PIN(80, APB2, C, 12),
__STM32_PIN(81, APB2, D, 0),
__STM32_PIN(82, APB2, D, 1),
__STM32_PIN(83, APB2, D, 2),
__STM32_PIN(84, APB2, D, 3),
__STM32_PIN(85, APB2, D, 4),
__STM32_PIN(86, APB2, D, 5),
__STM32_PIN(87, APB2, D, 6),
__STM32_PIN(88, APB2, D, 7),
__STM32_PIN(89, APB2, B, 3),
__STM32_PIN(90, APB2, B, 4),
__STM32_PIN(91, APB2, B, 5),
__STM32_PIN(92, APB2, B, 6),
__STM32_PIN(93, APB2, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(95, APB2, B, 8),
__STM32_PIN(96, APB2, B, 9),
__STM32_PIN(97, APB2, E, 0),
__STM32_PIN(98, APB2, E, 1),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
#if (STM32F10X_PIN_NUMBERS == 144)
__STM32_PIN_DEFAULT,
__STM32_PIN(1, APB2, E, 2),
__STM32_PIN(2, APB2, E, 3),
__STM32_PIN(3, APB2, E, 4),
__STM32_PIN(4, APB2, E, 5),
__STM32_PIN(5, APB2, E, 6),
__STM32_PIN_DEFAULT,
__STM32_PIN(7, APB2, C, 13),
__STM32_PIN(8, APB2, C, 14),
__STM32_PIN(9, APB2, C, 15),
__STM32_PIN(10, APB2, F, 0),
__STM32_PIN(11, APB2, F, 1),
__STM32_PIN(12, APB2, F, 2),
__STM32_PIN(13, APB2, F, 3),
__STM32_PIN(14, APB2, F, 4),
__STM32_PIN(15, APB2, F, 5),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(18, APB2, F, 6),
__STM32_PIN(19, APB2, F, 7),
__STM32_PIN(20, APB2, F, 8),
__STM32_PIN(21, APB2, F, 9),
__STM32_PIN(22, APB2, F, 10),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(26, APB2, C, 0),
__STM32_PIN(27, APB2, C, 1),
__STM32_PIN(28, APB2, C, 2),
__STM32_PIN(29, APB2, C, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(34, APB2, A, 0),
__STM32_PIN(35, APB2, A, 1),
__STM32_PIN(36, APB2, A, 2),
__STM32_PIN(37, APB2, A, 3),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(40, APB2, A, 4),
__STM32_PIN(41, APB2, A, 5),
__STM32_PIN(42, APB2, A, 6),
__STM32_PIN(43, APB2, A, 7),
__STM32_PIN(44, APB2, C, 4),
__STM32_PIN(45, APB2, C, 5),
__STM32_PIN(46, APB2, B, 0),
__STM32_PIN(47, APB2, B, 1),
__STM32_PIN(48, APB2, B, 2),
__STM32_PIN(49, APB2, F, 11),
__STM32_PIN(50, APB2, F, 12),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(53, APB2, F, 13),
__STM32_PIN(54, APB2, F, 14),
__STM32_PIN(55, APB2, F, 15),
__STM32_PIN(56, APB2, G, 0),
__STM32_PIN(57, APB2, G, 1),
__STM32_PIN(58, APB2, E, 7),
__STM32_PIN(59, APB2, E, 8),
__STM32_PIN(60, APB2, E, 9),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(63, APB2, E, 10),
__STM32_PIN(64, APB2, E, 11),
__STM32_PIN(65, APB2, E, 12),
__STM32_PIN(66, APB2, E, 13),
__STM32_PIN(67, APB2, E, 14),
__STM32_PIN(68, APB2, E, 15),
__STM32_PIN(69, APB2, B, 10),
__STM32_PIN(70, APB2, B, 11),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(73, APB2, B, 12),
__STM32_PIN(74, APB2, B, 13),
__STM32_PIN(75, APB2, B, 14),
__STM32_PIN(76, APB2, B, 15),
__STM32_PIN(77, APB2, D, 8),
__STM32_PIN(78, APB2, D, 9),
__STM32_PIN(79, APB2, D, 10),
__STM32_PIN(80, APB2, D, 11),
__STM32_PIN(81, APB2, D, 12),
__STM32_PIN(82, APB2, D, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(85, APB2, D, 14),
__STM32_PIN(86, APB2, D, 15),
__STM32_PIN(87, APB2, G, 2),
__STM32_PIN(88, APB2, G, 3),
__STM32_PIN(89, APB2, G, 4),
__STM32_PIN(90, APB2, G, 5),
__STM32_PIN(91, APB2, G, 6),
__STM32_PIN(92, APB2, G, 7),
__STM32_PIN(93, APB2, G, 8),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(96, APB2, C, 6),
__STM32_PIN(97, APB2, C, 7),
__STM32_PIN(98, APB2, C, 8),
__STM32_PIN(99, APB2, C, 9),
__STM32_PIN(100, APB2, A, 8),
__STM32_PIN(101, APB2, A, 9),
__STM32_PIN(102, APB2, A, 10),
__STM32_PIN(103, APB2, A, 11),
__STM32_PIN(104, APB2, A, 12),
__STM32_PIN(105, APB2, A, 13),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(109, APB2, A, 14),
__STM32_PIN(110, APB2, A, 15),
__STM32_PIN(111, APB2, C, 10),
__STM32_PIN(112, APB2, C, 11),
__STM32_PIN(113, APB2, C, 12),
__STM32_PIN(114, APB2, D, 0),
__STM32_PIN(115, APB2, D, 1),
__STM32_PIN(116, APB2, D, 2),
__STM32_PIN(117, APB2, D, 3),
__STM32_PIN(118, APB2, D, 4),
__STM32_PIN(119, APB2, D, 5),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(122, APB2, D, 6),
__STM32_PIN(123, APB2, D, 7),
__STM32_PIN(124, APB2, G, 9),
__STM32_PIN(125, APB2, G, 10),
__STM32_PIN(126, APB2, G, 11),
__STM32_PIN(127, APB2, G, 12),
__STM32_PIN(128, APB2, G, 13),
__STM32_PIN(129, APB2, G, 14),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
__STM32_PIN(132, APB2, G, 15),
__STM32_PIN(133, APB2, B, 3),
__STM32_PIN(134, APB2, B, 4),
__STM32_PIN(135, APB2, B, 5),
__STM32_PIN(136, APB2, B, 6),
__STM32_PIN(137, APB2, B, 7),
__STM32_PIN_DEFAULT,
__STM32_PIN(139, APB2, B, 8),
__STM32_PIN(140, APB2, B, 9),
__STM32_PIN(141, APB2, E, 0),
__STM32_PIN(142, APB2, E, 1),
__STM32_PIN_DEFAULT,
__STM32_PIN_DEFAULT,
#endif
};
struct pin_irq_map
{
rt_uint16_t pinbit;
rt_uint32_t irqbit;
enum IRQn irqno;
};
static const struct pin_irq_map pin_irq_map[] =
{
{GPIO_Pin_0, EXTI_Line0, EXTI0_IRQn },
{GPIO_Pin_1, EXTI_Line1, EXTI1_IRQn },
{GPIO_Pin_2, EXTI_Line2, EXTI2_IRQn },
{GPIO_Pin_3, EXTI_Line3, EXTI3_IRQn },
{GPIO_Pin_4, EXTI_Line4, EXTI4_IRQn },
{GPIO_Pin_5, EXTI_Line5, EXTI9_5_IRQn },
{GPIO_Pin_6, EXTI_Line6, EXTI9_5_IRQn },
{GPIO_Pin_7, EXTI_Line7, EXTI9_5_IRQn },
{GPIO_Pin_8, EXTI_Line8, EXTI9_5_IRQn },
{GPIO_Pin_9, EXTI_Line9, EXTI9_5_IRQn },
{GPIO_Pin_10, EXTI_Line10, EXTI15_10_IRQn},
{GPIO_Pin_11, EXTI_Line11, EXTI15_10_IRQn},
{GPIO_Pin_12, EXTI_Line12, EXTI15_10_IRQn},
{GPIO_Pin_13, EXTI_Line13, EXTI15_10_IRQn},
{GPIO_Pin_14, EXTI_Line14, EXTI15_10_IRQn},
{GPIO_Pin_15, EXTI_Line15, EXTI15_10_IRQn},
};
struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
};
#define ITEM_NUM(items) sizeof(items)/sizeof(items[0])
const struct pin_index *get_pin(uint8_t pin)
{
const struct pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->index == -1)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
};
void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
const struct pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
if (value == PIN_LOW)
{
GPIO_ResetBits(index->gpio, index->pin);
}
else
{
GPIO_SetBits(index->gpio, index->pin);
}
}
int stm32_pin_read(rt_device_t dev, rt_base_t pin)
{
int value;
const struct pin_index *index;
value = PIN_LOW;
index = get_pin(pin);
if (index == RT_NULL)
{
return value;
}
if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET)
{
value = PIN_LOW;
}
else
{
value = PIN_HIGH;
}
return value;
}
void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
GPIO_InitTypeDef GPIO_InitStructure;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
/* GPIO Periph clock enable */
RCC_APB2PeriphClockCmd(index->rcc, ENABLE);
/* Configure GPIO_InitStructure */
GPIO_InitStructure.GPIO_Pin = index->pin;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
if (mode == PIN_MODE_OUTPUT)
{
/* output setting */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
}
else if (mode == PIN_MODE_INPUT)
{
/* input setting: not pull. */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
else if (mode == PIN_MODE_INPUT_PULLUP)
{
/* input setting: pull up. */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
}
else
{
/* input setting:default. */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
}
GPIO_Init(index->gpio, &GPIO_InitStructure);
}
rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
{
int i;
for(i = 0; i < 32; i++)
{
if((0x01 << i) == bit)
{
return i;
}
}
return -1;
}
rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
{
rt_int32_t mapindex = bit2bitno(pinbit);
if(mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
{
return RT_NULL;
}
return &pin_irq_map[mapindex];
};
rt_err_t stm32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
{
return -RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if(pin_irq_hdr_tab[irqindex].pin == pin &&
pin_irq_hdr_tab[irqindex].hdr == hdr &&
pin_irq_hdr_tab[irqindex].mode == mode &&
pin_irq_hdr_tab[irqindex].args == args
)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if(pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return -RT_EBUSY;
}
pin_irq_hdr_tab[irqindex].pin = pin;
pin_irq_hdr_tab[irqindex].hdr = hdr;
pin_irq_hdr_tab[irqindex].mode = mode;
pin_irq_hdr_tab[irqindex].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t stm32_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
{
const struct pin_index *index;
rt_base_t level;
rt_int32_t irqindex = -1;
index = get_pin(pin);
if (index == RT_NULL)
{
return -RT_ENOSYS;
}
irqindex = bit2bitno(index->pin);
if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if(pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
pin_irq_hdr_tab[irqindex].pin = -1;
pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
pin_irq_hdr_tab[irqindex].mode = 0;
pin_irq_hdr_tab[irqindex].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t stm32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
rt_uint32_t enabled)
{
const struct pin_index *index;
const struct pin_irq_map *irqmap;
rt_base_t level;
rt_int32_t irqindex = -1;
GPIO_InitTypeDef GPIO_InitStructure;
NVIC_InitTypeDef NVIC_InitStructure;
EXTI_InitTypeDef EXTI_InitStructure;
index = get_pin(pin);
if (index == RT_NULL)
{
return -RT_ENOSYS;
}
if(enabled == PIN_IRQ_ENABLE)
{
irqindex = bit2bitno(index->pin);
if(irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
{
return -RT_ENOSYS;
}
level = rt_hw_interrupt_disable();
if(pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return -RT_ENOSYS;
}
irqmap = &pin_irq_map[irqindex];
/* GPIO Periph clock enable */
RCC_APB2PeriphClockCmd(index->rcc, ENABLE);
/* Configure GPIO_InitStructure */
GPIO_InitStructure.GPIO_Pin = index->pin;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(index->gpio, &GPIO_InitStructure);
NVIC_InitStructure.NVIC_IRQChannel= irqmap->irqno;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority= 2;
NVIC_InitStructure.NVIC_IRQChannelSubPriority= 2;
NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;
NVIC_Init(&NVIC_InitStructure);
GPIO_EXTILineConfig(index->port_source, index->pin_source);
EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
switch(pin_irq_hdr_tab[irqindex].mode)
{
case PIN_IRQ_MODE_RISING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
break;
case PIN_IRQ_MODE_FALLING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
break;
case PIN_IRQ_MODE_RISING_FALLING:
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
break;
}
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
EXTI_Init(&EXTI_InitStructure);
rt_hw_interrupt_enable(level);
}
else if(enabled == PIN_IRQ_DISABLE)
{
irqmap = get_pin_irq_map(index->pin);
if(irqmap == RT_NULL)
{
return -RT_ENOSYS;
}
EXTI_InitStructure.EXTI_Line = irqmap->irqbit;
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
EXTI_InitStructure.EXTI_LineCmd = DISABLE;
EXTI_Init(&EXTI_InitStructure);
}
else
{
return -RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops _stm32_pin_ops =
{
stm32_pin_mode,
stm32_pin_write,
stm32_pin_read,
stm32_pin_attach_irq,
stm32_pin_detach_irq,
stm32_pin_irq_enable,
};
int stm32_hw_pin_init(void)
{
int result;
result = rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL);
return result;
}
INIT_BOARD_EXPORT(stm32_hw_pin_init);
rt_inline void pin_irq_hdr(int irqno)
{
EXTI_ClearITPendingBit(pin_irq_map[irqno].irqbit);
if(pin_irq_hdr_tab[irqno].hdr)
{
pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
}
}
void EXTI0_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(0);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI1_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(1);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI2_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(2);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(3);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI4_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
pin_irq_hdr(4);
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI9_5_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(EXTI_GetITStatus(EXTI_Line5) != RESET)
{
pin_irq_hdr(5);
}
if(EXTI_GetITStatus(EXTI_Line6) != RESET)
{
pin_irq_hdr(6);
}
if(EXTI_GetITStatus(EXTI_Line7) != RESET)
{
pin_irq_hdr(7);
}
if(EXTI_GetITStatus(EXTI_Line8) != RESET)
{
pin_irq_hdr(8);
}
if(EXTI_GetITStatus(EXTI_Line9) != RESET)
{
pin_irq_hdr(9);
}
/* leave interrupt */
rt_interrupt_leave();
}
void EXTI15_10_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if(EXTI_GetITStatus(EXTI_Line10) != RESET)
{
pin_irq_hdr(10);
}
if(EXTI_GetITStatus(EXTI_Line11) != RESET)
{
pin_irq_hdr(11);
}
if(EXTI_GetITStatus(EXTI_Line12) != RESET)
{
pin_irq_hdr(12);
}
if(EXTI_GetITStatus(EXTI_Line13) != RESET)
{
pin_irq_hdr(13);
}
if(EXTI_GetITStatus(EXTI_Line14) != RESET)
{
pin_irq_hdr(14);
}
if(EXTI_GetITStatus(EXTI_Line15) != RESET)
{
pin_irq_hdr(15);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif

30
bsp/stm32f107/drivers/gpio.h Normal file
View File

@ -0,0 +1,30 @@
/*
* File : gpio.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2015, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2015-01-05 Bernard the first version
*/
#ifndef GPIO_H__
#define GPIO_H__
struct stm32_hw_pin_userdata
{
int pin;
uint32_t mode;
};
#define PIN_USERDATA_END {-1,0}
extern struct stm32_hw_pin_userdata stm32_pins[];
int stm32_hw_pin_init(void);
#endif

163
bsp/stm32f107/drivers/stm32f1_rtc.c Normal file
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@ -0,0 +1,163 @@
/*
* File : stm32f1_rtc.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version.
* 2011-11-26 aozima implementation time.
* 2015-07-16 FlyM rename rtc to stm32f1_rtc. remove finsh export function
*/
#include <rtthread.h>
#include <stm32f10x.h>
#include "stm32f1_rtc.h"
static struct rt_device rtc;
static rt_err_t rt_rtc_open(rt_device_t dev, rt_uint16_t oflag)
{
if (dev->rx_indicate != RT_NULL)
{
/* Open Interrupt */
}
return RT_EOK;
}
static rt_size_t rt_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
return 0;
}
static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
{
rt_time_t *time;
RT_ASSERT(dev != RT_NULL);
switch (cmd)
{
case RT_DEVICE_CTRL_RTC_GET_TIME:
time = (rt_time_t *)args;
/* read device */
*time = RTC_GetCounter();
break;
case RT_DEVICE_CTRL_RTC_SET_TIME:
{
time = (rt_time_t *)args;
/* Enable PWR and BKP clocks */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
/* Allow access to BKP Domain */
PWR_BackupAccessCmd(ENABLE);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
/* Change the current time */
RTC_SetCounter(*time);
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
BKP_WriteBackupRegister(BKP_DR1, 0xA5A5);
}
break;
}
return RT_EOK;
}
/*******************************************************************************
* Function Name : RTC_Configuration
* Description : Configures the RTC.
* Input : None
* Output : None
* Return : 0 reday,-1 error.
*******************************************************************************/
int RTC_Configuration(void)
{
u32 count=0x200000;
/* Enable PWR and BKP clocks */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
/* Allow access to BKP Domain */
PWR_BackupAccessCmd(ENABLE);
/* Reset Backup Domain */
BKP_DeInit();
/* Enable LSE */
RCC_LSEConfig(RCC_LSE_ON);
/* Wait till LSE is ready */
while ( (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) && (--count) );
if ( count == 0 )
{
return -1;
}
/* Select LSE as RTC Clock Source */
RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
/* Enable RTC Clock */
RCC_RTCCLKCmd(ENABLE);
/* Wait for RTC registers synchronization */
RTC_WaitForSynchro();
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
/* Set RTC prescaler: set RTC period to 1sec */
RTC_SetPrescaler(32767); /* RTC period = RTCCLK/RTC_PR = (32.768 KHz)/(32767+1) */
/* Wait until last write operation on RTC registers has finished */
RTC_WaitForLastTask();
return 0;
}
void rt_hw_rtc_init(void)
{
rtc.type = RT_Device_Class_RTC;
if (BKP_ReadBackupRegister(BKP_DR1) != 0xA5A5)
{
rt_kprintf("rtc is not configured\n");
rt_kprintf("please configure with set_date and set_time\n");
if ( RTC_Configuration() != 0)
{
rt_kprintf("rtc configure fail...\r\n");
return ;
}
}
else
{
/* Wait for RTC registers synchronization */
RTC_WaitForSynchro();
}
/* register rtc device */
rtc.init = RT_NULL;
rtc.open = rt_rtc_open;
rtc.close = RT_NULL;
rtc.read = rt_rtc_read;
rtc.write = RT_NULL;
rtc.control = rt_rtc_control;
/* no private */
rtc.user_data = RT_NULL;
rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
return;
}

20
bsp/stm32f107/drivers/stm32f1_rtc.h Normal file
View File

@ -0,0 +1,20 @@
/*
* File : stm32f1_rtc.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
*/
#ifndef __STM32F1_RTC_H__
#define __STM32F1_RTC_H__
void rt_hw_rtc_init(void);
#endif

92
bsp/stm32f107/drivers/usart.c
View File

@ -8,11 +8,12 @@
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode
* 2013-05-13 aozima update for kehong-lingtai.
* 2015-01-31 armink make sure the serial transmit complete in putc()
* Date Author Notes
* 2009-01-05 Bernard the first version
* 2010-03-29 Bernard remove interrupt Tx and DMA Rx mode
* 2013-05-13 aozima update for kehong-lingtai.
* 2015-01-31 armink make sure the serial transmit complete in putc()
* 2018-08-17 whj add to usart3
*/
#include "stm32f10x.h"
@ -38,6 +39,11 @@
#define UART2_GPIO GPIOA
#endif
/* USART3_REMAP = 1 */
#define UART3_GPIO_TX GPIO_Pin_10
#define UART3_GPIO_RX GPIO_Pin_11
#define UART3_GPIO GPIOC
/* STM32 uart driver */
struct stm32_uart
{
@ -184,7 +190,7 @@ void USART1_IRQHandler(void)
}
if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_ORE) == SET)
{
USART_ReceiveData(uart->uart_device);
stm32_getc(&serial1);
}
/* leave interrupt */
rt_interrupt_leave();
@ -221,7 +227,7 @@ void USART2_IRQHandler(void)
}
if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_ORE) == SET)
{
USART_ReceiveData(uart->uart_device);
stm32_getc(&serial2);
}
/* leave interrupt */
@ -229,6 +235,44 @@ void USART2_IRQHandler(void)
}
#endif /* RT_USING_UART2 */
#if defined(RT_USING_UART3)
/* UART1 device driver structure */
struct stm32_uart uart3 =
{
USART3,
USART3_IRQn,
};
struct rt_serial_device serial3;
void USART3_IRQHandler(void)
{
struct stm32_uart* uart;
uart = &uart3;
/* enter interrupt */
rt_interrupt_enter();
if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
{
rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
}
if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
{
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
}
if (USART_GetFlagStatus(uart->uart_device, USART_FLAG_ORE) == SET)
{
stm32_getc(&serial3);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART3 */
static void RCC_Configuration(void)
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
@ -252,6 +296,11 @@ static void RCC_Configuration(void)
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
#endif /* RT_USING_UART2 */
#if defined(RT_USING_UART3)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC, ENABLE);
GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE);
#endif /* RT_USING_UART3 */
}
static void GPIO_Configuration(void)
@ -281,6 +330,18 @@ static void GPIO_Configuration(void)
GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX;
GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
#endif /* RT_USING_UART2 */
#if defined(RT_USING_UART3)
/* Configure USART3 Rx (PC.11) as input floating */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX;
GPIO_Init(UART3_GPIO, &GPIO_InitStructure);
/* Configure USART3 Tx (PC.10) as alternate function push-pull */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Pin = UART3_GPIO_TX;
GPIO_Init(UART3_GPIO, &GPIO_InitStructure);
#endif /* RT_USING_UART3 */
}
static void NVIC_Configuration(struct stm32_uart* uart)
@ -327,9 +388,24 @@ void rt_hw_usart_init(void)
NVIC_Configuration(&uart2);
/* register UART1 device */
/* register UART2 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* RT_USING_UART2 */
#if defined(RT_USING_UART3)
uart = &uart3;
config.baud_rate = BAUD_RATE_115200;
serial2.ops = &stm32_uart_ops;
serial2.config = config;
NVIC_Configuration(&uart3);
/* register UART3 device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* RT_USING_UART3 */
}

1163
bsp/stm32f107/project.uvprojx
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File diff suppressed because it is too large Load Diff

291
bsp/stm32f107/rtconfig.h
View File

@ -1,158 +1,207 @@
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 8
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 8
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 32
/* Tick per Second */
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
#define RT_DEBUG
#define RT_THREAD_DEBUG
/* RT-Thread Kernel */
#define RT_NAME_MAX 8
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
/* Using Hook */
#define RT_USING_HOOK
#define RT_IDEL_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256
#define RT_DEBUG
/* Using Software Timer */
/* #define RT_USING_TIMER_SOFT */
#define RT_TIMER_THREAD_PRIO 4
#define RT_TIMER_THREAD_STACK_SIZE 512
/* Inter-Thread communication */
/* SECTION: IPC */
/* Using Semaphore*/
#define RT_USING_SEMAPHORE
/* Using Mutex */
#define RT_USING_MUTEX
/* Using Event */
#define RT_USING_EVENT
/* Using MailBox */
#define RT_USING_MAILBOX
/* Using Message Queue */
#define RT_USING_MESSAGEQUEUE
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
#define RT_USING_MEMPOOL
/* Memory Management */
/* Using Dynamic Heap Management */
#define RT_USING_MEMPOOL
#define RT_USING_MEMHEAP
#define RT_USING_SMALL_MEM
#define RT_USING_HEAP
/* Using Small MM */
#define RT_USING_SMALL_MEM
/* Kernel Device Object */
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
#define RT_USING_DEVICE_IPC
// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
#define RT_USING_SERIAL
#define RT_USING_SPI
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console*/
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart2"
#define ARCH_ARM
#define ARCH_ARM_CORTEX_M
#define ARCH_ARM_CORTEX_M3
// <string name="RT_CONSOLE_DEVICE_NAME" description="console device name" default="uart3" />
#define RT_CONSOLE_DEVICE_NAME "uart1"
// </section>
/* RT-Thread Components */
// <section name="RT_USING_COMPONENTS_INIT" description="Using components init" default="false" >
// #define RT_USING_COMPONENTS_INIT
// </section>
#define RT_USING_COMPONENTS_INIT
/* C++ features */
/* Command shell */
/* SECTION: finsh, a C-Express shell */
#define RT_USING_FINSH
/* Using symbol table */
#define FINSH_THREAD_NAME "tshell"
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_CMD_SIZE 80
#define FINSH_USING_MSH
#define FINSH_USING_MSH_DEFAULT
#define FINSH_ARG_MAX 10
/* Device virtual file system */
/* SECTION: device filesystem */
#define RT_USING_DFS
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 16
#define RT_USING_DFS_ELMFAT
/* Reentrancy (thread safe) of the FatFs module. */
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 2
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_DFS_ELM_REENTRANT
/* Number of volumes (logical drives) to be used. */
#define RT_DFS_ELM_DRIVES 2
/* #define RT_DFS_ELM_USE_LFN 1 */
#define RT_DFS_ELM_MAX_LFN 255
/* Maximum sector size to be handled. */
#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
#define RT_USING_DFS_DEVFS
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 2
/* the max number of opened files */
#define DFS_FD_MAX 4
/* Device Drivers */
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
#define RT_USING_LWIP
/* Enable ICMP protocol*/
#define RT_LWIP_ICMP
/* Enable UDP protocol*/
#define RT_LWIP_UDP
/* Enable TCP protocol*/
#define RT_LWIP_TCP
/* Enable DNS */
#define RT_LWIP_DNS
#define RT_USING_DEVICE_IPC
#define RT_PIPE_BUFSZ 512
#define RT_USING_SERIAL
#define RT_USING_PIN
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 5
/* Using USB */
/* ip address of target */
#define RT_LWIP_IPADDR "192.168.1.30"
/* gateway address of target */
#define RT_LWIP_GWADDR "192.168.1.1"
/* mask address of target */
#define RT_LWIP_MSKADDR "255.255.255.0"
/* tcp thread options */
#define RT_LWIP_TCPTHREAD_PRIORITY 12
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
/* ethernet if thread options */
#define RT_LWIP_ETHTHREAD_PRIORITY 15
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
/* TCP sender buffer space */
#define RT_LWIP_TCP_SND_BUF 8192
/* TCP receive window. */
#define RT_LWIP_TCP_WND 8192
#define CHECKSUM_CHECK_TCP 0
#define CHECKSUM_CHECK_IP 0
#define CHECKSUM_CHECK_UDP 0
#define CHECKSUM_GEN_TCP 0
#define CHECKSUM_GEN_IP 0
#define CHECKSUM_GEN_UDP 0
// <bool name="RT_USING_CMSIS_OS" description="Using CMSIS OS API" default="true" />
// #define RT_USING_CMSIS_OS
// <bool name="RT_USING_RTT_CMSIS" description="Using CMSIS in RTT" default="true" />
#define RT_USING_RTT_CMSIS
// <bool name="RT_USING_BSP_CMSIS" description="Using CMSIS in BSP" default="true" />
// #define RT_USING_BSP_CMSIS
/* POSIX layer and C standard library */
#define RT_USING_LIBC
/* Network */
/* Socket abstraction layer */
/* light weight TCP/IP stack */
#define RT_USING_LWIP
#define RT_USING_LWIP202
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 16
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_NETIF_LOOPBACK 0
/* Modbus master and slave stack */
/* AT commands */
/* VBUS(Virtual Software BUS) */
/* Utilities */
/* ARM CMSIS */
#define RT_USING_RTT_CMSIS
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* multimedia packages */
/* tools packages */
/* system packages */
/* peripheral libraries and drivers */
/* miscellaneous packages */
/* sample package */
/* example package: hello */
#define SOC_STM32F1
#define RT_USING_UART2
#endif

10
bsp/stm32f4xx-HAL/Kconfig
View File

@ -309,6 +309,16 @@ config RT_USING_UART6
bool "Using UART6"
default n
if RT_USING_CAN
config USING_BXCAN1
bool "Enable CAN1 RX:PD0 TX:PD1. Do not select HDR."
default n
config USING_BXCAN2
bool "Enable CAN2 RX:PB12 TX:PB6. Do not select HDR."
default n
endif
if RT_USING_SPI
config RT_USING_SPI1

5
bsp/stm32f4xx-HAL/drivers/SConscript
View File

@ -35,7 +35,10 @@ if GetDepend(['RT_USING_USB_HOST']):
src += ['drv_usbh.c']
if GetDepend(['RT_USING_I2C']):
src += ['drv_i2c.c']
src += ['drv_i2c.c']
if GetDepend(['RT_USING_CAN']):
src += ['drv_can.c']
if GetDepend(['RT_USING_PWM']):
src += ['drv_pwm.c']

868
bsp/stm32f4xx-HAL/drivers/drv_can.c Normal file
View File

@ -0,0 +1,868 @@
/*
* File : drv_can.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2018, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2018-08-05 Xeon Xu the first version
*/
/* Includes ------------------------------------------------------------------*/
#include "drv_can.h"
#include "board.h"
#include <rtdevice.h>
#include <rthw.h>
#include <rtthread.h>
#define BS1SHIFT 16
#define BS2SHIFT 20
#define RRESCLSHIFT 0
#define SJWSHIFT 24
#define BS1MASK ( (0x0F) << BS1SHIFT )
#define BS2MASK ( (0x07) << BS2SHIFT )
#define RRESCLMASK ( 0x3FF << RRESCLSHIFT )
#define SJWMASK ( 0x3 << SJWSHIFT )
struct stm_baud_rate_tab
{
rt_uint32_t baud_rate;
rt_uint32_t confdata;
};
/* STM32 can driver */
struct stm32_drv_can
{
CAN_HandleTypeDef CanHandle;
CanTxMsgTypeDef TxMessage;
CanRxMsgTypeDef RxMessage;
CAN_FilterConfTypeDef FilterConfig;
};
static const struct stm_baud_rate_tab can_baud_rate_tab[] =
{
{CAN1MBaud , (CAN_SJW_1TQ | CAN_BS1_2TQ | CAN_BS2_4TQ | 6)},
{CAN800kBaud, (CAN_SJW_1TQ | CAN_BS1_5TQ | CAN_BS2_7TQ | 4)},
{CAN500kBaud, (CAN_SJW_1TQ | CAN_BS1_14TQ | CAN_BS2_6TQ | 4)},
{CAN250kBaud, (CAN_SJW_1TQ | CAN_BS1_1TQ | CAN_BS2_2TQ | 42)},
{CAN125kBaud, (CAN_SJW_1TQ | CAN_BS1_1TQ | CAN_BS2_2TQ | 84)},
{CAN100kBaud, (CAN_SJW_1TQ | CAN_BS1_1TQ | CAN_BS2_1TQ | 140)},
{CAN50kBaud , (CAN_SJW_1TQ | CAN_BS1_1TQ | CAN_BS2_1TQ | 280)},
{CAN20kBaud , (CAN_SJW_1TQ | CAN_BS1_1TQ | CAN_BS2_1TQ | 700)},
{CAN10kBaud , (CAN_SJW_1TQ | CAN_BS1_3TQ | CAN_BS2_4TQ | 525)}
};
#define BAUD_DATA(TYPE,NO) \
((can_baud_rate_tab[NO].confdata & TYPE##MASK))
static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
{
rt_uint32_t len, index, default_index;
len = sizeof(can_baud_rate_tab)/sizeof(can_baud_rate_tab[0]);
default_index = len;
for(index = 0; index < len; index++)
{
if(can_baud_rate_tab[index].baud_rate == baud)
return index;
if(can_baud_rate_tab[index].baud_rate == 1000UL * 250)
default_index = index;
}
if(default_index != len)
return default_index;
return 0;
}
#ifdef USING_BXCAN1
static struct stm32_drv_can drv_can1;
struct rt_can_device dev_can1;
void CAN1_TX_IRQHandler(void)
{
CAN_HandleTypeDef *hcan;
rt_interrupt_enter();
hcan = &drv_can1.CanHandle;
HAL_CAN_IRQHandler(hcan);
if (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0))
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_TX_DONE | 0 << 8);
}
else
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_TX_FAIL | 0 << 8);
}
if (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1))
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_TX_DONE | 1 << 8);
}
else
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_TX_FAIL | 1 << 8);
}
if (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_TX_DONE | 2 << 8);
}
else
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_TX_FAIL | 2 << 8);
}
rt_interrupt_leave();
}
/**
* @brief This function handles CAN1 RX0 interrupts.
*/
void CAN1_RX0_IRQHandler(void)
{
CAN_HandleTypeDef *hcan;
hcan = &drv_can1.CanHandle;
rt_interrupt_enter();
HAL_CAN_IRQHandler(hcan);
if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0))
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_RXOF_IND | 0 << 8);
}
else
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_RX_IND | 0 << 8);
}
rt_interrupt_leave();
}
/**
* @brief This function handles CAN1 RX1 interrupts.
*/
void CAN1_RX1_IRQHandler(void)
{
CAN_HandleTypeDef *hcan;
hcan = &drv_can1.CanHandle;
rt_interrupt_enter();
HAL_CAN_IRQHandler(hcan);
if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1))
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_RXOF_IND | 1 << 8);
}
else
{
rt_hw_can_isr(&dev_can1, RT_CAN_EVENT_RX_IND | 1 << 8);
}
rt_interrupt_leave();
}
/**
* @brief This function handles CAN1 SCE interrupts.
*/
void CAN1_SCE_IRQHandler(void)
{
rt_uint32_t errtype;
CAN_HandleTypeDef *hcan;
hcan = &drv_can1.CanHandle;
errtype = hcan->Instance->ESR;
rt_interrupt_enter();
HAL_CAN_IRQHandler(hcan);
if (errtype & 0x70 && dev_can1.status.lasterrtype == (errtype & 0x70))
{
switch ((errtype & 0x70) >> 4)
{
case RT_CAN_BUS_BIT_PAD_ERR:
dev_can1.status.bitpaderrcnt++;
break;
case RT_CAN_BUS_FORMAT_ERR:
dev_can1.status.formaterrcnt++;
break;
case RT_CAN_BUS_ACK_ERR:
dev_can1.status.ackerrcnt++;
break;
case RT_CAN_BUS_IMPLICIT_BIT_ERR:
case RT_CAN_BUS_EXPLICIT_BIT_ERR:
dev_can1.status.biterrcnt++;
break;
case RT_CAN_BUS_CRC_ERR:
dev_can1.status.crcerrcnt++;
break;
}
dev_can1.status.lasterrtype = errtype & 0x70;
hcan->Instance->ESR &= ~0x70;
}
dev_can1.status.rcverrcnt = errtype >> 24;
dev_can1.status.snderrcnt = (errtype >> 16 & 0xFF);
dev_can1.status.errcode = errtype & 0x07;
hcan->Instance->MSR |= CAN_MSR_ERRI;
rt_interrupt_leave();
}
#endif // USING_BXCAN1
#ifdef USING_BXCAN2
static struct stm32_drv_can drv_can2;
struct rt_can_device dev_can2;
/**
* @brief This function handles CAN2 TX interrupts.
*/
void CAN2_TX_IRQHandler(void)
{
CAN_HandleTypeDef *hcan;
rt_interrupt_enter();
hcan = &drv_can2.CanHandle;
HAL_CAN_IRQHandler(hcan);
if (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0))
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_TX_DONE | 0 << 8);
}
else
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_TX_FAIL | 0 << 8);
}
if (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1))
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_TX_DONE | 1 << 8);
}
else
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_TX_FAIL | 1 << 8);
}
if (__HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2))
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_TX_DONE | 2 << 8);
}
else
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_TX_FAIL | 2 << 8);
}
rt_interrupt_leave();
}
/**
* @brief This function handles CAN2 RX0 interrupts.
*/
void CAN2_RX0_IRQHandler(void)
{
CAN_HandleTypeDef *hcan;
hcan = &drv_can2.CanHandle;
rt_interrupt_enter();
HAL_CAN_IRQHandler(hcan);
if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0))
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_RXOF_IND | 0 << 8);
}
else
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_RX_IND | 0 << 8);
}
rt_interrupt_leave();
}
/**
* @brief This function handles CAN2 RX1 interrupts.
*/
void CAN2_RX1_IRQHandler(void)
{
CAN_HandleTypeDef *hcan;
hcan = &drv_can2.CanHandle;
rt_interrupt_enter();
HAL_CAN_IRQHandler(hcan);
if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1))
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_RXOF_IND | 1 << 8);
}
else
{
rt_hw_can_isr(&dev_can2, RT_CAN_EVENT_RX_IND | 1 << 8);
}
rt_interrupt_leave();
}
/**
* @brief This function handles CAN2 SCE interrupts.
*/
void CAN2_SCE_IRQHandler(void)
{
rt_uint32_t errtype;
CAN_HandleTypeDef *hcan;
hcan = &drv_can2.CanHandle;
errtype = hcan->Instance->ESR;
rt_interrupt_enter();
HAL_CAN_IRQHandler(hcan);
if (errtype & 0x70 && dev_can2.status.lasterrtype == (errtype & 0x70))
{
switch ((errtype & 0x70) >> 4)
{
case RT_CAN_BUS_BIT_PAD_ERR:
dev_can2.status.bitpaderrcnt++;
break;
case RT_CAN_BUS_FORMAT_ERR:
dev_can2.status.formaterrcnt++;
break;
case RT_CAN_BUS_ACK_ERR:
dev_can2.status.ackerrcnt++;
break;
case RT_CAN_BUS_IMPLICIT_BIT_ERR:
case RT_CAN_BUS_EXPLICIT_BIT_ERR:
dev_can2.status.biterrcnt++;
break;
case RT_CAN_BUS_CRC_ERR:
dev_can2.status.crcerrcnt++;
break;
}
dev_can2.status.lasterrtype = errtype & 0x70;
hcan->Instance->ESR &= ~0x70;
}
dev_can2.status.rcverrcnt = errtype >> 24;
dev_can2.status.snderrcnt = (errtype >> 16 & 0xFF);
dev_can2.status.errcode = errtype & 0x07;
hcan->Instance->MSR |= CAN_MSR_ERRI;
rt_interrupt_leave();
}
#endif // USING_BXCAN2
/**
* @brief Error CAN callback.
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
/* TODO Error Callback */
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief Transmission complete callback in non blocking mode
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
{
switch((int)hcan->Instance)
{
case (int)CAN1:
/* User define */
break;
case (int)CAN2:
/* User define */
break;
}
}
/**
* @brief Transmission complete callback in non blocking mode
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
{
HAL_CAN_Receive_IT(hcan, CAN_FIFO0);
HAL_CAN_Receive_IT(hcan, CAN_FIFO1);
}
static rt_err_t drv_configure(struct rt_can_device *dev_can,
struct can_configure *cfg)
{
struct stm32_drv_can *drv_can;
rt_uint32_t baud_index;
CAN_InitTypeDef *drv_init;
CAN_FilterConfTypeDef *filterConf;
RT_ASSERT(dev_can);
RT_ASSERT(cfg);
drv_can = (struct stm32_drv_can *)dev_can->parent.user_data;
drv_init = &drv_can->CanHandle.Init;
drv_init->TTCM = DISABLE;
drv_init->ABOM = DISABLE;
drv_init->AWUM = DISABLE;
drv_init->NART = DISABLE;
drv_init->RFLM = DISABLE;
drv_init->TXFP = DISABLE;
switch (cfg->mode)
{
case RT_CAN_MODE_NORMAL:
drv_init->Mode = CAN_MODE_NORMAL;
break;
case RT_CAN_MODE_LISEN:
drv_init->Mode = CAN_MODE_SILENT;
break;
case RT_CAN_MODE_LOOPBACK:
drv_init->Mode = CAN_MODE_LOOPBACK;
break;
case RT_CAN_MODE_LOOPBACKANLISEN:
drv_init->Mode = CAN_MODE_SILENT_LOOPBACK;
break;
}
baud_index = get_can_baud_index(cfg->baud_rate);
drv_init->SJW = BAUD_DATA(SJW, baud_index);
drv_init->BS1 = BAUD_DATA(BS1, baud_index);
drv_init->BS2 = BAUD_DATA(BS2, baud_index);
drv_init->Prescaler = BAUD_DATA(RRESCL, baud_index);
if (HAL_CAN_Init(&drv_can->CanHandle) != HAL_OK)
{
return RT_ERROR;
}
/* Filter conf */
filterConf = &drv_can->FilterConfig;
filterConf->FilterNumber = 0;
filterConf->FilterMode = CAN_FILTERMODE_IDMASK;
filterConf->FilterScale = CAN_FILTERSCALE_32BIT;
filterConf->FilterIdHigh = 0x0000;
filterConf->FilterIdLow = 0x0000;
filterConf->FilterMaskIdHigh = 0x0000;
filterConf->FilterMaskIdLow = 0x0000;
filterConf->FilterFIFOAssignment = 0;
filterConf->FilterActivation = ENABLE;
filterConf->BankNumber = 14;
HAL_CAN_ConfigFilter(&drv_can->CanHandle, filterConf);
return RT_EOK;
}
static rt_err_t drv_control(struct rt_can_device *can, int cmd, void *arg)
{
struct stm32_drv_can *drv_can;
rt_uint32_t argval;
drv_can = (struct stm32_drv_can *) can->parent.user_data;
assert_param(drv_can != RT_NULL);
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
argval = (rt_uint32_t) arg;
if (argval == RT_DEVICE_FLAG_INT_RX)
{
if (CAN1 == drv_can->CanHandle.Instance) {
HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn);
}
else
{
HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn);
HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn);
}
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_FMP0);
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_FF0 );
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_FOV0);
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_FMP1);
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_FF1 );
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_FOV1);
}
else if (argval == RT_DEVICE_FLAG_INT_TX)
{
if (CAN1 == drv_can->CanHandle.Instance)
{
HAL_NVIC_DisableIRQ(CAN1_TX_IRQn);
}
else
{
HAL_NVIC_DisableIRQ(CAN2_TX_IRQn);
}
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_TME);
}
else if (argval == RT_DEVICE_CAN_INT_ERR)
{
if (CAN1 == drv_can->CanHandle.Instance)
{
NVIC_DisableIRQ(CAN1_SCE_IRQn);
}
else
{
NVIC_DisableIRQ(CAN2_SCE_IRQn);
}
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_BOF);
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_LEC);
__HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERR);
}
break;
case RT_DEVICE_CTRL_SET_INT:
argval = (rt_uint32_t) arg;
if (argval == RT_DEVICE_FLAG_INT_RX)
{
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_FMP0);
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_FF0);
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_FOV0);
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_FMP1);
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_FF1);
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_FOV1);
if (CAN1 == drv_can->CanHandle.Instance)
{
HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn);
}
else
{
HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);
HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn);
}
}
else if (argval == RT_DEVICE_FLAG_INT_TX)
{
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_TME);
if (CAN1 == drv_can->CanHandle.Instance)
{
HAL_NVIC_SetPriority(CAN1_TX_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(CAN1_TX_IRQn);
}
else
{
HAL_NVIC_SetPriority(CAN2_TX_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(CAN2_TX_IRQn);
}
}
else if (argval == RT_DEVICE_CAN_INT_ERR)
{
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_BOF);
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_LEC);
__HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERR);
if (CAN1 == drv_can->CanHandle.Instance)
{
HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn);
}
else
{
HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn);
}
}
break;
case RT_CAN_CMD_SET_FILTER:
/* TODO: filter*/
break;
case RT_CAN_CMD_SET_MODE:
argval = (rt_uint32_t) arg;
if (argval != RT_CAN_MODE_NORMAL ||
argval != RT_CAN_MODE_LISEN ||
argval != RT_CAN_MODE_LOOPBACK ||
argval != RT_CAN_MODE_LOOPBACKANLISEN)
{
return RT_ERROR;
}
if (argval != can->config.mode)
{
can->config.mode = argval;
if (HAL_CAN_Init(&drv_can->CanHandle) != HAL_OK)
{
return RT_ERROR;
}
}
break;
case RT_CAN_CMD_SET_BAUD:
argval = (rt_uint32_t) arg;
if (argval != CAN1MBaud &&
argval != CAN800kBaud &&
argval != CAN500kBaud &&
argval != CAN250kBaud &&
argval != CAN125kBaud &&
argval != CAN100kBaud &&
argval != CAN50kBaud &&
argval != CAN20kBaud &&
argval != CAN10kBaud)
{
return RT_ERROR;
}
if (argval != can->config.baud_rate)
{
CAN_InitTypeDef *drv_init;
rt_uint32_t baud_index;
can->config.baud_rate = argval;
drv_init = &drv_can->CanHandle.Init;
drv_init->TTCM = DISABLE;
drv_init->ABOM = DISABLE;
drv_init->AWUM = DISABLE;
drv_init->NART = DISABLE;
drv_init->RFLM = DISABLE;
drv_init->TXFP = DISABLE;
baud_index = get_can_baud_index(can->config.baud_rate);
drv_init->SJW = BAUD_DATA(SJW, baud_index);
drv_init->BS1 = BAUD_DATA(BS1, baud_index);
drv_init->BS2 = BAUD_DATA(BS2, baud_index);
drv_init->Prescaler = BAUD_DATA(RRESCL, baud_index);
if (HAL_CAN_Init(&drv_can->CanHandle) != HAL_OK)
{
return RT_ERROR;
}
}
break;
case RT_CAN_CMD_SET_PRIV:
argval = (rt_uint32_t) arg;
if (argval != RT_CAN_MODE_PRIV ||
argval != RT_CAN_MODE_NOPRIV)
{
return RT_ERROR;
}
if (argval != can->config.privmode)
{
can->config.privmode = argval;
if (HAL_CAN_Init(&drv_can->CanHandle) != HAL_OK)
{
return RT_ERROR;
}
}
break;
case RT_CAN_CMD_GET_STATUS:
{
rt_uint32_t errtype;
errtype = drv_can->CanHandle.Instance->ESR;
can->status.rcverrcnt = errtype >> 24;
can->status.snderrcnt = (errtype >> 16 & 0xFF);
can->status.errcode = errtype & 0x07;
if (arg != &can->status)
{
rt_memcpy(arg, &can->status, sizeof(can->status));
}
}
break;
}
return RT_EOK;
}
static int drv_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t boxno)
{
CAN_HandleTypeDef *hcan;
struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
hcan = &((struct stm32_drv_can *) can->parent.user_data)->CanHandle;
hcan->pTxMsg->StdId = pmsg->id;
hcan->pTxMsg->RTR = pmsg->rtr;
hcan->pTxMsg->IDE = pmsg->ide;
hcan->pTxMsg->DLC = pmsg->len;
rt_memset(&hcan->pTxMsg->Data, 0x00, 8);
/* rt_memcpy(&hcan->pTxMsg->Data, &pmsg->data, 8); */
hcan->pTxMsg->Data[0] = pmsg->data[0];
hcan->pTxMsg->Data[1] = pmsg->data[1];
hcan->pTxMsg->Data[2] = pmsg->data[2];
hcan->pTxMsg->Data[3] = pmsg->data[3];
hcan->pTxMsg->Data[4] = pmsg->data[4];
hcan->pTxMsg->Data[5] = pmsg->data[5];
hcan->pTxMsg->Data[6] = pmsg->data[6];
hcan->pTxMsg->Data[7] = pmsg->data[7];
HAL_CAN_Transmit_IT(hcan);
return RT_EOK;
}
static int drv_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t boxno)
{
CAN_HandleTypeDef *hcan;
struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
hcan = &((struct stm32_drv_can *) can->parent.user_data)->CanHandle;
pmsg->id = hcan->pRxMsg->StdId;
pmsg->rtr = hcan->pRxMsg->RTR;
pmsg->ide = hcan->pRxMsg->IDE;
pmsg->len = hcan->pRxMsg->DLC;
/* rt_memcpy(&pmsg->data, &hcan->pRxMsg->Data, 8); */
pmsg->data[0] = hcan->pRxMsg->Data[0];
pmsg->data[1] = hcan->pRxMsg->Data[1];
pmsg->data[2] = hcan->pRxMsg->Data[2];
pmsg->data[3] = hcan->pRxMsg->Data[3];
pmsg->data[4] = hcan->pRxMsg->Data[4];
pmsg->data[5] = hcan->pRxMsg->Data[5];
pmsg->data[6] = hcan->pRxMsg->Data[6];
pmsg->data[7] = hcan->pRxMsg->Data[7];
return RT_EOK;
}
static const struct rt_can_ops drv_can_ops =
{
drv_configure,
drv_control,
drv_sendmsg,
drv_recvmsg,
};
void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(canHandle->Instance==CAN1)
{
/* CAN1 clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
/**CAN1 GPIO Configuration
PD0 ------> CAN1_RX
PD1 ------> CAN1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
}
else if(canHandle->Instance==CAN2)
{
/* CAN2 clock enable */
__HAL_RCC_CAN2_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**CAN2 GPIO Configuration
PB12 ------> CAN2_RX
PB6 ------> CAN2_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_CAN2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
}
}
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle)
{
if(canHandle->Instance==CAN1)
{
/* Peripheral clock disable */
__HAL_RCC_CAN1_CLK_DISABLE();
/**CAN1 GPIO Configuration
PD0 ------> CAN1_RX
PD1 ------> CAN1_TX
*/
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_2);
HAL_NVIC_DisableIRQ(CAN1_TX_IRQn);
HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn);
}
else if(canHandle->Instance==CAN2)
{
__HAL_RCC_CAN2_CLK_DISABLE();
/**CAN2 GPIO Configuration
PB12 ------> CAN2_RX
PB6 ------> CAN2_TX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_6);
HAL_NVIC_DisableIRQ(CAN2_TX_IRQn);
HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn);
HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn);
}
}
int hw_can_init(void)
{
struct stm32_drv_can *drv_can;
struct can_configure config = CANDEFAULTCONFIG;
config.privmode = 0;
config.ticks = 50;
config.sndboxnumber = 3;
#ifdef RT_CAN_USING_HDR
config.maxhdr = 28;
#endif
#ifdef USING_BXCAN1
drv_can = &drv_can1;
drv_can->CanHandle.Instance = CAN1;
drv_can->CanHandle.pTxMsg = &drv_can->TxMessage;
drv_can->CanHandle.pRxMsg = &drv_can->RxMessage;
dev_can1.ops = &drv_can_ops;
dev_can1.config = config;
/* register CAN1 device */
rt_hw_can_register(&dev_can1, "can1",
&drv_can_ops,
drv_can);
#endif /* USING_BXCAN1 */
#ifdef USING_BXCAN2
drv_can = &drv_can2;
drv_can->CanHandle.Instance = CAN2;
drv_can->CanHandle.pTxMsg = &drv_can->TxMessage;
drv_can->CanHandle.pRxMsg = &drv_can->RxMessage;
dev_can2.ops = &drv_can_ops;
dev_can2.config = config;
/* register CAN2 device */
rt_hw_can_register(&dev_can2, "can2",
&drv_can_ops,
drv_can);
#endif /* USING_BXCAN2 */
return 0;
}
INIT_BOARD_EXPORT(hw_can_init);

23
bsp/stm32f4xx-HAL/drivers/drv_can.h Normal file
View File

@ -0,0 +1,23 @@
/*
* File : drv_can.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2018, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2018-08-05 Xeon Xu the first version
*/
#ifndef __CAN_H__
#define __CAN_H__
#ifdef __cplusplus
extern "C" {
#endif
extern int hw_can_init(void);
#ifdef __cplusplus
}
#endif
#endif /*__CAN_H__ */

4
bsp/stm32f4xx-HAL/drivers/stm32f4xx_hal_conf.h
View File

@ -52,7 +52,9 @@ extern "C" {
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
/* #define HAL_CAN_MODULE_ENABLED */
#ifdef RT_USING_CAN
#define HAL_CAN_MODULE_ENABLED
#endif
/* #define HAL_CRC_MODULE_ENABLED */
/* #define HAL_CRYP_MODULE_ENABLED */
/* #define HAL_DAC_MODULE_ENABLED */

5
components/drivers/include/drivers/spi.h
View File

@ -36,8 +36,8 @@ extern "C"{
#define RT_SPI_CPOL (1<<1) /* bit[1]:CPOL, clock polarity */
/**
* At CPOL=0 the base value of the clock is zero
* - For CPHA=0, data are captured on the clock's rising edge (low¡úhigh transition)
* and data are propagated on a falling edge (high¡úlow clock transition).
* - For CPHA=0, data are captured on the clock's rising edge (low->high transition)
* and data are propagated on a falling edge (high->low clock transition).
* - For CPHA=1, data are captured on the clock's falling edge and data are
* propagated on a rising edge.
* At CPOL=1 the base value of the clock is one (inversion of CPOL=0)
@ -118,6 +118,7 @@ struct rt_spi_device
struct rt_spi_bus *bus;
struct rt_spi_configuration config;
void *user_data;
};
#define SPI_DEVICE(dev) ((struct rt_spi_device *)(dev))

2
components/drivers/spi/sfud/LICENSE
View File

@ -1,6 +1,6 @@
The MIT License (MIT)
Copyright (c) 2016-2017 Armink (armink.ztl@gmail.com)
Copyright (c) 2016-2018 Armink (armink.ztl@gmail.com)
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the

1
components/drivers/spi/sfud/README.md
View File

@ -37,6 +37,7 @@
|[W25Q128BV](http://www.winbond.com/resource-files/w25q128bv_revh_100313_wo_automotive.pdf)|Winbond|128Mb|104Mhz|支持||
|[W25Q256FV](http://www.winbond.com/resource-files/w25q256fv%20revi%2002262016%20kms.pdf)|Winbond|256Mb|104Mhz|支持||
|[MX25L3206E](http://www.macronix.com/Lists/DataSheet/Attachments/3199/MX25L3206E,%203V,%2032Mb,%20v1.5.pdf)|Macronix|32Mb|86MHz|支持||
|[KH25L4006E](http://www.macronix.com.hk/Lists/Datasheet/Attachments/117/KH25L4006E.pdf)|Macronix|4Mb|86Mhz|支持| by [JiapengLi](https://github.com/JiapengLi)|
|[KH25L3206E](http://www.macronix.com.hk/Lists/Datasheet/Attachments/131/KH25L3206E.pdf)|Macronix|32Mb|86Mhz|支持||
|[SST25VF016B](http://ww1.microchip.com/downloads/en/DeviceDoc/20005044C.pdf)|Microchip|16Mb|50MHz|不支持| SST 已被 Microchip 收购|
|[M25P40](https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/m25p/m25p40.pdf)|Micron|4Mb|75Mhz|不支持| by [redocCheng](https://github.com/redocCheng)|

3
components/drivers/spi/sfud/inc/sfud_def.h
View File

@ -30,6 +30,7 @@
#define _SFUD_DEF_H_
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdbool.h>
#include <sfud_cfg.h>
@ -77,7 +78,7 @@ if (!(EXPR)) \
else {if (__delay_temp) {__delay_temp();} retry --;}
/* software version number */
#define SFUD_SW_VERSION "1.0.4"
#define SFUD_SW_VERSION "1.0.6"
/*
* all defined supported command
*/

4
components/drivers/spi/sfud/inc/sfud_flash_def.h
View File

@ -77,6 +77,7 @@ typedef struct {
#define SFUD_MF_ID_FUDAN 0xA1
#define SFUD_MF_ID_HYUNDAI 0xAD
#define SFUD_MF_ID_SST 0xBF
#define SFUD_MF_ID_MICRONIX 0xC2
#define SFUD_MF_ID_GIGADEVICE 0xC8
#define SFUD_MF_ID_ISSI 0xD5
#define SFUD_MF_ID_WINBOND 0xEF
@ -99,6 +100,7 @@ typedef struct {
{"GigaDevice", SFUD_MF_ID_GIGADEVICE}, \
{"ISSI", SFUD_MF_ID_ISSI}, \
{"Winbond", SFUD_MF_ID_WINBOND}, \
{"Micronix", SFUD_MF_ID_MICRONIX}, \
}
#ifdef SFUD_USING_FLASH_INFO_TABLE
@ -112,6 +114,8 @@ typedef struct {
{"AT45DB161E", SFUD_MF_ID_ATMEL, 0x26, 0x00, 2L*1024L*1024L, SFUD_WM_BYTE|SFUD_WM_DUAL_BUFFER, 512, 0x81}, \
{"W25Q40BV", SFUD_MF_ID_WINBOND, 0x40, 0x13, 512L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
{"W25Q16BV", SFUD_MF_ID_WINBOND, 0x40, 0x15, 2L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
{"W25Q128BV", SFUD_MF_ID_WINBOND, 0x40, 0x18, 16L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
{"W25Q256FV", SFUD_MF_ID_WINBOND, 0x40, 0x19, 32L*1024L*1024L, SFUD_WM_PAGE_256B, 4096, 0x20}, \
{"SST25VF016B", SFUD_MF_ID_SST, 0x25, 0x41, 2L*1024L*1024L, SFUD_WM_BYTE|SFUD_WM_AAI, 4096, 0x20}, \
{"M25P32", SFUD_MF_ID_MICRON, 0x20, 0x16, 4L*1024L*1024L, SFUD_WM_PAGE_256B, 64L*1024L, 0xD8}, \
{"M25P80", SFUD_MF_ID_MICRON, 0x20, 0x14, 1L*1024L*1024L, SFUD_WM_PAGE_256B, 64L*1024L, 0xD8}, \

2
components/drivers/spi/sfud/src/sfud.c
View File

@ -238,6 +238,8 @@ static sfud_err hardware_init(sfud_flash *flash) {
flash->chip.capacity);
} else if (flash_mf_name) {
SFUD_INFO("Find a %s flash chip. Size is %ld bytes.", flash_mf_name, flash->chip.capacity);
} else {
SFUD_INFO("Find a flash chip. Size is %ld bytes.", flash->chip.capacity);
}
}

38
components/drivers/spi/spi_flash_sfud.c
View File

@ -97,7 +97,7 @@ static rt_err_t rt_sfud_control(rt_device_t dev, int cmd, void *args) {
static rt_size_t rt_sfud_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) {
struct spi_flash_device *rtt_dev = (struct spi_flash_device *) (dev->user_data);
sfud_flash *sfud_dev = (sfud_flash *) (rtt_dev->user_data);
/* change the block device¡¯s logic address to physical address */
/* change the block device's logic address to physical address */
rt_off_t phy_pos = pos * rtt_dev->geometry.bytes_per_sector;
rt_size_t phy_size = size * rtt_dev->geometry.bytes_per_sector;
@ -111,7 +111,7 @@ static rt_size_t rt_sfud_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_si
static rt_size_t rt_sfud_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) {
struct spi_flash_device *rtt_dev = (struct spi_flash_device *) (dev->user_data);
sfud_flash *sfud_dev = (sfud_flash *) (rtt_dev->user_data);
/* change the block device¡¯s logic address to physical address */
/* change the block device's logic address to physical address */
rt_off_t phy_pos = pos * rtt_dev->geometry.bytes_per_sector;
rt_size_t phy_size = size * rtt_dev->geometry.bytes_per_sector;
@ -189,7 +189,7 @@ void sfud_log_debug(const char *file, const long line, const char *format, ...)
va_start(args, format);
rt_kprintf("[SFUD] (%s:%ld) ", file, line);
/* must use vprintf to print */
vsnprintf(log_buf, sizeof(log_buf), format, args);
rt_vsnprintf(log_buf, sizeof(log_buf), format, args);
rt_kprintf("%s\n", log_buf);
va_end(args);
}
@ -207,7 +207,7 @@ void sfud_log_info(const char *format, ...) {
va_start(args, format);
rt_kprintf("[SFUD] ");
/* must use vprintf to print */
vsnprintf(log_buf, sizeof(log_buf), format, args);
rt_vsnprintf(log_buf, sizeof(log_buf), format, args);
rt_kprintf("%s\n", log_buf);
va_end(args);
}
@ -298,6 +298,7 @@ rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const
sfud_dev->name = spi_flash_dev_name_bak;
/* accessed each other */
rtt_dev->user_data = sfud_dev;
rtt_dev->rt_spi_device->user_data = rtt_dev;
rtt_dev->flash_device.user_data = rtt_dev;
sfud_dev->user_data = rtt_dev;
/* initialize SFUD device */
@ -606,6 +607,35 @@ static void sf(uint8_t argc, char **argv) {
}
MSH_CMD_EXPORT(sf, SPI Flash operate.);
sfud_flash_t rt_sfud_flash_find(const char *spi_dev_name)
{
rt_spi_flash_device_t rtt_dev = RT_NULL;
struct rt_spi_device *rt_spi_device = RT_NULL;
sfud_flash_t sfud_dev = RT_NULL;
rt_spi_device = (struct rt_spi_device *) rt_device_find(spi_dev_name);
if (rt_spi_device == RT_NULL || rt_spi_device->parent.type != RT_Device_Class_SPIDevice)
{
rt_kprintf("ERROR: SPI device %s not found!\n", spi_dev_name);
goto error;
}
rtt_dev = (rt_spi_flash_device_t)(rt_spi_device->user_data);
if (rtt_dev && rtt_dev->user_data)
{
sfud_dev = (sfud_flash_t)(rtt_dev->user_data);
return sfud_dev;
}
else
{
rt_kprintf("ERROR: SFUD flash device not found!\n");
goto error;
}
error:
return RT_NULL;
}
#endif /* defined(RT_USING_FINSH) && defined(FINSH_USING_MSH) */
#endif /* RT_USING_SFUD */

10
components/drivers/spi/spi_flash_sfud.h
View File

@ -27,6 +27,7 @@
#include <rtthread.h>
#include "./sfud/inc/sfud.h"
#include "spi_flash.h"
/**
* Probe SPI flash by SFUD(Serial Flash Universal Driver) driver library and though SPI device.
@ -47,4 +48,13 @@ rt_spi_flash_device_t rt_sfud_flash_probe(const char *spi_flash_dev_name, const
*/
rt_err_t rt_sfud_flash_delete(rt_spi_flash_device_t spi_flash_dev);
/**
* Find sfud flash device
*
* @param spi_dev_name using SPI device name
*
* @return sfud flash device if success, otherwise return RT_NULL
*/
sfud_flash_t rt_sfud_flash_find(const char *spi_dev_name);
#endif /* _SPI_FLASH_SFUD_H_ */

127
components/net/at/at_socket/at_socket.c
View File

@ -36,10 +36,9 @@
#ifdef DBG_SECTION_NAME
#undef DBG_SECTION_NAME
#define DBG_SECTION_NAME "[AT_SOC] "
#define DBG_SECTION_NAME "AT_SOC"
#endif
#define HTONS_PORT(x) ((((x) & 0x00ffUL) << 8) | (((x) & 0xff00UL) >> 8))
#define NIPQUAD(addr) \
((unsigned char *)&addr)[0], \
@ -64,8 +63,6 @@ typedef enum {
/* the global array of available sockets */
static struct at_socket sockets[AT_SOCKETS_NUM] = { 0 };
/* the global AT socket lock */
static rt_mutex_t at_socket_lock = RT_NULL;
/* AT device socket options */
static struct at_device_ops *at_dev_ops = RT_NULL;
@ -91,7 +88,7 @@ static size_t at_recvpkt_put(rt_slist_t *rlist, const char *ptr, size_t length)
at_recv_pkt_t pkt;
pkt = (at_recv_pkt_t) rt_calloc(1, sizeof(struct at_recv_pkt));
if (!pkt)
if (pkt == RT_NULL)
{
LOG_E("No memory for receive packet table!");
return 0;
@ -257,12 +254,23 @@ static void at_do_event_changes(struct at_socket *sock, at_event_t event, rt_boo
static struct at_socket *alloc_socket(void)
{
char sem_name[RT_NAME_MAX];
char lock_name[RT_NAME_MAX];
static rt_mutex_t at_slock = RT_NULL;
char name[RT_NAME_MAX];
struct at_socket *sock;
int idx;
rt_mutex_take(at_socket_lock, RT_WAITING_FOREVER);
if(at_slock == RT_NULL)
{
/* create AT socket lock */
at_slock = rt_mutex_create("at_s", RT_IPC_FLAG_FIFO);
if (at_slock == RT_NULL)
{
LOG_E("No memory for AT socket lock!");
return RT_NULL;
}
}
rt_mutex_take(at_slock, RT_WAITING_FOREVER);
/* find an empty at socket entry */
for (idx = 0; idx < AT_SOCKETS_NUM && sockets[idx].magic; idx++);
@ -282,25 +290,25 @@ static struct at_socket *alloc_socket(void)
sock->errevent = RT_NULL;
rt_slist_init(&sock->recvpkt_list);
rt_snprintf(sem_name, RT_NAME_MAX, "%s%d", "at_recv_notice_", idx);
rt_snprintf(name, RT_NAME_MAX, "%s%d", "at_sr", idx);
/* create AT socket receive mailbox */
if ((sock->recv_notice = rt_sem_create(sem_name, 0, RT_IPC_FLAG_FIFO)) == RT_NULL)
if ((sock->recv_notice = rt_sem_create(name, 0, RT_IPC_FLAG_FIFO)) == RT_NULL)
{
goto __err;
}
rt_snprintf(lock_name, RT_NAME_MAX, "%s%d", "at_recv_lock_", idx);
rt_snprintf(name, RT_NAME_MAX, "%s%d", "at_sr", idx);
/* create AT socket receive ring buffer lock */
if((sock->recv_lock = rt_mutex_create(lock_name, RT_IPC_FLAG_FIFO)) == RT_NULL)
if((sock->recv_lock = rt_mutex_create(name, RT_IPC_FLAG_FIFO)) == RT_NULL)
{
goto __err;
}
rt_mutex_release(at_socket_lock);
rt_mutex_release(at_slock);
return sock;
__err:
rt_mutex_release(at_socket_lock);
rt_mutex_release(at_slock);
return RT_NULL;
}
@ -331,7 +339,7 @@ int at_socket(int domain, int type, int protocol)
/* allocate and initialize a new AT socket */
sock = alloc_socket();
if(!sock)
if(sock == RT_NULL)
{
LOG_E("Allocate a new AT socket failed!");
return RT_NULL;
@ -372,14 +380,16 @@ int at_closesocket(int socket)
struct at_socket *sock;
enum at_socket_state last_state;
if (!at_dev_ops)
if (at_dev_ops == RT_NULL)
{
LOG_E("Please register AT device socket options first!");
return -1;
}
if ((sock = at_get_socket(socket)) == RT_NULL)
sock = at_get_socket(socket);
if (sock == RT_NULL)
{
return -1;
}
last_state = sock->state;
@ -401,14 +411,16 @@ int at_shutdown(int socket, int how)
{
struct at_socket *sock;
if (!at_dev_ops)
if (at_dev_ops == RT_NULL)
{
LOG_E("Please register AT device socket options first!");
return -1;
}
if ((sock = at_get_socket(socket)) == RT_NULL)
sock = at_get_socket(socket);
if (sock == RT_NULL)
{
return -1;
}
if (sock->state == AT_SOCKET_CONNECT)
{
@ -425,7 +437,9 @@ int at_bind(int socket, const struct sockaddr *name, socklen_t namelen)
{
if (at_get_socket(socket) == RT_NULL)
{
return -1;
}
return 0;
}
@ -461,7 +475,8 @@ static void at_recv_notice_cb(int socket, at_socket_evt_t event, const char *buf
RT_ASSERT(bfsz);
RT_ASSERT(event == AT_SOCKET_EVT_RECV);
if ((sock = at_get_socket(socket)) == RT_NULL)
sock = at_get_socket(socket);
if (sock == RT_NULL)
return ;
/* put receive buffer to receiver packet list */
@ -486,7 +501,6 @@ static void at_closed_notice_cb(int socket, at_socket_evt_t event, const char *b
at_do_event_changes(sock, AT_EVENT_RECV, RT_TRUE);
at_do_event_changes(sock, AT_EVENT_ERROR, RT_TRUE);
// LOG_D("socket (%d) closed by remote");
sock->state = AT_SOCKET_CLOSED;
rt_sem_release(sock->recv_notice);
}
@ -498,14 +512,13 @@ int at_connect(int socket, const struct sockaddr *name, socklen_t namelen)
char ipstr[16] = { 0 };
int result = 0;
if (!at_dev_ops)
if (at_dev_ops == RT_NULL)
{
LOG_E("Please register AT device socket options first!");
return -1;
}
sock = at_get_socket(socket);
if (!sock)
if (sock == RT_NULL)
{
result = -1;
goto __exit;
@ -552,21 +565,19 @@ int at_recvfrom(int socket, void *mem, size_t len, int flags, struct sockaddr *f
int result = 0;
size_t recv_len = 0;
if (!mem || len == 0)
if (mem == RT_NULL || len == 0)
{
LOG_E("AT recvfrom input data or length error!");
result = -1;
goto __exit;
return -1;
}
if (!at_dev_ops)
if (at_dev_ops == RT_NULL)
{
LOG_E("Please register AT device socket options first!");
return -1;
}
sock = at_get_socket(socket);
if (!sock)
if (sock == RT_NULL)
{
result = -1;
goto __exit;
@ -678,14 +689,13 @@ int at_sendto(int socket, const void *data, size_t size, int flags, const struct
struct at_socket *sock;
int len, result = 0;
if (!at_dev_ops)
if (at_dev_ops == RT_NULL)
{
LOG_E("Please register AT device socket options first!");
result = -1;
goto __exit;
}
if (!data || size == 0)
if (data == RT_NULL || size == 0)
{
LOG_E("AT sendto input data or size error!");
result = -1;
@ -693,7 +703,7 @@ int at_sendto(int socket, const void *data, size_t size, int flags, const struct
}
sock = at_get_socket(socket);
if (!sock)
if (sock == RT_NULL)
{
result = -1;
goto __exit;
@ -767,20 +777,19 @@ int at_send(int socket, const void *data, size_t size, int flags)
return at_sendto(socket, data, size, flags, RT_NULL, 0);
}
int at_getsockopt(int socket, int level, int optname, void *optval, socklen_t *optlen)
{
struct at_socket *sock;
int32_t timeout;
if (!optval || !optlen)
if (optval == RT_NULL || optlen == RT_NULL)
{
LOG_E("AT getsocketopt input option value or option length error!");
return -1;
}
sock = at_get_socket(socket);
if (!sock)
if (sock == RT_NULL)
{
return -1;
}
@ -820,14 +829,14 @@ int at_setsockopt(int socket, int level, int optname, const void *optval, sockle
{
struct at_socket *sock;
if (!optval)
if (optval == RT_NULL)
{
LOG_E("AT setsockopt input option value error!");
return -1;
}
sock = at_get_socket(socket);
if (!sock)
if (sock == RT_NULL)
{
return -1;
}
@ -916,15 +925,14 @@ struct hostent *at_gethostbyname(const char *name)
static char s_hostname[DNS_MAX_NAME_LENGTH + 1];
size_t idx = 0;
if (!name)
if (name == RT_NULL)
{
LOG_E("AT gethostbyname input name error!");
return RT_NULL;
}
if (!at_dev_ops)
if (at_dev_ops == RT_NULL)
{
LOG_E("Please register AT device socket options first!");
return RT_NULL;
}
@ -976,12 +984,13 @@ int at_getaddrinfo(const char *nodename, const char *servname,
{
return EAI_FAIL;
}
if (!at_dev_ops)
*res = RT_NULL;
if (at_dev_ops == RT_NULL)
{
LOG_E("Please register AT device socket options first!");
return EAI_FAIL;
}
*res = RT_NULL;
if ((nodename == RT_NULL) && (servname == RT_NULL))
{
return EAI_NONAME;
@ -1078,10 +1087,10 @@ int at_getaddrinfo(const char *nodename, const char *servname,
struct sockaddr_in *sa4 = (struct sockaddr_in *) sa;
/* set up sockaddr */
sa4->sin_addr.s_addr = addr.u_addr.ip4.addr;
sa4->sin_family = AF_AT;
sa4->sin_family = AF_INET;
sa4->sin_len = sizeof(struct sockaddr_in);
sa4->sin_port = htons((u16_t )port_nr);
ai->ai_family = AF_AT;
ai->ai_family = AF_INET;
/* set up addrinfo */
if (hints != RT_NULL)
@ -1107,9 +1116,13 @@ int at_getaddrinfo(const char *nodename, const char *servname,
void at_freeaddrinfo(struct addrinfo *ai)
{
if (ai != RT_NULL)
struct addrinfo *next;
while (ai != NULL)
{
next = ai->ai_next;
rt_free(ai);
ai = next;
}
}
@ -1123,17 +1136,3 @@ void at_scoket_device_register(const struct at_device_ops *ops)
RT_ASSERT(ops->set_event_cb);
at_dev_ops = (struct at_device_ops *) ops;
}
static int at_socket_init(void)
{
/* create AT socket lock */
at_socket_lock = rt_mutex_create("at_socket_lock", RT_IPC_FLAG_FIFO);
if (!at_socket_lock)
{
LOG_E("No memory for AT socket lock!");
return -RT_ENOMEM;
}
return RT_EOK;
}
INIT_COMPONENT_EXPORT(at_socket_init);

10
components/net/at/at_socket/at_socket.h
View File

@ -32,6 +32,10 @@
#include <netdb.h>
#include <sys/socket.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef AT_SOCKET_RECV_BFSZ
#define AT_SOCKET_RECV_BFSZ 512
#endif
@ -144,7 +148,7 @@ void at_scoket_device_register(const struct at_device_ops *ops);
#ifndef RT_USING_SAL
#define socket(domain, type, protocol) at_socket(domain, type, protocol)
#define closescoket(socket) at_closesocket(socket)
#define closesocket(socket) at_closesocket(socket)
#define shutdown(socket, how) at_shutdown(socket, how)
#define bind(socket, name, namelen) at_bind(socket, name, namelen)
#define connect(socket, name, namelen) at_connect(socket, name, namelen)
@ -160,4 +164,8 @@ void at_scoket_device_register(const struct at_device_ops *ops);
#endif /* RT_USING_SAL */
#ifdef __cplusplus
}
#endif
#endif /* AT_SOCKET_H__ */

10
components/net/at/include/at.h
View File

@ -27,7 +27,10 @@
#include <rtthread.h>
#define AT_SW_VERSION "0.2.4"
#ifdef __cplusplus
extern "C" {
#endif
#define AT_SW_VERSION "0.3.0"
#define DBG_ENABLE
#define DBG_SECTION_NAME "AT"
@ -251,9 +254,8 @@ void at_port_reset(void);
void at_port_factory_reset(void);
#endif
#ifdef AT_USING_CLIENT
/* AT client port initialization */
int at_client_port_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __AT_H__ */

13
components/net/at/src/at_cli.c
View File

@ -100,9 +100,6 @@ void at_cli_deinit(void)
rt_base_t int_lvl;
rt_device_t console;
rt_sem_detach(&console_rx_notice);
rt_ringbuffer_destroy(console_rx_fifo);
int_lvl = rt_hw_interrupt_disable();
console = rt_console_get_device();
if (console && odev_rx_ind)
@ -111,6 +108,9 @@ void at_cli_deinit(void)
rt_device_set_rx_indicate(console, odev_rx_ind);
}
rt_hw_interrupt_enable(int_lvl);
rt_sem_detach(&console_rx_notice);
rt_ringbuffer_destroy(console_rx_fifo);
}
#ifdef AT_USING_SERVER
@ -272,15 +272,16 @@ static void client_cli_parser(void)
}
}
rt_thread_delete(at_client);
rt_sem_detach(&client_rx_notice);
rt_ringbuffer_destroy(client_rx_fifo);
/* restore client device RX indicate */
{
int_lvl = rt_hw_interrupt_disable();
rt_device_set_rx_indicate(client->device, client_odev_rx_ind);
rt_hw_interrupt_enable(int_lvl);
}
rt_thread_delete(at_client);
rt_sem_detach(&client_rx_notice);
rt_ringbuffer_destroy(client_rx_fifo);
}
else
{

26
components/net/at/src/at_client.c
View File

@ -663,6 +663,13 @@ void at_set_urc_table(const struct at_urc *table, rt_size_t size)
}
/**
* initialize AT client.
*
* @return 0: initialize success
* -1: initialize failed
* -5: no memory
*/
int at_client_init(void)
{
int result = RT_EOK;
@ -747,11 +754,6 @@ int at_client_init(void)
goto __exit;
}
if ((result = at_client_port_init()) != RT_EOK)
{
LOG_E("AT client port initialize failed(%d).", result);
}
__exit:
if (!result)
{
@ -773,14 +775,8 @@ __exit:
return result;
}
INIT_COMPONENT_EXPORT(at_client_init);
RT_WEAK int at_client_port_init(void)
{
at_client_local->urc_table = RT_NULL;
at_client_local->urc_table_size = 0;
LOG_E("The client porting initialize for AT client is not implement.");
return 0;
}
#ifdef FINSH_USING_MSH
#include <finsh.h>
MSH_CMD_EXPORT(at_client_init, initialize AT client);
#endif

3
components/net/sal_socket/SConscript
View File

@ -17,6 +17,9 @@ if GetDepend('SAL_USING_LWIP'):
if GetDepend('SAL_USING_AT'):
src += Glob('impl/af_inet_at.c')
if GetDepend('SAL_USING_LWIP') or GetDepend('SAL_USING_AT'):
CPPPATH += [cwd + '/impl']
if GetDepend('SAL_USING_POSIX'):
src += Glob('dfs_net/*.c')

48
components/net/sal_socket/impl/af_inet.h Normal file
View File

@ -0,0 +1,48 @@
/*
* File : af_inet.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2018-08-25 ChenYong First version
*/
#ifndef __AF_INET_H__
#define __AF_INET_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef SAL_USING_LWIP
/* lwIP protocol family register */
int lwip_inet_init(void);
#endif
#ifdef SAL_USING_AT
/* AT protocol family register */
int at_inet_init(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* __AF_INET_H__ */

2
components/net/sal_socket/impl/af_inet_at.c
View File

@ -26,6 +26,7 @@
#include <sal.h>
#include <at_socket.h>
#include <af_inet.h>
#ifdef SAL_USING_POSIX
#include <dfs_poll.h>
@ -107,6 +108,7 @@ static int at_create(struct sal_socket *socket, int type, int protocol)
}
static const struct proto_family at_inet_family_ops = {
"at",
AF_AT,
AF_INET,
at_create,

2
components/net/sal_socket/impl/af_inet_lwip.c
View File

@ -34,6 +34,7 @@
#endif
#include <sal.h>
#include <af_inet.h>
#if LWIP_VERSION < 0x2000000
#define SELWAIT_T int
@ -284,6 +285,7 @@ static int inet_create(struct sal_socket *socket, int type, int protocol)
}
static const struct proto_family lwip_inet_family_ops = {
"lwip",
AF_INET,
AF_INET,
inet_create,

4
components/net/sal_socket/include/dfs_net/dfs_net.h
View File

@ -26,12 +26,12 @@
#ifndef DFS_NET_H__
#define DFS_NET_H__
#include <dfs_file.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <dfs_file.h>
const struct dfs_file_ops* dfs_net_get_fops(void);
int dfs_net_getsocket(int fd);

21
components/net/sal_socket/include/sal.h
View File

@ -28,6 +28,10 @@
#include <dfs_file.h>
#include <rtdevice.h>
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(socklen_t) && !defined(SOCKLEN_T_DEFINED)
typedef uint32_t socklen_t;
#endif
@ -82,8 +86,9 @@ struct sal_socket
struct proto_family
{
int family; /* primary protocol families type*/
int sec_family; /* secondary protocol families type*/
char name[RT_NAME_MAX];
int family; /* primary protocol families type */
int sec_family; /* secondary protocol families type */
int (*create)(struct sal_socket *sal_socket, int type, int protocol); /* register socket options */
struct hostent* (*gethostbyname) (const char *name);
@ -92,10 +97,18 @@ struct proto_family
int (*getaddrinfo) (const char *nodename, const char *servname, const struct addrinfo *hints, struct addrinfo **res);
};
/* SAL socket initialization */
/* SAL(Socket Abstraction Layer) initialize */
int sal_init(void);
int sal_proto_family_register(const struct proto_family *pf);
struct sal_socket *sal_get_socket(int sock);
/* protocol family register and unregister operate */
int sal_proto_family_register(const struct proto_family *pf);
int sal_proto_family_unregister(const struct proto_family *pf);
struct proto_family *sal_proto_family_find(const char *name);
#ifdef __cplusplus
}
#endif
#endif /* SAL_H__ */

4
components/net/sal_socket/include/sal_ipaddr.h
View File

@ -26,6 +26,10 @@
#include "sal_type.h"
#ifdef __cplusplus
extern "C" {
#endif
/** IPv4 only: set the IP address given as an u32_t */
#define ip4_addr_set_u32(dest_ipaddr, src_u32) ((dest_ipaddr)->addr = (src_u32))
/** IPv4 only: get the IP address as an u32_t */

8
components/net/sal_socket/include/sal_netdb.h
View File

@ -26,6 +26,10 @@
#include <sal_socket.h>
#ifdef __cplusplus
extern "C" {
#endif
#define EAI_NONAME 200
#define EAI_SERVICE 201
#define EAI_FAIL 202
@ -88,4 +92,8 @@ int sal_getaddrinfo(const char *nodename,
const struct addrinfo *hints,
struct addrinfo **res);
#ifdef __cplusplus
}
#endif
#endif /* SAL_NETDB_H__ */

8
components/net/sal_socket/include/sal_socket.h
View File

@ -27,6 +27,10 @@
#include "sal_ipaddr.h"
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(socklen_t) && !defined(SOCKLEN_T_DEFINED)
typedef uint32_t socklen_t;
#endif
@ -175,4 +179,8 @@ int sal_socket(int domain, int type, int protocol);
int sal_closesocket(int socket);
int sal_ioctlsocket(int socket, long cmd, void *arg);
#ifdef __cplusplus
}
#endif
#endif /* SAL_SOCKET_H__ */

8
components/net/sal_socket/include/sal_type.h
View File

@ -28,6 +28,10 @@
#include <stdlib.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef int8_t err_t;
typedef uint8_t u8_t;
typedef int8_t s8_t;
@ -37,4 +41,8 @@ typedef uint32_t u32_t;
typedef int32_t s32_t;
typedef uintptr_t mem_ptr_t;
#ifdef __cplusplus
}
#endif
#endif /* SAL_TYPE_H__ */

1
components/net/sal_socket/socket/net_netdb.c
View File

@ -38,6 +38,7 @@ int gethostbyname_r(const char *name, struct hostent *ret, char *buf,
{
return sal_gethostbyname_r(name, ret, buf, buflen, result, h_errnop);
}
RTM_EXPORT(gethostbyname_r);
void freeaddrinfo(struct addrinfo *ai)
{

127
components/net/sal_socket/src/sal_socket.c
View File

@ -50,7 +50,7 @@ static struct rt_mutex sal_core_lock;
static rt_bool_t init_ok = RT_FALSE;
/**
* SAL (Socket Abstraction Layer) initialization.
* SAL (Socket Abstraction Layer) initialize.
*
* @return result
* >= 0: initialize success
@ -64,7 +64,7 @@ int sal_init(void)
}
/* clean sal socket table */
memset(&socket_table, 0, sizeof(socket_table));
rt_memset(&socket_table, 0, sizeof(socket_table));
/* create sal socket lock */
rt_mutex_init(&sal_core_lock, "sal_lock", RT_IPC_FLAG_FIFO);
@ -76,12 +76,12 @@ int sal_init(void)
INIT_COMPONENT_EXPORT(sal_init);
/**
* this function will register the current protocol family to the global array of protocol families.
* This function will register protocol family to the global array of protocol families.
*
* @param pf protocol families structure
* @param pf protocol family object
*
* @return 0 : protocol families structure index
* -1 : the global array of available protocol families is full
* @return >=0 : protocol family object index
* -1 : the global array of available protocol families is full
*/
int sal_proto_family_register(const struct proto_family *pf)
{
@ -91,6 +91,18 @@ int sal_proto_family_register(const struct proto_family *pf)
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* check protocol family is already registered */
for(idx = 0; idx < SAL_PROTO_FAMILIES_NUM; idx++)
{
if(rt_strcmp(proto_families[idx].name, pf->name) == 0)
{
/* enable interrupt */
rt_hw_interrupt_enable(level);
LOG_E("%s protocol family is already registered!", pf->name);
return -1;
}
}
/* find an empty protocol family entry */
for(idx = 0; idx < SAL_PROTO_FAMILIES_NUM && proto_families[idx].create; idx++);
@ -99,10 +111,10 @@ int sal_proto_family_register(const struct proto_family *pf)
{
/* enable interrupt */
rt_hw_interrupt_enable(level);
return -1;
}
rt_strncpy(proto_families[idx].name, pf->name, rt_strlen(pf->name));
proto_families[idx].family = pf->family;
proto_families[idx].sec_family = pf->sec_family;
proto_families[idx].create = pf->create;
@ -119,11 +131,62 @@ int sal_proto_family_register(const struct proto_family *pf)
}
/**
* this function will get socket structure by sal socket descriptor
* This function removes a previously registered protocol family object.
*
* @param pf protocol family object
*
* @return >=0 : unregister protocol family index
* -1 : unregister failed
*/
int sal_proto_family_unregister(const struct proto_family *pf)
{
int idx = 0;
RT_ASSERT(pf != RT_NULL);
for(idx = 0; idx < SAL_PROTO_FAMILIES_NUM; idx++)
{
if(rt_strcmp(proto_families[idx].name, pf->name) == 0)
{
rt_memset(&proto_families[idx], 0x00, sizeof(struct proto_family));
return idx;
}
}
return -1;
}
/**
* This function will get protocol family by name.
*
* @param name protocol family name
*
* @return protocol family object
*/
struct proto_family *sal_proto_family_find(const char *name)
{
int idx = 0;
RT_ASSERT(name != RT_NULL);
for (idx = 0; idx < SAL_PROTO_FAMILIES_NUM; idx++)
{
if (rt_strcmp(proto_families[idx].name, name) == 0)
{
return &proto_families[idx];
}
}
return RT_NULL;
}
/**
* This function will get sal socket object by sal socket descriptor.
*
* @param socket sal socket index
*
* @return socket structure of the current sal socket index
* @return sal socket object of the current sal socket index
*/
struct sal_socket *sal_get_socket(int socket)
{
@ -145,7 +208,7 @@ struct sal_socket *sal_get_socket(int socket)
}
/**
* this function will lock sal socket.
* This function will lock sal socket.
*
* @note please don't invoke it on ISR.
*/
@ -161,7 +224,7 @@ static void sal_lock(void)
}
/**
* this function will lock sal socket.
* This function will lock sal socket.
*
* @note please don't invoke it on ISR.
*/
@ -171,7 +234,7 @@ static void sal_unlock(void)
}
/**
* this function will get protocol family structure by family type
* This function will get protocol family structure by family type
*
* @param family protocol family
*
@ -201,17 +264,17 @@ static struct proto_family *get_proto_family(int family)
}
/**
* this function will initialize socket structure and set socket options
* This function will initialize sal socket object and set socket options
*
* @param family protocol family
* @param type socket type
* @param protocol transfer Protocol
* @param res socket structure address
* @param res sal socket object address
*
* @return 0 : socket initialize success
* -1 : input the wrong family
* -2 : input the wrong socket type
* -3 : get protocol family structure failed
* -3 : get protocol family object failed
* -4 : set socket options failed
*/
static int socket_init(int family, int type, int protocol, struct sal_socket **res)
@ -234,7 +297,7 @@ static int socket_init(int family, int type, int protocol, struct sal_socket **r
sock->type = type;
sock->protocol = protocol;
/* get socket protocol family structure */
/* get socket protocol family object */
if ((pf = get_proto_family(family)) == RT_NULL)
{
return -3;
@ -301,11 +364,6 @@ __result:
}
/**
* this function will return a empty sal socket structure address
*
* @return sal socket structure address
*/
static int socket_new(void)
{
struct sal_socket *sock;
@ -415,7 +473,7 @@ int sal_shutdown(int socket, int how)
if (sock->ops->shutdown((int) sock->user_data, how) == 0)
{
memset(sock, 0x00, sizeof(struct sal_socket));
rt_memset(sock, 0x00, sizeof(struct sal_socket));
return 0;
}
@ -622,7 +680,7 @@ int sal_closesocket(int socket)
if (sock->ops->closesocket((int) sock->user_data) == 0)
{
memset(sock, 0x00, sizeof(struct sal_socket));
rt_memset(sock, 0x00, sizeof(struct sal_socket));
return 0;
}
@ -669,12 +727,17 @@ int sal_poll(struct dfs_fd *file, struct rt_pollreq *req)
struct hostent *sal_gethostbyname(const char *name)
{
int i;
struct hostent *hst;
for (i = 0; i < SAL_PROTO_FAMILIES_NUM; ++i)
{
if (proto_families[i].gethostbyname)
{
return proto_families[i].gethostbyname(name);
hst = proto_families[i].gethostbyname(name);
if (hst != RT_NULL)
{
return hst;
}
}
}
@ -684,13 +747,17 @@ struct hostent *sal_gethostbyname(const char *name)
int sal_gethostbyname_r(const char *name, struct hostent *ret, char *buf,
size_t buflen, struct hostent **result, int *h_errnop)
{
int i;
int i, res;
for (i = 0; i < SAL_PROTO_FAMILIES_NUM; ++i)
{
if (proto_families[i].gethostbyname_r)
{
return proto_families[i].gethostbyname_r(name, ret, buf, buflen, result, h_errnop);
res = proto_families[i].gethostbyname_r(name, ret, buf, buflen, result, h_errnop);
if (res == 0)
{
return res;
}
}
}
@ -716,13 +783,17 @@ int sal_getaddrinfo(const char *nodename,
const struct addrinfo *hints,
struct addrinfo **res)
{
int i;
int i, ret;
for (i = 0; i < SAL_PROTO_FAMILIES_NUM; ++i)
{
if (proto_families[i].getaddrinfo)
{
return proto_families[i].getaddrinfo(nodename, servname, hints, res);
ret = proto_families[i].getaddrinfo(nodename, servname, hints, res);
if (ret == 0)
{
return ret;
}
}
}

4
components/utilities/ymodem/ymodem.c
View File

@ -72,7 +72,7 @@ static enum rym_code _rym_read_code(
{
/* Fast path */
if (rt_device_read(ctx->dev, 0, ctx->buf, 1) == 1)
return *ctx->buf;
return (enum rym_code)(*ctx->buf);
/* Slow path */
do {
@ -85,7 +85,7 @@ static enum rym_code _rym_read_code(
/* Try to read one */
rsz = rt_device_read(ctx->dev, 0, ctx->buf, 1);
if (rsz == 1)
return *ctx->buf;
return (enum rym_code)(*ctx->buf);
} while (1);
}

6
src/timer.c
View File

@ -220,7 +220,7 @@ rt_err_t rt_timer_detach(rt_timer_t timer)
rt_object_detach((rt_object_t)timer);
return -RT_EOK;
return RT_EOK;
}
RTM_EXPORT(rt_timer_detach);
@ -283,7 +283,7 @@ rt_err_t rt_timer_delete(rt_timer_t timer)
rt_object_delete((rt_object_t)timer);
return -RT_EOK;
return RT_EOK;
}
RTM_EXPORT(rt_timer_delete);
#endif
@ -410,7 +410,7 @@ rt_err_t rt_timer_start(rt_timer_t timer)
}
#endif
return -RT_EOK;
return RT_EOK;
}
RTM_EXPORT(rt_timer_start);