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[Bsp][Tina]Fix uart bug

This commit is contained in:
ZYH 2018-02-19 15:31:28 +08:00
parent 40b580b223
commit ccf15490c9
1 changed files with 3 additions and 0 deletions
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3
bsp/allwinner_tina/drivers/drv_uart.c
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@ -184,16 +184,19 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
if ((rt_uint32_t)(uart->hw_base) == UART0_BASE_ADDR) if ((rt_uint32_t)(uart->hw_base) == UART0_BASE_ADDR)
{ {
bus_gate_clk_enalbe(UART0_GATING); bus_gate_clk_enalbe(UART0_GATING);
bus_software_reset_disalbe(UART0_GATING);
bus_software_reset_enalbe(UART0_GATING); bus_software_reset_enalbe(UART0_GATING);
} }
else if ((rt_uint32_t)(uart->hw_base) == UART1_BASE_ADDR) else if ((rt_uint32_t)(uart->hw_base) == UART1_BASE_ADDR)
{ {
bus_gate_clk_enalbe(UART1_GATING); bus_gate_clk_enalbe(UART1_GATING);
bus_software_reset_disalbe(UART1_GATING);
bus_software_reset_enalbe(UART1_GATING); bus_software_reset_enalbe(UART1_GATING);
} }
else if ((rt_uint32_t)(uart->hw_base) == UART2_BASE_ADDR) else if ((rt_uint32_t)(uart->hw_base) == UART2_BASE_ADDR)
{ {
bus_gate_clk_enalbe(UART2_GATING); bus_gate_clk_enalbe(UART2_GATING);
bus_software_reset_disalbe(UART2_GATING);
bus_software_reset_enalbe(UART2_GATING); bus_software_reset_enalbe(UART2_GATING);
} }
else else