From c32093482ed2c73c2a230808af0083d8adb97a5c Mon Sep 17 00:00:00 2001 From: tanek liang Date: Mon, 11 Dec 2017 13:03:26 +0800 Subject: [PATCH] [bsp] clean code --- bsp/imxrt1052-evk/sdram_init.jlinkscript | 311 ----------------------- bsp/imxrt1052-evk/sdram_mpu_init.ini | 236 ----------------- bsp/imxrt1052-evk/sdram_mpu_init.mac | 249 ------------------ 3 files changed, 796 deletions(-) delete mode 100644 bsp/imxrt1052-evk/sdram_init.jlinkscript delete mode 100644 bsp/imxrt1052-evk/sdram_mpu_init.ini delete mode 100644 bsp/imxrt1052-evk/sdram_mpu_init.mac diff --git a/bsp/imxrt1052-evk/sdram_init.jlinkscript b/bsp/imxrt1052-evk/sdram_init.jlinkscript deleted file mode 100644 index b33ff301a..000000000 --- a/bsp/imxrt1052-evk/sdram_init.jlinkscript +++ /dev/null @@ -1,311 +0,0 @@ -/********************************************************************* -* SEGGER MICROCONTROLLER GmbH & Co. K.G. * -* Solutions for real time microcontroller applications * -********************************************************************** -* * -* (c) 2011-2015 SEGGER Microcontroller GmbH & Co. KG * -* * -* Internet: www.segger.com Support: support@segger.com * -* * -********************************************************************** ----------------------------------------------------------------------- -Purpose : ----------------------------END-OF-HEADER------------------------------ -*/ - -void Clock_Init() { - // Enable all clocks - MEM_WriteU32(0x400FC068,0xffffffff); - MEM_WriteU32(0x400FC06C,0xffffffff); - MEM_WriteU32(0x400FC070,0xffffffff); - MEM_WriteU32(0x400FC074,0xffffffff); - MEM_WriteU32(0x400FC078,0xffffffff); - MEM_WriteU32(0x400FC07C,0xffffffff); - MEM_WriteU32(0x400FC080,0xffffffff); - - MEM_WriteU32(0x400D8030,0x00002001); - MEM_WriteU32(0x400D8100,0x00100000); - MEM_WriteU32(0x400FC014,0x00050D40); - - Report("Clock Init Done"); -} - -void SDRAM_WaitIpCmdDone(void) -{ - unsigned int reg; - do - { - reg = MEM_ReadU32(0x402F003C); - }while((reg & 0x3) == 0); -} - -void SDRAM_Init() { - // Config IOMUX for SDRAM - MEM_WriteU32(0x401F8014,0x00000000); - MEM_WriteU32(0x401F8018,0x00000000); - MEM_WriteU32(0x401F801C,0x00000000); - MEM_WriteU32(0x401F8020,0x00000000); - MEM_WriteU32(0x401F8024,0x00000000); - MEM_WriteU32(0x401F8028,0x00000000); - MEM_WriteU32(0x401F802C,0x00000000); - MEM_WriteU32(0x401F8030,0x00000000); - MEM_WriteU32(0x401F8034,0x00000000); - MEM_WriteU32(0x401F8038,0x00000000); - MEM_WriteU32(0x401F803C,0x00000000); - MEM_WriteU32(0x401F8040,0x00000000); - MEM_WriteU32(0x401F8044,0x00000000); - MEM_WriteU32(0x401F8048,0x00000000); - MEM_WriteU32(0x401F804C,0x00000000); - MEM_WriteU32(0x401F8050,0x00000000); - MEM_WriteU32(0x401F8054,0x00000000); - MEM_WriteU32(0x401F8058,0x00000000); - MEM_WriteU32(0x401F805C,0x00000000); - MEM_WriteU32(0x401F8060,0x00000000); - MEM_WriteU32(0x401F8064,0x00000000); - MEM_WriteU32(0x401F8068,0x00000000); - MEM_WriteU32(0x401F806C,0x00000000); - MEM_WriteU32(0x401F8070,0x00000000); - MEM_WriteU32(0x401F8074,0x00000000); - MEM_WriteU32(0x401F8078,0x00000000); - MEM_WriteU32(0x401F807C,0x00000000); - MEM_WriteU32(0x401F8080,0x00000000); - MEM_WriteU32(0x401F8084,0x00000000); - MEM_WriteU32(0x401F8088,0x00000000); - MEM_WriteU32(0x401F808C,0x00000000); - MEM_WriteU32(0x401F8090,0x00000000); - MEM_WriteU32(0x401F8094,0x00000000); - MEM_WriteU32(0x401F8098,0x00000000); - MEM_WriteU32(0x401F809C,0x00000000); - MEM_WriteU32(0x401F80A0,0x00000000); - MEM_WriteU32(0x401F80A4,0x00000000); - MEM_WriteU32(0x401F80A8,0x00000000); - MEM_WriteU32(0x401F80AC,0x00000000); - MEM_WriteU32(0x401F80B0,0x00000000); - MEM_WriteU32(0x401F80B4,0x00000000); - MEM_WriteU32(0x401F80B8,0x00000000); - - // PAD ctrl - MEM_WriteU32(0x401F8204,0x000000F1); - MEM_WriteU32(0x401F8208,0x000000F1); - MEM_WriteU32(0x401F820C,0x000000F1); - MEM_WriteU32(0x401F8210,0x000000F1); - MEM_WriteU32(0x401F8214,0x000000F1); - MEM_WriteU32(0x401F8218,0x000000F1); - MEM_WriteU32(0x401F821C,0x000000F1); - MEM_WriteU32(0x401F8220,0x000000F1); - MEM_WriteU32(0x401F8224,0x000000F1); - MEM_WriteU32(0x401F8228,0x000000F1); - MEM_WriteU32(0x401F822C,0x000000F1); - MEM_WriteU32(0x401F8230,0x000000F1); - MEM_WriteU32(0x401F8234,0x000000F1); - MEM_WriteU32(0x401F8238,0x000000F1); - MEM_WriteU32(0x401F823C,0x000000F1); - MEM_WriteU32(0x401F8240,0x000000F1); - MEM_WriteU32(0x401F8244,0x000000F1); - MEM_WriteU32(0x401F8248,0x000000F1); - MEM_WriteU32(0x401F824C,0x000000F1); - MEM_WriteU32(0x401F8250,0x000000F1); - MEM_WriteU32(0x401F8254,0x000000F1); - MEM_WriteU32(0x401F8258,0x000000F1); - MEM_WriteU32(0x401F825C,0x000000F1); - MEM_WriteU32(0x401F8260,0x000000F1); - MEM_WriteU32(0x401F8264,0x000000F1); - MEM_WriteU32(0x401F8268,0x000000F1); - MEM_WriteU32(0x401F826C,0x000000F1); - MEM_WriteU32(0x401F8270,0x000000F1); - MEM_WriteU32(0x401F8274,0x000000F1); - MEM_WriteU32(0x401F8278,0x000000F1); - MEM_WriteU32(0x401F827C,0x000000F1); - MEM_WriteU32(0x401F8280,0x000000F1); - MEM_WriteU32(0x401F8284,0x000000F1); - MEM_WriteU32(0x401F8288,0x000000F1); - MEM_WriteU32(0x401F828C,0x000000F1); - MEM_WriteU32(0x401F8290,0x000000F1); - MEM_WriteU32(0x401F8294,0x000000F1); - MEM_WriteU32(0x401F8298,0x000000F1); - MEM_WriteU32(0x401F829C,0x000000F1); - MEM_WriteU32(0x401F82A0,0x000000F1); - MEM_WriteU32(0x401F82A4,0x000000F1); - MEM_WriteU32(0x401F82A8,0x000000F1); - - // Config SEMC - MEM_WriteU32(0x402F0000,0x1000E000); - MEM_WriteU32(0x402F0008,0x00030524); - MEM_WriteU32(0x402F000C,0x06030524); - MEM_WriteU32(0x402F0010,0x8000001B); - MEM_WriteU32(0x402F0014,0x90000021); - MEM_WriteU32(0x402F0004,0x00000008); - MEM_WriteU32(0x402F0040,0x00000B27); - MEM_WriteU32(0x402F0044,0x00100100); - MEM_WriteU32(0x402F0048,0x00020201); - MEM_WriteU32(0x402F004C,0x08193D0E); - MEM_WriteU32(0x402F0080,0x00000021); - MEM_WriteU32(0x402F0084,0x00888888); - MEM_WriteU32(0x402F0094,0x00000002); - MEM_WriteU32(0x402F0098,0x00000000); - - MEM_WriteU32(0x402F0090,0x80000000); - MEM_WriteU32(0x402F009C,0xA55A000F); - SDRAM_WaitIpCmdDone(); - MEM_WriteU32(0x402F0090,0x80000000); - MEM_WriteU32(0x402F009C,0xA55A000C); - SDRAM_WaitIpCmdDone(); - MEM_WriteU32(0x402F0090,0x80000000); - MEM_WriteU32(0x402F009C,0xA55A000C); - SDRAM_WaitIpCmdDone(); - MEM_WriteU32(0x402F00A0,0x00000022); - MEM_WriteU32(0x402F0090,0x80000000); - MEM_WriteU32(0x402F009C,0xA55A000A); - SDRAM_WaitIpCmdDone(); - - Report("SDRAM Init Done"); -} - -/* MPU configuration */ -void MPU_Init() -{ - unsigned int rbar0; - unsigned int rbar1; - unsigned int rbar2; - unsigned int rbar3; - unsigned int rbar4; - unsigned int rbar5; - unsigned int rbar6; - unsigned int rasr0; - unsigned int rasr1; - unsigned int rasr2; - unsigned int rasr3; - unsigned int rasr4; - unsigned int rasr5; - unsigned int rasr6; - unsigned int ctrl; - - rbar0 = ((0xC0000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (0 << 0)); - rbar1 = ((0x80000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (1 << 0)); - rbar2 = ((0x60000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (2 << 0)); - rbar3 = ((0x10000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (3 << 0)); - rbar4 = ((0x08000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (4 << 0)); - rbar5 = ((0x80000000 & ((0x7FFFFFF << 5))) | (1 << 4) | (5 << 0)); - rbar6 = ((0x81E00000 & ((0x7FFFFFF << 5))) | (1 << 4) | (6 << 0)); - - rasr0 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (28 << 1) | (1 << 0); - rasr1 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (29 << 1) | (1 << 0); - rasr2 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (28 << 1) | (1 << 0); - rasr3 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (27 << 1) | (1 << 0); - rasr4 = (0x3 << 24) | (2 << 19) | (0xC0 << 8) | (26 << 1) | (1 << 0); - rasr5 = (0x3 << 24) | (3 << 16) | (0xC0 << 8) | (25 << 1) | (1 << 0); - rasr6 = (0x3 << 24) | (1 << 19) | (0xC0 << 8) | (20 << 1) | (1 << 0); - - ctrl = (0x1 << 0) | (1 << 2); - - /* MPU_CTRL. */ - MEM_WriteU32(0xE000ED94, 0x0); - - /* MPU_RBAR. */ - MEM_WriteU32(0xE000ED9C, rbar6); - /* MPU_RASR. */ - MEM_WriteU32(0xE000EDA0, rasr6); - - /* MPU_RBAR. */ - MEM_WriteU32(0xE000ED9C, rbar5); - /* MPU_RASR. */ - MEM_WriteU32(0xE000EDA0, rasr5); - - /* MPU_RBAR. */ - MEM_WriteU32(0xE000ED9C, rbar4); - /* MPU_RASR. */ - MEM_WriteU32(0xE000EDA0, rasr4); - - /* MPU_RBAR. */ - MEM_WriteU32(0xE000ED9C, rbar3); - /* MPU_RASR. */ - MEM_WriteU32(0xE000EDA0, rasr3); - - /* MPU_RBAR. */ - MEM_WriteU32(0xE000ED9C, rbar2); - /* MPU_RASR. */ - MEM_WriteU32(0xE000EDA0, rasr2); - - /* MPU_RBAR. */ - MEM_WriteU32(0xE000ED9C, rbar1); - /* MPU_RASR. */ - MEM_WriteU32(0xE000EDA0, rasr1); - - /* MPU_RBAR. */ - MEM_WriteU32(0xE000ED9C, rbar0); - /* MPU_RASR. */ - MEM_WriteU32(0xE000EDA0, rasr0); - - /* MPU_CTRL. */ - MEM_WriteU32(0xE000ED94, ctrl); -} - -void flexram_init(void) -{ - Report("flexram init\n"); - MEM_WriteU32(0x400AC040, 0x80000000); //IOMUXC_GPR_GPR16 - - //MEM_WriteU32(0x400AC044, 0xFFFFAA55); //IOMUXC_GPR_GPR17: 256K ITCM, 128K DTCM, 128K OCRAM - MEM_WriteU32(0x400AC044, 0xFFFFFFFF); //IOMUXC_GPR_GPR17: 512K ITCM - - MEM_WriteU32(0x400AC038, 0x00890000); //IOMUXC_GPR_GPR14 - MEM_WriteU32(0x400AC040, 0x80000007); //IOMUXC_GPR_GPR16 -} - -/* ConfigTarget */ -void ConfigTargetSettings(void) -{ - Report("Config JTAG Speed to 4000kHz"); - JTAG_Speed = 4000; -} - -/* SetupTarget */ -void SetupTarget(void) { - - Report("Enabling i.MXRT SDRAM"); - Clock_Init(); - flexram_init(); - SDRAM_Init(); - MPU_Init(); -} - -/* ResetTarget */ -void ResetTarget(void) { - unsigned int v; - unsigned int Tmp; - // - // J-Link DLL expects CPU to be reset and halted when leaving this function - // - Report("J-Link script: ResetTarget()"); - //issue a software reset - //Tmp = MEM_ReadU32(0xE000ED0C); - //Tmp = (Tmp&0x0000ffff)|0x05fa0000|(1<<2); - //MEM_WriteU32(0xE000ED0C,Tmp); - //SYS_Sleep(10); - // Read IDCODE - v=JLINK_CORESIGHT_ReadDP(0); - Report1("DP0: ", v); - - // Power up Debugger - JLINK_CORESIGHT_WriteDP(1, 0x50000000); - v=JLINK_CORESIGHT_ReadDP(1); - Report1("DP1: ", v); - - - JLINK_CORESIGHT_WriteAP(0, 0x23000042); - v=JLINK_CORESIGHT_ReadAP(0); - Report1("AHB-AP0: ", v); - - JLINK_CORESIGHT_WriteAP(1, 0xE000EDF0); - v=JLINK_CORESIGHT_ReadAP(1); - Report1("AHB-AP1: ", v); - v=JLINK_CORESIGHT_ReadAP(3); - Report1("AHB-AP3: ", v); - JLINK_CORESIGHT_WriteAP(3, 0xa05f0003); - v=JLINK_CORESIGHT_ReadAP(3); - Report1("AHB-AP3: ", v); - - Clock_Init(); - SDRAM_Init(); - MPU_Init(); -} diff --git a/bsp/imxrt1052-evk/sdram_mpu_init.ini b/bsp/imxrt1052-evk/sdram_mpu_init.ini deleted file mode 100644 index 475bd7ada..000000000 --- a/bsp/imxrt1052-evk/sdram_mpu_init.ini +++ /dev/null @@ -1,236 +0,0 @@ -FUNC void SDRAM_WaitIpCmdDone(void) -{ - unsigned long reg; - do - { - reg = _RDWORD(0x402F003C); - }while((reg & 0x3) == 0); -} - -FUNC void _clock_init(void) -{ - // Enable all clocks - _WDWORD(0x400FC068, 0xffffffff); - _WDWORD(0x400FC06C, 0xffffffff); - _WDWORD(0x400FC070, 0xffffffff); - _WDWORD(0x400FC074, 0xffffffff); - _WDWORD(0x400FC078, 0xffffffff); - _WDWORD(0x400FC07C, 0xffffffff); - _WDWORD(0x400FC080, 0xffffffff); - - _WDWORD(0x400D8030, 0x00002001); - _WDWORD(0x400D8100, 0x00100000); - _WDWORD(0x400FC014, 0x00050D40); -} - -FUNC void _sdr_Init(void) -{ - // Config IOMUX - _WDWORD(0x401F8014, 0x00000000); - _WDWORD(0x401F8018, 0x00000000); - _WDWORD(0x401F801C, 0x00000000); - _WDWORD(0x401F8020, 0x00000000); - _WDWORD(0x401F8024, 0x00000000); - _WDWORD(0x401F8028, 0x00000000); - _WDWORD(0x401F802C, 0x00000000); - _WDWORD(0x401F8030, 0x00000000); - _WDWORD(0x401F8034, 0x00000000); - _WDWORD(0x401F8038, 0x00000000); - _WDWORD(0x401F803C, 0x00000000); - _WDWORD(0x401F8040, 0x00000000); - _WDWORD(0x401F8044, 0x00000000); - _WDWORD(0x401F8048, 0x00000000); - _WDWORD(0x401F804C, 0x00000000); - _WDWORD(0x401F8050, 0x00000000); - _WDWORD(0x401F8054, 0x00000000); - _WDWORD(0x401F8058, 0x00000000); - _WDWORD(0x401F805C, 0x00000000); - _WDWORD(0x401F8060, 0x00000000); - _WDWORD(0x401F8064, 0x00000000); - _WDWORD(0x401F8068, 0x00000000); - _WDWORD(0x401F806C, 0x00000000); - _WDWORD(0x401F8070, 0x00000000); - _WDWORD(0x401F8074, 0x00000000); - _WDWORD(0x401F8078, 0x00000000); - _WDWORD(0x401F807C, 0x00000000); - _WDWORD(0x401F8080, 0x00000000); - _WDWORD(0x401F8084, 0x00000000); - _WDWORD(0x401F8088, 0x00000000); - _WDWORD(0x401F808C, 0x00000000); - _WDWORD(0x401F8090, 0x00000000); - _WDWORD(0x401F8094, 0x00000000); - _WDWORD(0x401F8098, 0x00000000); - _WDWORD(0x401F809C, 0x00000000); - _WDWORD(0x401F80A0, 0x00000000); - _WDWORD(0x401F80A4, 0x00000000); - _WDWORD(0x401F80A8, 0x00000000); - _WDWORD(0x401F80AC, 0x00000000); - _WDWORD(0x401F80B0, 0x00000000); - _WDWORD(0x401F80B4, 0x00000000); - _WDWORD(0x401F80B8, 0x00000000); - - // PAD ctrl - _WDWORD(0x401F8204, 0x000000F1); - _WDWORD(0x401F8208, 0x000000F1); - _WDWORD(0x401F820C, 0x000000F1); - _WDWORD(0x401F8210, 0x000000F1); - _WDWORD(0x401F8214, 0x000000F1); - _WDWORD(0x401F8218, 0x000000F1); - _WDWORD(0x401F821C, 0x000000F1); - _WDWORD(0x401F8220, 0x000000F1); - _WDWORD(0x401F8224, 0x000000F1); - _WDWORD(0x401F8228, 0x000000F1); - _WDWORD(0x401F822C, 0x000000F1); - _WDWORD(0x401F8230, 0x000000F1); - _WDWORD(0x401F8234, 0x000000F1); - _WDWORD(0x401F8238, 0x000000F1); - _WDWORD(0x401F823C, 0x000000F1); - _WDWORD(0x401F8240, 0x000000F1); - _WDWORD(0x401F8244, 0x000000F1); - _WDWORD(0x401F8248, 0x000000F1); - _WDWORD(0x401F824C, 0x000000F1); - _WDWORD(0x401F8250, 0x000000F1); - _WDWORD(0x401F8254, 0x000000F1); - _WDWORD(0x401F8258, 0x000000F1); - _WDWORD(0x401F825C, 0x000000F1); - _WDWORD(0x401F8260, 0x000000F1); - _WDWORD(0x401F8264, 0x000000F1); - _WDWORD(0x401F8268, 0x000000F1); - _WDWORD(0x401F826C, 0x000000F1); - _WDWORD(0x401F8270, 0x000000F1); - _WDWORD(0x401F8274, 0x000000F1); - _WDWORD(0x401F8278, 0x000000F1); - _WDWORD(0x401F827C, 0x000000F1); - _WDWORD(0x401F8280, 0x000000F1); - _WDWORD(0x401F8284, 0x000000F1); - _WDWORD(0x401F8288, 0x000000F1); - _WDWORD(0x401F828C, 0x000000F1); - _WDWORD(0x401F8290, 0x000000F1); - _WDWORD(0x401F8294, 0x000000F1); - _WDWORD(0x401F8298, 0x000000F1); - _WDWORD(0x401F829C, 0x000000F1); - _WDWORD(0x401F82A0, 0x000000F1); - _WDWORD(0x401F82A4, 0x000000F1); - _WDWORD(0x401F82A8, 0x000000F1); - - _WDWORD(0x402F0000, 0x1000E000); - _WDWORD(0x402F0008, 0x00030524); - _WDWORD(0x402F000C, 0x06030524); - _WDWORD(0x402F0010, 0x8000001B); - _WDWORD(0x402F0014, 0x90000021); - _WDWORD(0x402F0004, 0x00000008); - _WDWORD(0x402F0040, 0x00000B27); - _WDWORD(0x402F0044, 0x00100100); - _WDWORD(0x402F0048, 0x00020201); - _WDWORD(0x402F004C, 0x08193D0E); - _WDWORD(0x402F0080, 0x00000021); - _WDWORD(0x402F0084, 0x00888888); - _WDWORD(0x402F0094, 0x00000002); - _WDWORD(0x402F0098, 0x00000000); - - _WDWORD(0x402F0090, 0x80000000); - _WDWORD(0x402F009C, 0xA55A000F); - SDRAM_WaitIpCmdDone(); - _WDWORD(0x402F0090, 0x80000000); - _WDWORD(0x402F009C, 0xA55A000C); - SDRAM_WaitIpCmdDone(); - _WDWORD(0x402F0090, 0x80000000); - _WDWORD(0x402F009C, 0xA55A000C); - SDRAM_WaitIpCmdDone(); - _WDWORD(0x402F00A0, 0x00000022); - _WDWORD(0x402F0090, 0x80000000); - _WDWORD(0x402F009C, 0xA55A000A); - SDRAM_WaitIpCmdDone(); -} - -FUNC void _mpu_Init() -{ - unsigned long rbar0, rbar1, rbar2, rbar3, rbar4, rbar5, rbar6; - unsigned long rasr0, rasr1, rasr2, rasr3, rasr4, rasr5, rasr6; - unsigned long ctrl; - - rbar0 = ((0xC0000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (0U << 0U)); - rbar1 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (1U << 0U)); - rbar2 = ((0x60000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (2U << 0U)); - rbar3 = ((0x10000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (3U << 0U)); - rbar4 = ((0x08000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (4U << 0U)); - rbar5 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (5U << 0U)); - rbar6 = ((0x81E00000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (6U << 0U)); - - rasr0 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U); - rasr1 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (29U << 1U) | (1U << 0U); - rasr2 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U); - rasr3 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (27U << 1U) | (1U << 0U); - rasr4 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (26U << 1U) | (1U << 0U); - rasr5 = (0x3U << 24U) | (3UL << 16U) | (0xC0U << 8U) | (25U << 1U) | (1U << 0U); - rasr6 = (0x3U << 24U) | (1UL << 19U) | (0xC0U << 8U) | (20U << 1U) | (1U << 0U); - - /* Enable Privileged default memory map and the MPU. */ - ctrl = (0x1U << 0) | (1U << 2U); - - /* MPU_CTRL. */ - _WDWORD(0xE000ED94, 0x0); - - /* MPU_RBAR. */ - _WDWORD(0xE000ED9C, rbar6); - /* MPU_RASR. */ - _WDWORD(0xE000EDA0, rasr6); - - /* MPU_RBAR. */ - _WDWORD(0xE000ED9C, rbar5); - /* MPU_RASR. */ - _WDWORD(0xE000EDA0, rasr5); - - _WDWORD(0xE000ED9C, rbar4); - /* MPU_RASR. */ - _WDWORD(0xE000EDA0, rasr4); - - _WDWORD(0xE000ED9C, rbar3); - /* MPU_RASR. */ - _WDWORD(0xE000EDA0, rasr3); - - /* MPU_RBAR. */ - _WDWORD(0xE000ED9C, rbar2); - /* MPU_RASR. */ - _WDWORD(0xE000EDA0, rasr2); - - _WDWORD(0xE000ED9C, rbar1); - /* MPU_RASR. */ - _WDWORD(0xE000EDA0, rasr1); - - _WDWORD(0xE000ED9C, rbar0); - /* MPU_RASR. */ - _WDWORD(0xE000EDA0, rasr0); - - /* MPU_CTRL. */ - _WDWORD(0xE000ED94, ctrl); -} - -FUNC void _flexram_init(void) -{ - _WDWORD(0x400AC040, 0x80000000); //IOMUXC_GPR_GPR16 - //_WDWORD(0x400AC044, 0xFFFFAA55); //IOMUXC_GPR_GPR17 - _WDWORD(0x400AC044, 0xFFFFFFFF); //IOMUXC_GPR_GPR17 - _WDWORD(0x400AC038, 0x00890000); //IOMUXC_GPR_GPR14 - _WDWORD(0x400AC040, 0x80000007); //IOMUXC_GPR_GPR16 -} - -FUNC void Setup (void) { - _clock_init(); - //_flexram_init(); - _sdr_Init(); - _mpu_Init(); - SP = _RDWORD(0x00000000); // Setup Stack Pointer - PC = _RDWORD(0x00000004); // Setup Program Counter - _WDWORD(0xE000ED08, 0x00000000); // Setup Vector Table Offset Register -} - -FUNC void OnResetExec (void) { // executes upon software RESET - Setup(); // Setup for Running -} - -LOAD %L INCREMENTAL // Download - -Setup(); // Setup for Running - -// g, main diff --git a/bsp/imxrt1052-evk/sdram_mpu_init.mac b/bsp/imxrt1052-evk/sdram_mpu_init.mac deleted file mode 100644 index 0e11122fc..000000000 --- a/bsp/imxrt1052-evk/sdram_mpu_init.mac +++ /dev/null @@ -1,249 +0,0 @@ -/*****************************************************************************/ - - -SDRAM_WaitIpCmdDone() -{ - __var reg; - do - { - reg = __readMemory32(0x402F003C, "Memory"); - }while((reg & 0x3) == 0); -} - -_clock_init() -{ - // Enable all clocks - __writeMemory32(0xffffffff, 0x400FC068, "Memory"); - __writeMemory32(0xffffffff, 0x400FC06C, "Memory"); - __writeMemory32(0xffffffff, 0x400FC070, "Memory"); - __writeMemory32(0xffffffff, 0x400FC074, "Memory"); - __writeMemory32(0xffffffff, 0x400FC078, "Memory"); - __writeMemory32(0xffffffff, 0x400FC07C, "Memory"); - __writeMemory32(0xffffffff, 0x400FC080, "Memory"); - - __writeMemory32(0x00002001, 0x400D8030, "Memory"); - __writeMemory32(0x00100000, 0x400D8100, "Memory"); - __writeMemory32(0x00050D40, 0x400FC014, "Memory"); -} - -_sdr_Init() -{ - // Config IOMUX - __writeMemory32(0x00000000, 0x401F8014, "Memory"); - __writeMemory32(0x00000000, 0x401F8018, "Memory"); - __writeMemory32(0x00000000, 0x401F801C, "Memory"); - __writeMemory32(0x00000000, 0x401F8020, "Memory"); - __writeMemory32(0x00000000, 0x401F8024, "Memory"); - __writeMemory32(0x00000000, 0x401F8028, "Memory"); - __writeMemory32(0x00000000, 0x401F802C, "Memory"); - __writeMemory32(0x00000000, 0x401F8030, "Memory"); - __writeMemory32(0x00000000, 0x401F8034, "Memory"); - __writeMemory32(0x00000000, 0x401F8038, "Memory"); - __writeMemory32(0x00000000, 0x401F803C, "Memory"); - __writeMemory32(0x00000000, 0x401F8040, "Memory"); - __writeMemory32(0x00000000, 0x401F8044, "Memory"); - __writeMemory32(0x00000000, 0x401F8048, "Memory"); - __writeMemory32(0x00000000, 0x401F804C, "Memory"); - __writeMemory32(0x00000000, 0x401F8050, "Memory"); - __writeMemory32(0x00000000, 0x401F8054, "Memory"); - __writeMemory32(0x00000000, 0x401F8058, "Memory"); - __writeMemory32(0x00000000, 0x401F805C, "Memory"); - __writeMemory32(0x00000000, 0x401F8060, "Memory"); - __writeMemory32(0x00000000, 0x401F8064, "Memory"); - __writeMemory32(0x00000000, 0x401F8068, "Memory"); - __writeMemory32(0x00000000, 0x401F806C, "Memory"); - __writeMemory32(0x00000000, 0x401F8070, "Memory"); - __writeMemory32(0x00000000, 0x401F8074, "Memory"); - __writeMemory32(0x00000000, 0x401F8078, "Memory"); - __writeMemory32(0x00000000, 0x401F807C, "Memory"); - __writeMemory32(0x00000000, 0x401F8080, "Memory"); - __writeMemory32(0x00000000, 0x401F8084, "Memory"); - __writeMemory32(0x00000000, 0x401F8088, "Memory"); - __writeMemory32(0x00000000, 0x401F808C, "Memory"); - __writeMemory32(0x00000000, 0x401F8090, "Memory"); - __writeMemory32(0x00000000, 0x401F8094, "Memory"); - __writeMemory32(0x00000000, 0x401F8098, "Memory"); - __writeMemory32(0x00000000, 0x401F809C, "Memory"); - __writeMemory32(0x00000000, 0x401F80A0, "Memory"); - __writeMemory32(0x00000000, 0x401F80A4, "Memory"); - __writeMemory32(0x00000000, 0x401F80A8, "Memory"); - __writeMemory32(0x00000000, 0x401F80AC, "Memory"); - __writeMemory32(0x00000000, 0x401F80B0, "Memory"); - __writeMemory32(0x00000000, 0x401F80B4, "Memory"); - __writeMemory32(0x00000000, 0x401F80B8, "Memory"); - - // PAD ctrl - __writeMemory32(0x000000F1, 0x401F8204, "Memory"); - __writeMemory32(0x000000F1, 0x401F8208, "Memory"); - __writeMemory32(0x000000F1, 0x401F820C, "Memory"); - __writeMemory32(0x000000F1, 0x401F8210, "Memory"); - __writeMemory32(0x000000F1, 0x401F8214, "Memory"); - __writeMemory32(0x000000F1, 0x401F8218, "Memory"); - __writeMemory32(0x000000F1, 0x401F821C, "Memory"); - __writeMemory32(0x000000F1, 0x401F8220, "Memory"); - __writeMemory32(0x000000F1, 0x401F8224, "Memory"); - __writeMemory32(0x000000F1, 0x401F8228, "Memory"); - __writeMemory32(0x000000F1, 0x401F822C, "Memory"); - __writeMemory32(0x000000F1, 0x401F8230, "Memory"); - __writeMemory32(0x000000F1, 0x401F8234, "Memory"); - __writeMemory32(0x000000F1, 0x401F8238, "Memory"); - __writeMemory32(0x000000F1, 0x401F823C, "Memory"); - __writeMemory32(0x000000F1, 0x401F8240, "Memory"); - __writeMemory32(0x000000F1, 0x401F8244, "Memory"); - __writeMemory32(0x000000F1, 0x401F8248, "Memory"); - __writeMemory32(0x000000F1, 0x401F824C, "Memory"); - __writeMemory32(0x000000F1, 0x401F8250, "Memory"); - __writeMemory32(0x000000F1, 0x401F8254, "Memory"); - __writeMemory32(0x000000F1, 0x401F8258, "Memory"); - __writeMemory32(0x000000F1, 0x401F825C, "Memory"); - __writeMemory32(0x000000F1, 0x401F8260, "Memory"); - __writeMemory32(0x000000F1, 0x401F8264, "Memory"); - __writeMemory32(0x000000F1, 0x401F8268, "Memory"); - __writeMemory32(0x000000F1, 0x401F826C, "Memory"); - __writeMemory32(0x000000F1, 0x401F8270, "Memory"); - __writeMemory32(0x000000F1, 0x401F8274, "Memory"); - __writeMemory32(0x000000F1, 0x401F8278, "Memory"); - __writeMemory32(0x000000F1, 0x401F827C, "Memory"); - __writeMemory32(0x000000F1, 0x401F8280, "Memory"); - __writeMemory32(0x000000F1, 0x401F8284, "Memory"); - __writeMemory32(0x000000F1, 0x401F8288, "Memory"); - __writeMemory32(0x000000F1, 0x401F828C, "Memory"); - __writeMemory32(0x000000F1, 0x401F8290, "Memory"); - __writeMemory32(0x000000F1, 0x401F8294, "Memory"); - __writeMemory32(0x000000F1, 0x401F8298, "Memory"); - __writeMemory32(0x000000F1, 0x401F829C, "Memory"); - __writeMemory32(0x000000F1, 0x401F82A0, "Memory"); - __writeMemory32(0x000000F1, 0x401F82A4, "Memory"); - __writeMemory32(0x000000F1, 0x401F82A8, "Memory"); - - __writeMemory32(0x1000E000, 0x402F0000, "Memory"); - __writeMemory32(0x00030524, 0x402F0008, "Memory"); - __writeMemory32(0x06030524, 0x402F000C, "Memory"); - __writeMemory32(0x8000001B, 0x402F0010, "Memory"); - __writeMemory32(0x90000021, 0x402F0014, "Memory"); - __writeMemory32(0x00000008, 0x402F0004, "Memory"); - __writeMemory32(0x00000B27, 0x402F0040, "Memory"); - __writeMemory32(0x00100100, 0x402F0044, "Memory"); - __writeMemory32(0x00020201, 0x402F0048, "Memory"); - __writeMemory32(0x08193D0E, 0x402F004C, "Memory"); - __writeMemory32(0x00000021, 0x402F0080, "Memory"); - __writeMemory32(0x00888888, 0x402F0084, "Memory"); - __writeMemory32(0x00000002, 0x402F0094, "Memory"); - __writeMemory32(0x00000000, 0x402F0098, "Memory"); - - __writeMemory32(0x80000000, 0x402F0090, "Memory"); - __writeMemory32(0xA55A000F, 0x402F009C, "Memory"); - SDRAM_WaitIpCmdDone(); - __writeMemory32(0x80000000, 0x402F0090, "Memory"); - __writeMemory32(0xA55A000C, 0x402F009C, "Memory"); - SDRAM_WaitIpCmdDone(); - __writeMemory32(0x80000000, 0x402F0090, "Memory"); - __writeMemory32(0xA55A000C, 0x402F009C, "Memory"); - SDRAM_WaitIpCmdDone(); - __writeMemory32(0x00000022, 0x402F00A0, "Memory"); - __writeMemory32(0x80000000, 0x402F0090, "Memory"); - __writeMemory32(0xA55A000A, 0x402F009C, "Memory"); - SDRAM_WaitIpCmdDone(); - __message "SDRAM init done\n"; -} - -_mpu_Init() -{ - __var rbar0, rbar1, rbar2, rbar3, rbar4, rbar5, rbar6; - rbar0 = ((0xC0000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (0U << 0U)); - rbar1 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (1U << 0U)); - rbar2 = ((0x60000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (2U << 0U)); - rbar3 = ((0x10000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (3U << 0U)); - rbar4 = ((0x08000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (4U << 0U)); - rbar5 = ((0x80000000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (5U << 0U)); - rbar6 = ((0x81E00000U & ((0x7FFFFFFUL << 5U))) | (1UL << 4U) | (6U << 0U)); - - __var rasr0, rasr1, rasr2, rasr3, rasr4, rasr5, rasr6; - rasr0 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U); - rasr1 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (29U << 1U) | (1U << 0U); - rasr2 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (28U << 1U) | (1U << 0U); - rasr3 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (27U << 1U) | (1U << 0U); - rasr4 = (0x3U << 24U) | (2UL << 19U) | (0xC0U << 8U) | (26U << 1U) | (1U << 0U); - rasr5 = (0x3U << 24U) | (3UL << 16U) | (0xC0U << 8U) | (25U << 1U) | (1U << 0U); - rasr6 = (0x3U << 24U) | (1UL << 19U) | (0xC0U << 8U) | (20U << 1U) | (1U << 0U); - - /* Enable Privileged default memory map and the MPU. */ - __var ctrl; - ctrl = (0x1U << 0) | (1U << 2U); - - /* MPU_CTRL. */ - __writeMemory32(0x0, 0xE000ED94, "Memory"); - - /* MPU_RBAR. */ - __writeMemory32(rbar6, 0xE000ED9C, "Memory"); - /* MPU_RASR. */ - __writeMemory32(rasr6, 0xE000EDA0, "Memory"); - - /* MPU_RBAR. */ - __writeMemory32(rbar5, 0xE000ED9C, "Memory"); - /* MPU_RASR. */ - __writeMemory32(rasr5, 0xE000EDA0, "Memory"); - - /* MPU_RBAR. */ - __writeMemory32(rbar4, 0xE000ED9C, "Memory"); - /* MPU_RASR. */ - __writeMemory32(rasr4, 0xE000EDA0, "Memory"); - - /* MPU_RBAR. */ - __writeMemory32(rbar3, 0xE000ED9C, "Memory"); - /* MPU_RASR. */ - __writeMemory32(rasr3, 0xE000EDA0, "Memory"); - - /* MPU_RBAR. */ - __writeMemory32(rbar2, 0xE000ED9C, "Memory"); - /* MPU_RASR. */ - __writeMemory32(rasr2, 0xE000EDA0, "Memory"); - - /* MPU_RBAR. */ - __writeMemory32(rbar1, 0xE000ED9C, "Memory"); - /* MPU_RASR. */ - __writeMemory32(rasr1, 0xE000EDA0, "Memory"); - - /* MPU_RBAR. */ - __writeMemory32(rbar0, 0xE000ED9C, "Memory"); - /* MPU_RASR. */ - __writeMemory32(rasr0, 0xE000EDA0, "Memory"); - - /* MPU_CTRL. */ - __writeMemory32(ctrl, 0xE000ED94, "Memory"); -} - -_flexram_init() -{ - __message "flexram init\n"; - __writeMemory32(0x80000000, 0x400AC040, "Memory"); //IOMUXC_GPR_GPR16 - //__writeMemory32(0xFFFFAA55, 0x400AC044, "Memory"); //IOMUXC_GPR_GPR17 - __writeMemory32(0xFFFFFFFF, 0x400AC044, "Memory"); //IOMUXC_GPR_GPR17 - __writeMemory32(0x00890000, 0x400AC038, "Memory"); //IOMUXC_GPR_GPR14 - __writeMemory32(0x80000007, 0x400AC040, "Memory"); //IOMUXC_GPR_GPR16 -} - -execUserPreload() -{ - __message "execUserPreload() start.\n"; - - _clock_init(); - _flexram_init(); - _sdr_Init(); - _mpu_Init(); - - __message "execUserPreload() done.\n"; -} - -execUserReset() -{ - __message "execUserReset() start.\n"; - - _clock_init(); - _flexram_init(); - _sdr_Init(); - _mpu_Init(); - - __message "execUserReset() done.\n"; -} -