From bdc8da55461b1f692d355fb09b4160beb1356b9c Mon Sep 17 00:00:00 2001 From: chinky Date: Tue, 14 Aug 2018 19:56:45 +0800 Subject: [PATCH] bsp stm32f030r8 --- bsp/stm32f030r8-nucleo/drivers/SConscript | 2 +- bsp/stm32f030r8-nucleo/drivers/board.h | 196 +---------- bsp/stm32f030r8-nucleo/drivers/gcc_startup.s | 104 ------ .../drivers/startup_stm32f030x8.s | 286 ++++++++++++++++ .../drivers/stm32f0xx_hal_conf.h | 324 ++++++++++++++++++ .../drivers/stm32f0xx_hal_msp.c | 197 +++++++++++ bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.c | 73 ++++ bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.h | 58 ++++ bsp/stm32f0x/.config | 245 +++++++++++++ bsp/stm32f0x/Kconfig | 58 ++++ bsp/stm32f0x/applications/application.c | 83 ----- bsp/stm32f0x/applications/main.c | 20 ++ bsp/stm32f0x/applications/startup.c | 112 ------ bsp/stm32f0x/rtconfig.h | 196 ++++++----- bsp/stm32f0x/ul.bat | 1 + 15 files changed, 1383 insertions(+), 572 deletions(-) delete mode 100644 bsp/stm32f030r8-nucleo/drivers/gcc_startup.s create mode 100644 bsp/stm32f030r8-nucleo/drivers/startup_stm32f030x8.s create mode 100644 bsp/stm32f030r8-nucleo/drivers/stm32f0xx_hal_conf.h create mode 100644 bsp/stm32f030r8-nucleo/drivers/stm32f0xx_hal_msp.c create mode 100644 bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.c create mode 100644 bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.h create mode 100644 bsp/stm32f0x/.config create mode 100644 bsp/stm32f0x/Kconfig delete mode 100644 bsp/stm32f0x/applications/application.c create mode 100644 bsp/stm32f0x/applications/main.c delete mode 100644 bsp/stm32f0x/applications/startup.c create mode 100644 bsp/stm32f0x/ul.bat diff --git a/bsp/stm32f030r8-nucleo/drivers/SConscript b/bsp/stm32f030r8-nucleo/drivers/SConscript index 3568c9a89..6d512a98a 100644 --- a/bsp/stm32f030r8-nucleo/drivers/SConscript +++ b/bsp/stm32f030r8-nucleo/drivers/SConscript @@ -22,7 +22,7 @@ if GetDepend(['RT_USING_SDCARD']): src += ['drv_sdcard.c'] if rtconfig.CROSS_TOOL == 'gcc': - src += ['gcc_startup.s'] + src += ['startup_stm32f030x8.s'] CPPPATH = [cwd] diff --git a/bsp/stm32f030r8-nucleo/drivers/board.h b/bsp/stm32f030r8-nucleo/drivers/board.h index 731dc67a4..070bceb91 100644 --- a/bsp/stm32f030r8-nucleo/drivers/board.h +++ b/bsp/stm32f030r8-nucleo/drivers/board.h @@ -11,199 +11,31 @@ * Date Author Notes * 2009-09-22 Bernard add board.h to this bsp * 2017-10-20 ZYH emmm...setup for HAL Libraries + * 2018-08-14 Chinky Support stm32f0xx */ // <<< Use Configuration Wizard in Context Menu >>> #ifndef __BOARD_H__ #define __BOARD_H__ -#include "stm32f1xx_hal.h" +#include "stm32f0xx_hal.h" /* board configuration */ -#if \ - defined(STM32F101TB)||\ - defined(STM32F103T8)||\ - defined(STM32F103TB) -#define STM32F10X_PIN_NUMBERS 36 -#elif \ - defined(STM32F101CB)||\ - defined(STM32F102CB)||\ - defined(STM32F103C8)||\ - defined(STM32F103CB) -#define STM32F10X_PIN_NUMBERS 48 -#elif \ - defined(STM32F100RC)||\ - defined(STM32F100RD)||\ - defined(STM32F100RE)||\ - defined(STM32F101RB)||\ - defined(STM32F101RC)||\ - defined(STM32F101RD)||\ - defined(STM32F101RE)||\ - defined(STM32F101RF)||\ - defined(STM32F101RG)||\ - defined(STM32F102RB)||\ - defined(STM32F103R8)||\ - defined(STM32F103RB)||\ - defined(STM32F103RC)||\ - defined(STM32F103RD)||\ - defined(STM32F103RE)||\ - defined(STM32F103RF)||\ - defined(STM32F103RG)||\ - defined(STM32F105R8)||\ - defined(STM32F105RB)||\ - defined(STM32F105RC)||\ - defined(STM32F107RB)||\ - defined(STM32F107RC) -#define STM32F10X_PIN_NUMBERS 64 -#elif \ - defined(STM32F100VC)||\ - defined(STM32F100VD)||\ - defined(STM32F100VE)||\ - defined(STM32F101VB)||\ - defined(STM32F101VC)||\ - defined(STM32F101VD)||\ - defined(STM32F101VE)||\ - defined(STM32F101VF)||\ - defined(STM32F101VG)||\ - defined(STM32F103V8)||\ - defined(STM32F103VB)||\ - defined(STM32F103VC)||\ - defined(STM32F103VD)||\ - defined(STM32F103VE)||\ - defined(STM32F103VF)||\ - defined(STM32F103VG)||\ - defined(STM32F105V8)||\ - defined(STM32F105VB)||\ - defined(STM32F105VC)||\ - defined(STM32F107VB)||\ - defined(STM32F107VC) -#define STM32F10X_PIN_NUMBERS 100 -#elif \ - defined(STM32F100ZC)||\ - defined(STM32F100ZD)||\ - defined(STM32F100ZE)||\ - defined(STM32F101ZC)||\ - defined(STM32F101ZD)||\ - defined(STM32F101ZE)||\ - defined(STM32F101ZF)||\ - defined(STM32F101ZG)||\ - defined(STM32F103ZC)||\ - defined(STM32F103ZD)||\ - defined(STM32F103ZE)||\ - defined(STM32F103ZF)||\ - defined(STM32F103ZG) -#define STM32F10X_PIN_NUMBERS 144 +#if defined(STM32F030RB) +#define STM32F0XX_PIN_NUMBERS 64 #endif -#if \ - defined(STM32F100RC)||\ - defined(STM32F100VC)||\ - defined(STM32F100ZC) -#define STM32_SRAM_SIZE 24 -//#define STM32F100xE -#elif \ - defined(STM32F100RD)||\ - defined(STM32F100RE)||\ - defined(STM32F100VD)||\ - defined(STM32F100VE)||\ - defined(STM32F100ZD)||\ - defined(STM32F100ZE) -#define STM32_SRAM_SIZE 32 -//#define STM32F100xE -#elif \ - defined(STM32F101TB)||\ - defined(STM32F101CB)||\ - defined(STM32F101RB)||\ - defined(STM32F101VB) -#define STM32_SRAM_SIZE 16 -//#define STM32F101xB -#elif \ - defined(STM32F101RC)||\ - defined(STM32F101VC)||\ - defined(STM32F101ZC) -#define STM32_SRAM_SIZE 32 -//#define STM32F101xE -#elif \ - defined(STM32F101RD)||\ - defined(STM32F101RE)||\ - defined(STM32F101VD)||\ - defined(STM32F101VE)||\ - defined(STM32F101ZD)||\ - defined(STM32F101ZE) -#define STM32_SRAM_SIZE 48 -//#define STM32F101xE -#elif \ - defined(STM32F101RF)||\ - defined(STM32F101RG)||\ - defined(STM32F101VF)||\ - defined(STM32F101VG)||\ - defined(STM32F101ZF)||\ - defined(STM32F101ZG) -#define STM32_SRAM_SIZE 80 -//#define STM32F101xG -#elif \ - defined(STM32F102CB)||\ - defined(STM32F102RB) -#define STM32_SRAM_SIZE 16 -//#define STM32F102xB -#elif \ - defined(STM32F103T8)||\ - defined(STM32F103TB)||\ - defined(STM32F103C8)||\ - defined(STM32F103CB)||\ - defined(STM32F103R8)||\ - defined(STM32F103RB)||\ - defined(STM32F103V8)||\ - defined(STM32F103VB) -#define STM32_SRAM_SIZE 20 -//#define STM32F103xB -#elif \ - defined(STM32F103RC)||\ - defined(STM32F103VC)||\ - defined(STM32F103ZC) -#define STM32_SRAM_SIZE 48 -//#define STM32F103xE -#elif \ - defined(STM32F103RD)||\ - defined(STM32F103RE)||\ - defined(STM32F103VD)||\ - defined(STM32F103VE)||\ - defined(STM32F103ZD)||\ - defined(STM32F103ZE) -#define STM32_SRAM_SIZE 64 -//#define STM32F103xE -#elif \ - defined(STM32F103RF)||\ - defined(STM32F103RG)||\ - defined(STM32F103VF)||\ - defined(STM32F103VG)||\ - defined(STM32F103ZF)||\ - defined(STM32F103ZG) -#define STM32_SRAM_SIZE 96 -//#define STM32F103xG -#elif \ - defined(STM32F105R8)||\ - defined(STM32F105RB)||\ - defined(STM32F105RC)||\ - defined(STM32F105V8)||\ - defined(STM32F105VB)||\ - defined(STM32F105VC) -#define STM32_SRAM_SIZE 64 -//#define STM32F105xC -#elif \ - defined(STM32F107RB)||\ - defined(STM32F107RC)||\ - defined(STM32F107VB)||\ - defined(STM32F107VC) -#define STM32_SRAM_SIZE 64 -//#define STM32F107xC +#if defined(STM32F030RB) +#define STM32_SRAM_SIZE 8 #endif + /* whether use board external SRAM memory */ // Use external SRAM memory on the board // Enable External SRAM memory #define STM32_EXT_SRAM 0 // Begin Address of External SRAM // Default: 0x68000000 -#define STM32_EXT_SRAM_BEGIN 0x68000000 /* the begining address of external SRAM */ +#define STM32_EXT_SRAM_BEGIN \ + 0x68000000 /* the begining address of external SRAM */ // End Address of External SRAM // Default: 0x68080000 #define STM32_EXT_SRAM_END 0x68080000 /* the end address of external SRAM */ @@ -213,15 +45,15 @@ #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024) #ifdef __CC_ARM extern int Image$$RW_IRAM1$$ZI$$Limit; -#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) #elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else extern int __bss_end; -#define HEAP_BEGIN ((void *)&__bss_end) +#define HEAP_BEGIN ((void *)&__bss_end) #endif -#define HEAP_END STM32_SRAM_END +#define HEAP_END STM32_SRAM_END void rt_hw_board_init(void); diff --git a/bsp/stm32f030r8-nucleo/drivers/gcc_startup.s b/bsp/stm32f030r8-nucleo/drivers/gcc_startup.s deleted file mode 100644 index ee7a673f0..000000000 --- a/bsp/stm32f030r8-nucleo/drivers/gcc_startup.s +++ /dev/null @@ -1,104 +0,0 @@ -/** - *************** (C) COPYRIGHT 2017 STMicroelectronics ************************ - * @file gcc_startup.s - * @author MCD Application Team - * @version V4.2.0 - * @date 31-March-2017 - * @brief Based on STM32F103xE's startup file. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Configure external SRAM mounted on STM3210E-EVAL board - * to be used as data memory (optional, to be enabled by user) - * - Branches to entry in the C library (which eventually - * calls main(), but entry() in RT-Thread). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .global Reset_Handler - - .section .text.Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl entry - bx lr -.size Reset_Handler, .-Reset_Handler - diff --git a/bsp/stm32f030r8-nucleo/drivers/startup_stm32f030x8.s b/bsp/stm32f030r8-nucleo/drivers/startup_stm32f030x8.s new file mode 100644 index 000000000..e3fa93dfd --- /dev/null +++ b/bsp/stm32f030r8-nucleo/drivers/startup_stm32f030x8.s @@ -0,0 +1,286 @@ +/** + ****************************************************************************** + * @file startup_stm32f030x8.s + * @author MCD Application Team + * @brief STM32F030x8 devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word 0 /* Reserved */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* Reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* Reserved */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM6_IRQHandler /* TIM6 */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word TIM15_IRQHandler /* TIM15 */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word I2C2_IRQHandler /* I2C2 */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak I2C2_IRQHandler + .thumb_set I2C2_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_hal_conf.h b/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_hal_conf.h new file mode 100644 index 000000000..cbf98b21c --- /dev/null +++ b/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_hal_conf.h @@ -0,0 +1,324 @@ +/** + ****************************************************************************** + * @file stm32f0xx_hal_conf.h + * @brief HAL configuration file. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2018 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_HAL_CONF_H +#define __STM32F0xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "main.h" +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_CAN_MODULE_ENABLED */ +/*#define HAL_CEC_MODULE_ENABLED */ +/*#define HAL_COMP_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_TSC_MODULE_ENABLED */ +/*#define HAL_DAC_MODULE_ENABLED */ +/*#define HAL_I2S_MODULE_ENABLED */ +#define HAL_IWDG_MODULE_ENABLED +/*#define HAL_LCD_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/*#define HAL_USART_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED */ +/*#define HAL_SMBUS_MODULE_ENABLED */ +#define HAL_WWDG_MODULE_ENABLED +/*#define HAL_PCD_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + * Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + * Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) + #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator for ADC (HSI14) value. + */ +#if !defined (HSI14_VALUE) +#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI14_VALUE */ + +/** + * @brief Internal High Speed oscillator for USB (HSI48) value. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)40000) +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSI) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */ + /* Warning: Must be set to higher priority for HAL_Delay() */ + /* and HAL_GetTick() usage under interrupt context */ +#define USE_RTOS 0 +#define PREFETCH_ENABLE 1 +#define INSTRUCTION_CACHE_ENABLE 0 +#define DATA_CACHE_ENABLE 0 +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f0xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f0xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f0xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED + #include "stm32f0xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f0xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED + #include "stm32f0xx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_hal_msp.c b/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_hal_msp.c new file mode 100644 index 000000000..40f87faa6 --- /dev/null +++ b/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_hal_msp.c @@ -0,0 +1,197 @@ +/** + ****************************************************************************** + * File Name : stm32f0xx_hal_msp.c + * Description : This file provides code for the MSP Initialization + * and de-Initialization codes. + ****************************************************************************** + ** This notice applies to any and all portions of this file + * that are not between comment pairs USER CODE BEGIN and + * USER CODE END. Other portions of this file, whether + * inserted by the user or by software development tools + * are owned by their respective copyright owners. + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" + +extern void _Error_Handler(char *, int); +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + + /* System interrupt init*/ + /* SVC_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SVC_IRQn, 0, 0); + /* PendSV_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); + /* SysTick_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + PA12 ------> USART1_DE + */ + GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF1_USART1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspInit 0 */ + + /* USER CODE END USART2_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_USART2_CLK_ENABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_USART2; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USER CODE BEGIN USART2_MspInit 1 */ + + /* USER CODE END USART2_MspInit 1 */ + } + +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) +{ + + if(huart->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PA9 ------> USART1_TX + PA10 ------> USART1_RX + PA12 ------> USART1_DE + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_12); + + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } + else if(huart->Instance==USART2) + { + /* USER CODE BEGIN USART2_MspDeInit 0 */ + + /* USER CODE END USART2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART2_CLK_DISABLE(); + + /**USART2 GPIO Configuration + PA2 ------> USART2_TX + PA3 ------> USART2_RX + */ + HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); + + /* USER CODE BEGIN USART2_MspDeInit 1 */ + + /* USER CODE END USART2_MspDeInit 1 */ + } + +} + +void HAL_WWDG_MspInit(WWDG_HandleTypeDef* hwwdg) +{ + + if(hwwdg->Instance==WWDG) + { + /* USER CODE BEGIN WWDG_MspInit 0 */ + + /* USER CODE END WWDG_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_WWDG_CLK_ENABLE(); + /* USER CODE BEGIN WWDG_MspInit 1 */ + + /* USER CODE END WWDG_MspInit 1 */ + } + +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.c b/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.c new file mode 100644 index 000000000..7cd8f844b --- /dev/null +++ b/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.c @@ -0,0 +1,73 @@ +/** + ****************************************************************************** + * @file stm32f0xx_it.c + * @brief Interrupt Service Routines. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" +#include "stm32f0xx.h" +#include "stm32f0xx_it.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* External variables --------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M0 Processor Interruption and Exception Handlers */ +/******************************************************************************/ + +/** +* @brief This function handles System tick timer. +*/ +void SysTick_Handler(void) +{ + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + HAL_SYSTICK_IRQHandler(); + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + +/******************************************************************************/ +/* STM32F0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file (startup_stm32f0xx.s). */ +/******************************************************************************/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.h b/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.h new file mode 100644 index 000000000..a40bc0f5f --- /dev/null +++ b/bsp/stm32f030r8-nucleo/drivers/stm32f0xx_it.h @@ -0,0 +1,58 @@ +/** + ****************************************************************************** + * @file stm32f0xx_it.h + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * + * COPYRIGHT(c) 2018 STMicroelectronics + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F0xx_IT_H +#define __STM32F0xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f0xx_hal.h" +#include "main.h" +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F0xx_IT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/stm32f0x/.config b/bsp/stm32f0x/.config new file mode 100644 index 000000000..5bf36682e --- /dev/null +++ b/bsp/stm32f0x/.config @@ -0,0 +1,245 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +# CONFIG_RT_USING_MODULE is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +# CONFIG_RT_USING_FINSH is not set + +# +# Device virtual file system +# +# CONFIG_RT_USING_DFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=256 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_AUDIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# Modbus master and slave stack +# +# CONFIG_RT_USING_MODBUS is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_LOGTRACE is not set +# CONFIG_RT_USING_RYM is not set + +# +# RT-Thread online packages +# + +# +# system packages +# + +# +# RT-Thread GUI Engine +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set + +# +# language packages +# +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_IPERF is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set + +# +# example package: hello +# +# CONFIG_PKG_USING_HELLO is not set +CONFIG_STM32F030RB=y +# CONFIG_RT_USING_HSI is not set +CONFIG_RT_HSE_VALUE=8000000 +# CONFIG_RT_USING_UART1 is not set +CONFIG_RT_USING_UART2=y diff --git a/bsp/stm32f0x/Kconfig b/bsp/stm32f0x/Kconfig new file mode 100644 index 000000000..391d5709e --- /dev/null +++ b/bsp/stm32f0x/Kconfig @@ -0,0 +1,58 @@ +mainmenu "RT-Thread Configuration" + +config $BSP_DIR + string + option env="BSP_ROOT" + default "." + +config $RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config $PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" + +choice + prompt "Device type" + default STM32F030RB + config STM32F030RB + bool "STM32F030RB" + +endchoice + +config RT_USING_HSI + bool "Using HSI as clock source" + default n +config RT_HSE_VALUE + int "HSE Value" + default 8000000 + depends on !RT_USING_HSI + + +if RT_USING_SERIAL + + config RT_USING_UART1 + bool "Using uart1" + default y + + config RT_USING_UART2 + bool "Using uart2" + default n + +endif + +if RT_USING_SPI + config RT_USING_SPI1 + bool "Using spi1" + default y + config RT_USING_SPI2 + bool "Using spi2" + default n +endif + diff --git a/bsp/stm32f0x/applications/application.c b/bsp/stm32f0x/applications/application.c deleted file mode 100644 index c0fb3b4b2..000000000 --- a/bsp/stm32f0x/applications/application.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-01-05 Bernard the first version - * 2013-11-15 bright add init thread and components initial - */ - -/** - * @addtogroup STM32 - */ -/*@{*/ - -#include - -#include -#include - -#include "led.h" - -/* led thread entry */ -static void led_thread_entry(void* parameter) -{ - while(1) - { - rt_hw_led_on(); - rt_thread_delay(RT_TICK_PER_SECOND); - - rt_hw_led_off(); - rt_thread_delay(RT_TICK_PER_SECOND); - } -} - -static void rt_init_thread_entry(void* parameter) -{ - rt_thread_t led_thread; - -/* Initialization RT-Thread Components */ -#ifdef RT_USING_COMPONENTS_INIT - rt_components_init(); -#endif - -/* Set finsh device */ -#ifdef RT_USING_FINSH - finsh_set_device(RT_CONSOLE_DEVICE_NAME); -#endif /* RT_USING_FINSH */ - - /* Create led thread */ - led_thread = rt_thread_create("led", - led_thread_entry, RT_NULL, - 256, 20, 20); - if(led_thread != RT_NULL) - rt_thread_startup(led_thread); -} - -int rt_application_init() -{ - rt_thread_t init_thread; - -#if (RT_THREAD_PRIORITY_MAX == 32) - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 512, 8, 20); -#else - init_thread = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 512, 80, 20); -#endif - if(init_thread != RT_NULL) - rt_thread_startup(init_thread); - - return 0; -} - - -/*@}*/ diff --git a/bsp/stm32f0x/applications/main.c b/bsp/stm32f0x/applications/main.c new file mode 100644 index 000000000..0f5e6000a --- /dev/null +++ b/bsp/stm32f0x/applications/main.c @@ -0,0 +1,20 @@ +/* + * File : main.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2015-07-29 Arda.Fu first implementation + */ +#include + +int main(void) +{ + /* user app entry */ + return 0; +} diff --git a/bsp/stm32f0x/applications/startup.c b/bsp/stm32f0x/applications/startup.c deleted file mode 100644 index 4d9bfaa68..000000000 --- a/bsp/stm32f0x/applications/startup.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-08-31 Bernard first implementation - * 2013-11-15 bright modify for stm32f0xx version and components initial - */ - -#include -#include - -#include "board.h" - -/** - * @addtogroup STM32 - */ - -/*@{*/ - -extern int rt_application_init(void); - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#define STM32_SRAM_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) -#elif __ICCARM__ -#pragma section="HEAP" -#define STM32_SRAM_BEGIN (__segment_end("HEAP")) -#else -extern int __bss_end; -#define STM32_SRAM_BEGIN (&__bss_end) -#endif - -/******************************************************************************* -* Function Name : assert_failed -* Description : Reports the name of the source file and the source line number -* where the assert error has occurred. -* Input : - file: pointer to the source file name -* - line: assert error line source number -* Output : None -* Return : None -*******************************************************************************/ -void assert_failed(uint8_t* file, uint32_t line) -{ - rt_kprintf("\n\r Wrong parameter value detected on\r\n"); - rt_kprintf(" file %s\r\n", file); - rt_kprintf(" line %d\r\n", line); - - while (1) ; -} - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); - - /* init kernel object */ - rt_system_object_init(); - - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP - rt_system_heap_init((void*)STM32_SRAM_BEGIN, (void*)STM32_SRAM_END); -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - - /* init application */ - rt_application_init(); - - /* init timer thread */ - rt_system_timer_thread_init(); - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - rt_hw_interrupt_disable(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/stm32f0x/rtconfig.h b/bsp/stm32f0x/rtconfig.h index bee200136..259fafe1a 100644 --- a/bsp/stm32f0x/rtconfig.h +++ b/bsp/stm32f0x/rtconfig.h @@ -1,114 +1,130 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 +/* RT-Thread Kernel */ -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -#define RT_DEBUG -#define RT_DEBUG_INIT 1 +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 #define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_IDEL_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_DEBUG -/* Using Hook */ -/* #define RT_USING_HOOK */ +/* Inter-Thread communication */ -/* Using Software Timer */ -/* #define RT_USING_TIMER_SOFT */ -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 -#define RT_TIMER_TICK_PER_SECOND 10 - -/* SECTION: IPC */ -/* Using Semaphore*/ #define RT_USING_SEMAPHORE - -/* Using Mutex */ #define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE -/* Using Event */ -/* #define RT_USING_EVENT */ +/* Memory Management */ -/* Using MailBox */ -/* #define RT_USING_MAILBOX */ - -/* Using Message Queue */ -/* #define RT_USING_MESSAGEQUEUE */ - -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -/* #define RT_USING_MEMPOOL */ - -/* Using Dynamic Heap Management */ +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM #define RT_USING_HEAP -/* Using Small MM */ -#define RT_USING_SMALL_MEM -#define RT_USING_TINY_SIZE +/* Kernel Device Object */ -// -#define RT_USING_COMPONENTS_INIT - -/* SECTION: Device System */ -/* Using Device System */ #define RT_USING_DEVICE -// -#define RT_USING_DEVICE_IPC -// -#define RT_USING_SERIAL - -/* SECTION: Console options */ #define RT_USING_CONSOLE -/* the buffer size of console*/ -#define RT_CONSOLEBUF_SIZE 128 -// -#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 1024 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ +/* Command shell */ -/* SECTION: finsh, a C-Express shell */ -#define RT_USING_FINSH -/* configure finsh parameters */ -#define FINSH_THREAD_PRIORITY 25 -#define FINSH_THREAD_STACK_SIZE 1024 -#define FINSH_HISTORY_LINES 1 -/* Using symbol table */ -//#define FINSH_USING_SYMTAB -//#define FINSH_USING_DESCRIPTION -#define FINSH_USING_MSH -#define FINSH_USING_MSH_ONLY -/* SECTION: libc management */ -// #define RT_USING_LIBC +/* Device virtual file system */ -/* SECTION: device filesystem */ -/* #define RT_USING_DFS */ -//#define RT_USING_DFS_ELMFAT -#define RT_DFS_ELM_WORD_ACCESS -/* Reentrancy (thread safe) of the FatFs module. */ -#define RT_DFS_ELM_REENTRANT -/* Number of volumes (logical drives) to be used. */ -#define RT_DFS_ELM_DRIVES 2 -/* #define RT_DFS_ELM_USE_LFN 1 */ -#define RT_DFS_ELM_MAX_LFN 255 -/* Maximum sector size to be handled. */ -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 -#define RT_USING_DFS_ROMFS +/* Device Drivers */ -/* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 4 +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 256 +#define RT_USING_SERIAL +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC + +/* Network */ + +/* Socket abstraction layer */ + + +/* light weight TCP/IP stack */ + + +/* Modbus master and slave stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* system packages */ + +/* RT-Thread GUI Engine */ + + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* miscellaneous packages */ + + +/* example package: hello */ + +#define STM32F030RB +#define RT_HSE_VALUE 8000000 +#define RT_USING_UART2 #endif diff --git a/bsp/stm32f0x/ul.bat b/bsp/stm32f0x/ul.bat new file mode 100644 index 000000000..e19d48fad --- /dev/null +++ b/bsp/stm32f0x/ul.bat @@ -0,0 +1 @@ +copy rtthread.bin d:\ \ No newline at end of file