Merge pull request #641 from kontais/master
[BSP] flush cache after exception code install in loogson 1B/C
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commit
bb9bb4ea79
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@ -32,6 +32,9 @@ extern int rt_application_init(void);
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extern void tlb_refill_exception(void);
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extern void tlb_refill_exception(void);
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extern void general_exception(void);
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extern void general_exception(void);
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extern void irq_exception(void);
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extern void irq_exception(void);
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extern void rt_hw_cache_init(void);
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extern void invalidate_writeback_dcache_all(void);
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extern void invalidate_icache_all(void);
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/**
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/**
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* This function will startup RT-Thread RTOS.
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* This function will startup RT-Thread RTOS.
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@ -51,6 +54,9 @@ void rtthread_startup(void)
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rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
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rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
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rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
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rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
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invalidate_writeback_dcache_all();
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invalidate_icache_all();
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/* init board */
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/* init board */
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rt_hw_board_init();
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rt_hw_board_init();
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@ -33,6 +33,9 @@ extern int rt_application_init(void);
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extern void tlb_refill_exception(void);
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extern void tlb_refill_exception(void);
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extern void general_exception(void);
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extern void general_exception(void);
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extern void irq_exception(void);
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extern void irq_exception(void);
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extern void rt_hw_cache_init(void);
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extern void invalidate_writeback_dcache_all(void);
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extern void invalidate_icache_all(void);
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/**
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/**
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* This function will startup RT-Thread RTOS.
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* This function will startup RT-Thread RTOS.
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@ -52,6 +55,9 @@ void rtthread_startup(void)
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rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
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rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
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rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
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rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
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invalidate_writeback_dcache_all();
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invalidate_icache_all();
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/* init board */
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/* init board */
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rt_hw_board_init();
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rt_hw_board_init();
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@ -13,6 +13,7 @@
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* 2011-08-08 lgnq modified for LS1B
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* 2011-08-08 lgnq modified for LS1B
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*/
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*/
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#include <rtthread.h>
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#include "../common/mipsregs.h"
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#include "../common/mipsregs.h"
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#define K0BASE 0x80000000
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#define K0BASE 0x80000000
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@ -23,6 +24,7 @@ extern void Invalidate_Icache_Ls1b(unsigned int);
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extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int);
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extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int);
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extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
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extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
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extern void Writeback_Invalidate_Dcache(unsigned int);
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extern void Writeback_Invalidate_Dcache(unsigned int);
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extern void enable_cpu_cache(void);
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typedef struct cacheinfo_t
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typedef struct cacheinfo_t
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{
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{
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@ -151,7 +153,7 @@ void invalidate_dcache_all(void)
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unsigned int end = (start + pcacheinfo->dcache_size);
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unsigned int end = (start + pcacheinfo->dcache_size);
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while (start <end)
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while (start <end)
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{
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{
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Invalidate_Dcache_Fill_Gc3210I(start);
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Invalidate_Dcache_Fill_Ls1b(start);
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start += pcacheinfo->icacheline_size;
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start += pcacheinfo->icacheline_size;
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}
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}
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}
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}
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@ -14,6 +14,7 @@
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* 2015-07-08 chinesebear modified for loongson 1c
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* 2015-07-08 chinesebear modified for loongson 1c
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*/
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*/
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#include <rtthread.h>
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#include "../common/mipsregs.h"
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#include "../common/mipsregs.h"
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#define K0BASE 0x80000000
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#define K0BASE 0x80000000
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@ -24,6 +25,7 @@ extern void Invalidate_Icache_Ls1c(unsigned int);
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extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
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extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
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extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
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extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
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extern void Writeback_Invalidate_Dcache(unsigned int);
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extern void Writeback_Invalidate_Dcache(unsigned int);
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extern void enable_cpu_cache(void);
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typedef struct cacheinfo_t
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typedef struct cacheinfo_t
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{
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{
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@ -152,7 +154,7 @@ void invalidate_dcache_all(void)
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unsigned int end = (start + pcacheinfo->dcache_size);
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unsigned int end = (start + pcacheinfo->dcache_size);
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while (start <end)
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while (start <end)
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{
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{
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Invalidate_Dcache_Fill_Gc3210I(start);
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Invalidate_Dcache_Fill_Ls1c(start);
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start += pcacheinfo->icacheline_size;
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start += pcacheinfo->icacheline_size;
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}
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}
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}
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}
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