update jz47xx branch code.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@892 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong@gmail.com
parent
144af8fcfe
commit
b63899a92a
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@ -46,6 +46,7 @@ void rt_hw_board_init()
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/* init hardware UART device */
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rt_hw_uart_init();
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#endif
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device("uart");
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@ -17,6 +17,7 @@
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void rt_hw_board_init(void);
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/* 32M SDRAM */
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#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024)
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#endif
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@ -11,20 +11,33 @@
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* Date Author Notes
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* 2010-05-17 swkyer first version
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* 2010-08-23 bernard change to jz47xx
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* 2010-09-04 bernard move the beginning entry to 0x80100000
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*/
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OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
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OUTPUT_ARCH(mips)
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ENTRY(_entry)
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MEMORY
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{
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/* 16M SDRAM */
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DRAM : ORIGIN = 0x80100000, LENGTH = 0x01000000
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/* 16K SRAM */
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IRAM : ORIGIN = 0x80000000, LENGTH = 0x00004000
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}
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ENTRY(_start)
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SECTIONS
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{
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.start 0x80000000:
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. = 0x80100000 ;
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.start :
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{
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*(.start);
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}
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.text ALIGN(0x4) :
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} > DRAM
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. = ALIGN(4);
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.text :
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{
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*(.text)
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*(.text.*)
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@ -43,9 +56,11 @@ SECTIONS
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(4);
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}
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.data ALIGN(0x4) :
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} > DRAM
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. = ALIGN(4);
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.data :
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{
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*(.data)
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*(.data.*)
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@ -58,25 +73,48 @@ SECTIONS
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*(.sdata)
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*(.sdata.*)
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}
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} > DRAM
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. = ALIGN(4);
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_iramat = .;
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.iram : AT(_iramat)
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{
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_iramstart = .;
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*(.vectors.1);
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. = 0x100;
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*(.vectors.2);
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. = 0x180;
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*(.vectors.3);
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. = 0x200;
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*(.vectors.4);
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*(.vectors);
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*(.icode);
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*(.irodata);
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*(.idata);
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KEEP(*(.vectors*))
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_iramend = .;
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} > IRAM
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_iramcopy = LOADADDR(.iram);
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__bss_start = ABSOLUTE(.);
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.sbss :
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{
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__bss_start = .;
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*(.sbss)
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*(.sbss.*)
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*(.dynsbss)
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*(.scommon)
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}
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} > DRAM
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.bss :
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{
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*(.bss)
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*(.bss.*)
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*(.dynbss)
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*(COMMON)
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}
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__bss_end = ABSOLUTE(.);
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__bss_end = .;
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} > DRAM
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_end = .;
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@ -113,4 +151,4 @@ SECTIONS
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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}
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}
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@ -3,13 +3,13 @@
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#define __RTTHREAD_CFG_H__
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/* RT_NAME_MAX*/
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#define RT_NAME_MAX 8
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#define RT_NAME_MAX 10
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/* RT_ALIGN_SIZE*/
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#define RT_ALIGN_SIZE 4
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/* PRIORITY_MAX */
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#define RT_THREAD_PRIORITY_MAX 32
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#define RT_THREAD_PRIORITY_MAX 256
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/* Tick per Second */
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#define RT_TICK_PER_SECOND 100
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@ -57,12 +57,13 @@
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/* SECTION: Device System */
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/* Using Device System */
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#define RT_USING_DEVICE
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/* RT_USING_UART */
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#define RT_USING_UART0
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#define RT_USING_UART
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#define RT_USING_UART1
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#define RT_UART_RX_BUFFER_SIZE 64
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/* SECTION: Console options */
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/* the buffer size of console */
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#define RT_USING_CONSOLE
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#define RT_CONSOLEBUF_SIZE 128
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/* SECTION: finsh, a C-Express shell */
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@ -51,7 +51,7 @@ if rtconfig_ns.has_key('RT_USING_MODULE'):
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ARCH='mips'
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CPU='jz47xx'
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CROSS_TOOL = 'gcc'
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CROSS_TOOL = 'gcc'
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PLATFORM = 'gcc'
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EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
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BUILD = 'debug'
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@ -82,4 +82,6 @@ else:
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CFLAGS += ' -O2'
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RT_USING_MINILIBC = True
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POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
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DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
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COPY_ACTION = 'copy rtthread.bin usbboot\n'
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POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + DUMP_ACTION + COPY_ACTION
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@ -25,17 +25,33 @@
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extern unsigned char __bss_start;
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extern unsigned char __bss_end;
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extern int rt_application_init(void);
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extern int rt_application_init(void);
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void dump_memory(rt_uint8_t* ptr, rt_size_t size)
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{
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rt_size_t index;
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for (index = 0; index < size; index ++)
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{
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rt_kprintf("%02x ", ptr[index] & 0xff);
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if ((index + 1) % 16 == 0) rt_kprintf("\n");
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}
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}
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/**
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* This function will startup RT-Thread RTOS.
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*/
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void rtthread_startup(void)
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{
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/* init hardware interrupt */
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rt_hw_interrupt_init();
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/* init board */
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rt_hw_board_init();
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rt_show_version();
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dump_memory((rt_uint8_t*)0x80000200, 32);
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/* init tick */
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rt_system_tick_init();
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@ -1,5 +1,6 @@
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#include <rthw.h>
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#include <rtthread.h>
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#include <jz47xx.h>
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/**
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* @addtogroup Jz47xx
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@ -9,30 +10,29 @@
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#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
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#define UART_BAUDRATE 115200
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#define DEV_CLK 12000000
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#define DEV_CLK 12000000
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/*
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* Define macros for UARTIER
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* UART Interrupt Enable Register
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*/
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#define UARTIER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
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#define UARTIER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
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#define UARTIER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
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#define UARTIER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
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#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
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#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
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#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
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#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
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/*
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* Define macros for UARTISR
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* UART Interrupt Status Register
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*/
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#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
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#define UARTISR_IID (7 << 1) /* Source of Interrupt */
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#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
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#define UARTISR_IID (7 << 1) /* Source of Interrupt */
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#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */
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#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
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#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */
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#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
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#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
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#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
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#define UARTISR_FFMS_NO_FIFO (0 << 6)
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#define UARTISR_FFMS_FIFO_MODE (3 << 6)
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@ -40,11 +40,11 @@
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* Define macros for UARTFCR
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* UART FIFO Control Register
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*/
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#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
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#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
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#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
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#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
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#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
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#define UARTFCR_UUE (1 << 4) /* 0: disable UART */
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#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
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#define UARTFCR_UUE (1 << 4) /* 0: disable UART */
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#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
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#define UARTFCR_RTRG_1 (0 << 6)
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#define UARTFCR_RTRG_4 (1 << 6)
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@ -62,7 +62,7 @@
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#define UARTLCR_WLEN_8 (3 << 0)
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#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
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1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
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#define UARTLCR_PE (1 << 3) /* 0: parity disable */
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#define UARTLCR_PE (1 << 3) /* 0: parity disable */
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#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
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#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */
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#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
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@ -72,11 +72,11 @@
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* Define macros for UARTLSR
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* UART Line Status Register
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*/
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#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
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#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
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#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */
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#define UARTLSR_PER (1 << 2) /* 0: no parity error */
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#define UARTLSR_FER (1 << 3) /* 0; no framing error */
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#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
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#define UARTLSR_PER (1 << 2) /* 0: no parity error */
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#define UARTLSR_FER (1 << 3) /* 0; no framing error */
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#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
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#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
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#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
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#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
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@ -85,12 +85,12 @@
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* Define macros for UARTMCR
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* UART Modem Control Register
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*/
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#define UARTMCR_DTR (1 << 0) /* 0: DTR_ ouput high */
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#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high */
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#define UARTMCR_DTR (1 << 0) /* 0: DTR_ ouput high */
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#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high */
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#define UARTMCR_OUT1 (1 << 2) /* 0: UARTMSR.RI is set to 0 and RI_ input high */
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#define UARTMCR_OUT2 (1 << 3) /* 0: UARTMSR.DCD is set to 0 and DCD_ input high */
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#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
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#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
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#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
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/*
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* Define macros for UARTMSR
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@ -98,12 +98,12 @@
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*/
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#define UARTMSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UARTMSR */
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#define UARTMSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UARTMSR */
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#define UARTMSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UARTMSR */
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#define UARTMSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UARTMSR */
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#define UARTMSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UARTMSR */
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#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
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#define UARTMSR_DSR (1 << 5) /* 0: DSR_ pin is high */
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#define UARTMSR_RI (1 << 6) /* 0: RI_ pin is high */
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#define UARTMSR_DCD (1 << 7) /* 0: DCD_ pin is high */
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#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
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#define UARTMSR_DSR (1 << 5) /* 0: DSR_ pin is high */
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#define UARTMSR_RI (1 << 6) /* 0: RI_ pin is high */
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#define UARTMSR_DCD (1 << 7) /* 0: DCD_ pin is high */
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/*
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* Define macros for SIRCR
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@ -209,8 +209,11 @@ static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
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{
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/* Enable the UART Interrupt */
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UART_IER(uart->hw_base) |= (UARTIER_RIE | UARTIER_RTIE);
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}
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/* install interrupt */
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rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL);
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rt_hw_interrupt_umask(uart->irq);
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}
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return RT_EOK;
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}
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@ -293,13 +296,13 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer
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if (*ptr == '\n')
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{
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/* FIFO status, contain valid data */
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while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
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while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
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/* write data */
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UART_TDR(uart->hw_base) = '\r';
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}
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/* FIFO status, contain valid data */
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while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
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while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
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/* write data */
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UART_TDR(uart->hw_base) = *ptr;
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@ -336,6 +339,19 @@ void rt_hw_uart_init(void)
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uart->parent.type = RT_Device_Class_Char;
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rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
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uart->read_index = uart->save_index = 0;
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#if defined(RT_USING_UART0)
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uart->hw_base = UART0_BASE;
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uart->irq = IRQ_UART0;
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#elif defined(RT_USING_UART1)
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uart->hw_base = UART1_BASE;
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uart->irq = IRQ_UART1;
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#elif defined(RT_USING_UART2)
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uart->hw_base = UART2_BASE;
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uart->irq = IRQ_UART2;
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#elif defined(RT_USING_UART3)
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uart->hw_base = UART3_BASE;
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uart->irq = IRQ_UART3;
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#endif
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/* device interface */
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uart->parent.init = rt_uart_init;
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