add GNU GCC support in LPC2478.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1333 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong
parent
24dfbe437d
commit
b5fbd46776
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@ -3,15 +3,8 @@ Import('RTT_ROOT')
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from building import *
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src_bsp = ['application.c', 'startup.c', 'board.c']
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src_drv = []
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if GetDepend('RT_USING_DFS'):
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src_drv += ['sd.c', 'spi.c']
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if GetDepend('RT_USING_LWIP'):
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src_drv += ['emac.c']
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src = File(src_bsp + src_drv)
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src = File(src_bsp)
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CPPPATH = [RTT_ROOT + '/bsp/lpc2478']
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group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
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@ -6,7 +6,7 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread-lpc2478.' + rtconfig.TARGET_EXT
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TARGET = 'rtthread-lpc.' + rtconfig.TARGET_EXT
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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@ -21,15 +21,6 @@ Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT)
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if GetDepend('RT_USING_WEBSERVER'):
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objs = objs + SConscript(RTT_ROOT + '/components/net/webserver/SConscript', variant_dir='build/net/webserver', duplicate=0)
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if GetDepend('RT_USING_RTGUI'):
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objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
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# libc testsuite
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# objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
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# build program
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env.Program(TARGET, objs)
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@ -18,54 +18,8 @@
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* @addtogroup LPC2478
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*/
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/*@{*/
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char thread1_stack[512];
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char thread2_stack[512];
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struct rt_thread thread1;
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struct rt_thread thread2;
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void thread1_entry(void* parameter)
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{
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int i;
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while (1)
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{
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for (i = 0; i < 10; i ++)
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{
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rt_kprintf("%d\n", i);
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rt_thread_delay(100);
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}
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}
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}
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void thread2_entry(void* parameter)
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{
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int count = 0;
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while (1)
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{
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rt_kprintf("Thread2 count:%d\n", count++);
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rt_thread_delay(50);
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}
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}
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int rt_application_init()
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{
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rt_thread_init(&thread1,
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"thread1",
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thread1_entry, RT_NULL,
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&thread1_stack[0], sizeof(thread1_stack),
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20, 10);
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rt_thread_init(&thread2,
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"thread2",
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thread2_entry, RT_NULL,
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&thread2_stack[0], sizeof(thread2_stack),
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25, 8);
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rt_thread_startup(&thread1);
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rt_thread_startup(&thread2);
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return 0;
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}
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@ -18,9 +18,9 @@
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#include <LPC24xx.h>
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#include "board.h"
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/* #define RT_BOARD_DEBUG */
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#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */
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#define DATA_COUNT 14400000/RT_TICK_PER_SECOND /* T0MR0 = delayInMs * (Fpclk / 1000); */
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extern void rt_hw_serial_init(void);
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/**
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* @addtogroup LPC2478
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@ -29,70 +29,21 @@
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void rt_timer_handler(int vector)
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{
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#ifdef BOARD_DEBUG
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rt_kprintf("timer handler, increase a tick\n");
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#endif
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T0IR |= 0x01; /* clear interrupt flag */
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rt_tick_increase();
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VICVectAddr = 0; /* Acknowledge Interrupt */
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}
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/**
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* This function is used to display a string on console, normally, it's
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* invoked by rt_kprintf
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*
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* @param str the displayed string
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*/
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void rt_hw_console_output(const char* str)
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{
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while (*str)
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{
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if (*str=='\n')
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{
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while (!(U0LSR & 0x20));
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U0THR = '\r';
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}
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while (!(U0LSR & 0x20));
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U0THR = *str;
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str ++;
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}
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}
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#define BAUD_RATE 115200
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#define U0PINS 0x50
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void rt_hw_console_init()
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{
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rt_uint32_t fdiv;
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/* Enable RxD and TxD pins */
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PINSEL0 = U0PINS;
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/* 8 bits, no Parity, 1 Stop bit */
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U0LCR = 0x83;
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/* Setup Baudrate */
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fdiv = ( PCLK / 16 ) / BAUD_RATE ; /*baud rate */
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U0DLM = fdiv / 256;
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U0DLL = fdiv % 256;
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U0FCR = 0x00; /* Enable and reset TX and RX FIFO. */
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U0LCR = 0x03; /* DLAB = 0 */
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/* DLAB = 0 */
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U0LCR = 0x03;
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}
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/**
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* This function will init LPC2478 board
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*/
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void rt_hw_board_init()
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{
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/* init console for rt_kprintf function */
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rt_hw_console_init();
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#if defined(RT_USING_DEVICE) && defined(RT_USING_UART1)
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rt_hw_serial_init();
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rt_console_set_device("uart1");
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#endif
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T0IR = 0xff;
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T0TC = 0;
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T0MCR = 0x03;
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@ -1,105 +1,144 @@
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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/*
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* linker script for LPC2478 with GNU ld
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* bernard.xiong 2011-03-17
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*/
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/* Program Entry, set to mark it as "used" and avoid gc */
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MEMORY
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{
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CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000
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DATA (rw) : ORIGIN = 0x40000000, LENGTH = 0x00010000
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}
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ENTRY(_start)
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SECTIONS
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{
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. = 0x00000000;
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.text :
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{
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*(.init)
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*(.text)
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*(.text.*) /* remaining code */
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*(.rodata) /* read-only data (constants) */
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*(.rodata*)
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*(.glue_7)
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*(.glue_7t)
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*(.gnu.linkonce.t*)
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__text_start = .;
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.text :
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{
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*(.vectors)
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*(.text)
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*(.text.*)
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} =0
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/* section information for finsh shell */
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(4);
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__text_end = .;
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__rodata_start = .;
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.rodata :
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{
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*(.rodata)
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*(.rodata.*)
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/* section information for finsh shell */
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(4);
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}
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__rodata_end = .;
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. = 0x40000000; /*Data in SRAM*/
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__data_start = .;
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. = ALIGN(4);
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.data :
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{
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*(.data)
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*(.data.*)
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}
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__data_end = .;
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. = ALIGN(4);
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_etext = .;
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} > CODE = 0
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. = ALIGN(4);
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__bss_start = __data_end;
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.bss :
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{
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN(4);
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}
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. = ALIGN(4);
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__bss_end = .;
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. = ALIGN(4);
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.ctors :
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{
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PROVIDE(__ctors_start__ = .);
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KEEP(*(SORT(.ctors.*)))
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KEEP(*(.ctors))
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PROVIDE(__ctors_end__ = .);
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} > CODE
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. = ALIGN(4);
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__UndStack_start = __bss_end;
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.UndStack : { *(.UndStack) }
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__UndStack_end = ( __UndStack_start + 0x00000100 );
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. = ALIGN(4);
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__IRQStack_start = __UndStack_end;
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.IRQStack : { *(.IRQStack) }
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__IRQStack_end = ( __IRQStack_start + 0x00000400 );
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. = ALIGN(4);
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__FIQStack_start = __IRQStack_end;
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.FIQStack : { *(.FIQStack) }
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__FIQStack_end = ( __FIQStack_start + 0x00000400 );
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. = ALIGN(4);
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__SVCStack_start = __FIQStack_end;
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.SVCStack : { *(.SVCStack) }
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__SVCStack_end = ( __SVCStack_start + 0x00000400 );
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. = ALIGN(4);
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__ABTStack_start = __SVCStack_end;
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.ABTStack : { *(.ABTStack) }
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__ABTStack_end = ( __ABTStack_start + 0x00000400 );
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. = ALIGN(4);
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__USRStack_start = __ABTStack_end;
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.USRStack : { *(.USRStack) }
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__USRStack_end = ( __USRStack_start + 0x00000400 );
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. = ALIGN(4);
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__Heap_start = __USRStack_end;
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.Heap : { *(.Heap) }
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__Heap_end = (__Heap_start + 0x00004000);
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.dtors :
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{
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PROVIDE(__dtors_start__ = .);
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KEEP(*(SORT(.dtors.*)))
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KEEP(*(.dtors))
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PROVIDE(__dtors_end__ = .);
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} > CODE
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* This is used by the startup in order to initialize the .data secion */
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_sidata = .;
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} > CODE
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__exidx_end = .;
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_end = .;
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/* .data section which is used for initialized data */
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.data : AT (_sidata)
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_sdata = . ;
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d*)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >DATA
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__data_end = .;
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.noinit :
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{
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*(.bss.noinit)
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} > DATA
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__bss_start = .;
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.bss :
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{
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_sbss = .;
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*(.bss)
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*(COMMON)
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .bss secion */
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_ebss = . ;
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_estack = .;
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} > DATA
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__bss_end = .;
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_end = .;
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF debug sections.
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* Symbols in the DWARF debugging sections are relative to the beginning
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* of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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}
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@ -0,0 +1,143 @@
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### uVision2 Project, (C) Keil Software
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### Do not modify !
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Target (RT-Thread LPC2478), 0x0004 // Tools: 'ARM-ADS'
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Group (Startup)
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Group (Kernel)
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Group (LPC24XX)
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Group (finsh)
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File 1,1,<.\application.c><application.c>
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File 1,1,<.\startup.c><startup.c>
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File 1,1,<.\board.c><board.c>
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File 2,1,<..\..\src\clock.c><clock.c>
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File 2,1,<..\..\src\device.c><device.c>
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File 2,1,<..\..\src\idle.c><idle.c>
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File 2,1,<..\..\src\ipc.c><ipc.c>
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File 2,1,<..\..\src\irq.c><irq.c>
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File 2,1,<..\..\src\kservice.c><kservice.c>
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File 2,1,<..\..\src\mem.c><mem.c>
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File 2,1,<..\..\src\mempool.c><mempool.c>
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File 2,1,<..\..\src\module.c><module.c>
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File 2,1,<..\..\src\object.c><object.c>
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File 2,1,<..\..\src\rtm.c><rtm.c>
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File 2,1,<..\..\src\scheduler.c><scheduler.c>
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File 2,1,<..\..\src\slab.c><slab.c>
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File 2,1,<..\..\src\thread.c><thread.c>
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File 2,1,<..\..\src\timer.c><timer.c>
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File 3,1,<..\..\libcpu\arm\lpc24xx\cpu.c><cpu.c>
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File 3,1,<..\..\libcpu\arm\lpc24xx\interrupt.c><interrupt.c>
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File 3,1,<..\..\libcpu\arm\lpc24xx\serial.c><serial.c>
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File 3,1,<..\..\libcpu\arm\lpc24xx\stack.c><stack.c>
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File 3,1,<..\..\libcpu\arm\lpc24xx\trap.c><trap.c>
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File 3,2,<..\..\libcpu\arm\lpc24xx\context_rvds.S><context_rvds.S>
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File 3,2,<..\..\libcpu\arm\lpc24xx\start_rvds.S><start_rvds.S>
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File 3,1,<..\..\libcpu\arm\common\backtrace.c><backtrace.c>
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File 3,1,<..\..\libcpu\arm\common\div0.c><div0.c>
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File 3,1,<..\..\libcpu\arm\common\showmem.c><showmem.c>
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File 4,1,<..\..\components\finsh\cmd.c><cmd.c>
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File 4,1,<..\..\components\finsh\finsh_compiler.c><finsh_compiler.c>
|
||||
File 4,1,<..\..\components\finsh\finsh_error.c><finsh_error.c>
|
||||
File 4,1,<..\..\components\finsh\finsh_heap.c><finsh_heap.c>
|
||||
File 4,1,<..\..\components\finsh\finsh_init.c><finsh_init.c>
|
||||
File 4,1,<..\..\components\finsh\finsh_node.c><finsh_node.c>
|
||||
File 4,1,<..\..\components\finsh\finsh_ops.c><finsh_ops.c>
|
||||
File 4,1,<..\..\components\finsh\finsh_parser.c><finsh_parser.c>
|
||||
File 4,1,<..\..\components\finsh\finsh_token.c><finsh_token.c>
|
||||
File 4,1,<..\..\components\finsh\finsh_var.c><finsh_var.c>
|
||||
File 4,1,<..\..\components\finsh\finsh_vm.c><finsh_vm.c>
|
||||
File 4,1,<..\..\components\finsh\shell.c><shell.c>
|
||||
File 4,1,<..\..\components\finsh\symbol.c><symbol.c>
|
||||
|
||||
|
||||
Options 1,0,0 // Target 'RT-Thread LPC2478'
|
||||
Device (LPC2478)
|
||||
Vendor (NXP (founded by Philips))
|
||||
Cpu (IRAM(0x40000000-0x4000FFFF) IRAM2(0x7FE00000-0x7FE03FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
|
||||
FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 38400 1))
|
||||
StupF ("STARTUP\Philips\LPC2400.s" ("Philips LPC2400 Startup Code"))
|
||||
FlashDR (UL2ARM(-U268761108 -O7 -S0 -C0 -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07E000))
|
||||
DevID (4307)
|
||||
Rgf (LPC23xx.H)
|
||||
Mem ()
|
||||
C ()
|
||||
A ()
|
||||
RL ()
|
||||
OH ()
|
||||
DBC_IFX ()
|
||||
DBC_CMS ()
|
||||
DBC_AMS ()
|
||||
DBC_LMS ()
|
||||
UseEnv=0
|
||||
EnvBin ()
|
||||
EnvInc ()
|
||||
EnvLib ()
|
||||
EnvReg (Philips\)
|
||||
OrgReg (Philips\)
|
||||
TgStat=16
|
||||
OutDir (.\obj\)
|
||||
OutName (rtthread-lpc)
|
||||
GenApp=1
|
||||
GenLib=0
|
||||
GenHex=0
|
||||
Debug=1
|
||||
Browse=1
|
||||
LstDir (.\obj\)
|
||||
HexSel=1
|
||||
MG32K=0
|
||||
TGMORE=0
|
||||
RunUsr 0 0 <>
|
||||
RunUsr 1 0 <>
|
||||
BrunUsr 0 0 <>
|
||||
BrunUsr 1 0 <>
|
||||
CrunUsr 0 0 <>
|
||||
CrunUsr 1 0 <>
|
||||
SVCSID <>
|
||||
GLFLAGS=1790
|
||||
ADSFLGA { 243,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
ACPUTYP (ARM7TDMI)
|
||||
RVDEV ()
|
||||
ADSTFLGA { 0,12,16,2,99,0,0,66,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
OCMADSIRAM { 0,0,0,0,64,0,0,1,0 }
|
||||
OCMADSIROM { 1,0,0,0,0,0,0,8,0 }
|
||||
OCMADSXRAM { 0,0,0,0,0,0,0,0,0 }
|
||||
OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,8,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,0,1,0,0,0,0,224,127,0,64,0,0 }
|
||||
RV_STAVEC ()
|
||||
ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
ADSCMISC ()
|
||||
ADSCDEFN ()
|
||||
ADSCUDEF ()
|
||||
ADSCINCD (..\..\include;..\..\libcpu\arm\common;..\..\components\finsh;..\..\libcpu\arm\lpc24xx;.)
|
||||
ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
ADSAMISC ()
|
||||
ADSADEFN ()
|
||||
ADSAUDEF ()
|
||||
ADSAINCD ()
|
||||
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
IncBld=1
|
||||
AlwaysBuild=0
|
||||
GenAsm=0
|
||||
AsmAsm=0
|
||||
PublicsOnly=0
|
||||
StopCode=3
|
||||
CustArgs ()
|
||||
LibMods ()
|
||||
ADSLDFG { 17,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
|
||||
ADSLDTA (0x00000000)
|
||||
ADSLDDA (0x10000000)
|
||||
ADSLDSC ()
|
||||
ADSLDIB ()
|
||||
ADSLDIC ()
|
||||
ADSLDMC ( --keep __fsym_* --keep __vsym_*)
|
||||
ADSLDIF ()
|
||||
ADSLDDW ()
|
||||
OPTDL (SARM.DLL)(-cLPC24xx)(DARMP.DLL)(-pLPC2478)(SARM.DLL)()(TARMP.DLL)(-pLPC2478)
|
||||
OPTDBG 48125,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
|
||||
FLASH1 { 9,0,0,0,1,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0 }
|
||||
FLASH2 (BIN\UL2ARM.DLL)
|
||||
FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1))
|
||||
FLASH4 ()
|
||||
EndOpt
|
||||
|
||||
|
|
@ -67,6 +67,7 @@
|
|||
#define RT_UART_RX_BUFFER_SIZE 64
|
||||
|
||||
/* SECTION: Console options */
|
||||
#define RT_USING_CONSOLE
|
||||
/* the buffer size of console*/
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
|
||||
|
|
@ -77,14 +78,6 @@
|
|||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
|
||||
/* SECTION: a mini libc */
|
||||
/* Using mini libc library*/
|
||||
/* #define RT_USING_MINILIBC */
|
||||
|
||||
/* SECTION: C++ support */
|
||||
/* Using C++ support*/
|
||||
/* #define RT_USING_CPLUSPLUS */
|
||||
|
||||
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
|
||||
/* Using lighweight TCP/IP protocol stack*/
|
||||
/* #define RT_USING_LWIP */
|
||||
|
|
|
|||
|
|
@ -12,11 +12,6 @@ elif CROSS_TOOL == 'keil':
|
|||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
print "========================="
|
||||
print "Can not support GNU GCC!!"
|
||||
print "========================="
|
||||
exit (0)
|
||||
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
|
|
|
|||
|
|
@ -73,14 +73,7 @@ void rtthread_startup(void)
|
|||
|
||||
/* init scheduler system */
|
||||
rt_system_scheduler_init();
|
||||
|
||||
#ifdef RT_USING_DEVICE
|
||||
/* init hardware serial device */
|
||||
rt_hw_serial_init();
|
||||
|
||||
/*init all registed devices*/
|
||||
rt_device_init_all();
|
||||
#endif
|
||||
/* init application */
|
||||
rt_application_init();
|
||||
|
||||
|
|
@ -106,6 +99,11 @@ void rtthread_startup(void)
|
|||
#ifdef __CC_ARM
|
||||
int main(void)
|
||||
{
|
||||
rt_uint32_t UNUSED level;
|
||||
|
||||
/* disable interrupt first */
|
||||
level = rt_hw_interrupt_disable();
|
||||
|
||||
/* invoke rtthread_startup */
|
||||
rtthread_startup();
|
||||
|
||||
|
|
|
|||
|
|
@ -52,7 +52,6 @@ void rt_hw_interrupt_init()
|
|||
*vect_addr = 0x0;
|
||||
*vect_cntl = 0xF;
|
||||
}
|
||||
|
||||
|
||||
/* init interrupt nest, and context in thread sp */
|
||||
rt_interrupt_nest = 0;
|
||||
|
|
@ -79,6 +78,7 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha
|
|||
{
|
||||
/* find first un-assigned VIC address for the handler */
|
||||
vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + vector*4);
|
||||
if (old_handler != RT_NULL) *old_handler = *vect_addr; /* get old handler */
|
||||
*vect_addr = (rt_uint32_t)new_handler; /* set interrupt vector */
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -322,7 +322,7 @@ void rt_hw_serial_init(void)
|
|||
lpc_serial->read_index = lpc_serial->save_index = 0;
|
||||
|
||||
/* Enable UART0 RxD and TxD pins */
|
||||
PINSEL0 |= 0x05;
|
||||
PINSEL0 |= 0x50;
|
||||
|
||||
/* 8 bits, no Parity, 1 Stop bit */
|
||||
UART_LCR(lpc_serial->hw_base) = 0x83;
|
||||
|
|
@ -334,6 +334,7 @@ void rt_hw_serial_init(void)
|
|||
/* DLAB = 0 */
|
||||
UART_LCR(lpc_serial->hw_base) = 0x03;
|
||||
|
||||
lpc_serial->parent.type = RT_Device_Class_Char;
|
||||
lpc_serial->parent.init = rt_serial_init;
|
||||
lpc_serial->parent.open = rt_serial_open;
|
||||
lpc_serial->parent.close = rt_serial_close;
|
||||
|
|
@ -343,7 +344,7 @@ void rt_hw_serial_init(void)
|
|||
lpc_serial->parent.user_data = RT_NULL;
|
||||
|
||||
rt_device_register(&lpc_serial->parent,
|
||||
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
|
||||
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART2
|
||||
|
|
@ -371,6 +372,7 @@ void rt_hw_serial_init(void)
|
|||
/* DLAB = 0 */
|
||||
UART_LCR(lpc_serial->hw_base) = 0x03;
|
||||
|
||||
lpc_serial->parent.type = RT_Device_Class_Char;
|
||||
lpc_serial->parent.init = rt_serial_init;
|
||||
lpc_serial->parent.open = rt_serial_open;
|
||||
lpc_serial->parent.close = rt_serial_close;
|
||||
|
|
|
|||
|
|
@ -10,13 +10,10 @@
|
|||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2008-12-11 XuXinming first version
|
||||
* 2011-03-17 Bernard update to 0.4.x
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup LPC2478
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
#define CONFIG_STACKSIZE 512
|
||||
#define WDMOD (0xE0000000 + 0x00)
|
||||
#define VICIntEnClr (0xFFFFF000 + 0x014)
|
||||
#define VICVectAddr (0xFFFFF000 + 0xF00)
|
||||
|
|
@ -26,189 +23,265 @@
|
|||
#define PLLFEED (0xE01FC000 + 0x08C)
|
||||
#define PLLSTAT (0xE01FC000 + 0x088)
|
||||
#define CCLKCFG (0xE01FC000 + 0x104)
|
||||
#define MEMMAP (0xE01FC000 + 0x040)
|
||||
#define SCS (0xE01FC000 + 0x1A0)
|
||||
#define MEMMAP (0xE01FC000 + 0x040)
|
||||
#define SCS (0xE01FC000 + 0x1A0)
|
||||
#define CLKSRCSEL (0xE01FC000 + 0x10C)
|
||||
#define MAMCR (0xE01FC000 + 0x000)
|
||||
#define MAMTIM (0xE01FC000 + 0x004)
|
||||
|
||||
/* stack memory */
|
||||
.section .bss.noinit
|
||||
.equ IRQ_STACK_SIZE, 0x00000200
|
||||
.equ FIQ_STACK_SIZE, 0x00000100
|
||||
.equ UDF_STACK_SIZE, 0x00000004
|
||||
.equ ABT_STACK_SIZE, 0x00000004
|
||||
.equ SVC_STACK_SIZE, 0x00000200
|
||||
|
||||
/*.section .init, "ax"*/
|
||||
.section .vectors
|
||||
.space IRQ_STACK_SIZE
|
||||
IRQ_STACK:
|
||||
|
||||
.space FIQ_STACK_SIZE
|
||||
FIQ_STACK:
|
||||
|
||||
.space UDF_STACK_SIZE
|
||||
UDF_STACK:
|
||||
|
||||
.space ABT_STACK_SIZE
|
||||
ABT_STACK:
|
||||
|
||||
.space SVC_STACK_SIZE
|
||||
SVC_STACK:
|
||||
|
||||
.section .init, "ax"
|
||||
.code 32
|
||||
.globl _start
|
||||
_start:
|
||||
b reset
|
||||
ldr pc, _vector_undef
|
||||
ldr pc, _vector_swi
|
||||
ldr pc, _vector_pabt
|
||||
ldr pc, _vector_dabt
|
||||
ldr pc, _vector_resv
|
||||
ldr pc, _vector_irq
|
||||
ldr pc, _vector_fiq
|
||||
b reset
|
||||
ldr pc, _vector_undef
|
||||
ldr pc, _vector_swi
|
||||
ldr pc, _vector_pabt
|
||||
ldr pc, _vector_dabt
|
||||
ldr pc, _vector_resv
|
||||
ldr pc, _vector_irq
|
||||
ldr pc, _vector_fiq
|
||||
|
||||
_vector_undef: .word vector_undef
|
||||
_vector_swi: .word vector_swi
|
||||
_vector_pabt: .word vector_pabt
|
||||
_vector_dabt: .word vector_dabt
|
||||
_vector_resv: .word vector_resv
|
||||
_vector_irq: .word vector_irq
|
||||
_vector_fiq: .word vector_fiq
|
||||
_vector_undef: .word vector_undef
|
||||
_vector_swi: .word vector_swi
|
||||
_vector_pabt: .word vector_pabt
|
||||
_vector_dabt: .word vector_dabt
|
||||
_vector_resv: .word vector_resv
|
||||
_vector_irq: .word vector_irq
|
||||
_vector_fiq: .word vector_fiq
|
||||
|
||||
.balignl 16,0xdeadbeef
|
||||
|
||||
/*
|
||||
* rtthread kernel start and end
|
||||
* which are defined in linker script
|
||||
*/
|
||||
.globl _rtthread_start
|
||||
_rtthread_start:
|
||||
.word _start
|
||||
|
||||
.globl _rtthread_end
|
||||
_rtthread_end:
|
||||
.word _end
|
||||
|
||||
/*
|
||||
* rtthread bss start and end which are defined in linker script
|
||||
*/
|
||||
.globl _bss_start
|
||||
_bss_start:
|
||||
.word __bss_start
|
||||
|
||||
.globl _bss_end
|
||||
_bss_end:
|
||||
.word __bss_end
|
||||
|
||||
.text
|
||||
.code 32
|
||||
|
||||
/* the system entry */
|
||||
reset:
|
||||
/* enter svc mode */
|
||||
msr cpsr_c, #SVCMODE|NOINT
|
||||
|
||||
/*watch dog disable */
|
||||
ldr r0,=WDMOD
|
||||
ldr r1,=0x0
|
||||
str r1,[r0]
|
||||
|
||||
/* all interrupt disable */
|
||||
ldr r0,=VICIntEnClr
|
||||
ldr r1,=0xffffffff
|
||||
str r1,[r0]
|
||||
|
||||
ldr r1, =VICVectAddr
|
||||
ldr r0, =0x00
|
||||
str r0, [r1]
|
||||
|
||||
ldr r1, =VICIntSelect
|
||||
ldr r0, =0x00
|
||||
str r0, [r1]
|
||||
|
||||
/* setup stack */
|
||||
bl stack_setup
|
||||
/* enter svc mode */
|
||||
msr cpsr_c, #SVCMODE|NOINT
|
||||
|
||||
/*watch dog disable */
|
||||
ldr r0,=WDMOD
|
||||
ldr r1,=0x0
|
||||
str r1,[r0]
|
||||
|
||||
/* all interrupt disable */
|
||||
ldr r0,=VICIntEnClr
|
||||
ldr r1,=0xffffffff
|
||||
str r1,[r0]
|
||||
|
||||
ldr r1, =VICVectAddr
|
||||
ldr r0, =0x00
|
||||
str r0, [r1]
|
||||
|
||||
ldr r1, =VICIntSelect
|
||||
ldr r0, =0x00
|
||||
str r0, [r1]
|
||||
|
||||
/* setup stack */
|
||||
bl stack_setup
|
||||
|
||||
_rtthread_startup: .word rtthread_startup
|
||||
/* copy .data to SRAM */
|
||||
ldr r1, =_sidata /* .data start in image */
|
||||
ldr r2, =_edata /* .data end in image */
|
||||
ldr r3, =_sdata /* sram data start */
|
||||
data_loop:
|
||||
ldr r0, [r1, #0]
|
||||
str r0, [r3]
|
||||
|
||||
.equ USERMODE, 0x10
|
||||
.equ FIQMODE, 0x11
|
||||
.equ IRQMODE, 0x12
|
||||
.equ SVCMODE, 0x13
|
||||
.equ ABORTMODE, 0x17
|
||||
.equ UNDEFMODE, 0x1b
|
||||
.equ MODEMASK, 0x1f
|
||||
.equ NOINT, 0xc0
|
||||
add r1, r1, #4
|
||||
add r3, r3, #4
|
||||
|
||||
cmp r3, r2 /* check if data to clear */
|
||||
blo data_loop /* loop until done */
|
||||
|
||||
/* clear .bss */
|
||||
mov r0,#0 /* get a zero */
|
||||
ldr r1,=__bss_start /* bss start */
|
||||
ldr r2,=__bss_end /* bss end */
|
||||
|
||||
bss_loop:
|
||||
cmp r1,r2 /* check if data to clear */
|
||||
strlo r0,[r1],#4 /* clear 4 bytes */
|
||||
blo bss_loop /* loop until done */
|
||||
|
||||
/* call C++ constructors of global objects */
|
||||
ldr r0, =__ctors_start__
|
||||
ldr r1, =__ctors_end__
|
||||
|
||||
ctor_loop:
|
||||
cmp r0, r1
|
||||
beq ctor_end
|
||||
ldr r2, [r0], #4
|
||||
stmfd sp!, {r0-r1}
|
||||
mov lr, pc
|
||||
bx r2
|
||||
ldmfd sp!, {r0-r1}
|
||||
b ctor_loop
|
||||
ctor_end:
|
||||
|
||||
/* start RT-Thread Kernel */
|
||||
ldr pc, _rtthread_startup
|
||||
|
||||
_rtthread_startup:
|
||||
.word rtthread_startup
|
||||
|
||||
.equ USERMODE, 0x10
|
||||
.equ FIQMODE, 0x11
|
||||
.equ IRQMODE, 0x12
|
||||
.equ SVCMODE, 0x13
|
||||
.equ ABORTMODE, 0x17
|
||||
.equ UNDEFMODE, 0x1b
|
||||
.equ MODEMASK, 0x1f
|
||||
.equ NOINT, 0xc0
|
||||
|
||||
/* exception handlers */
|
||||
vector_undef: bl rt_hw_trap_udef
|
||||
vector_swi: bl rt_hw_trap_swi
|
||||
vector_pabt: bl rt_hw_trap_pabt
|
||||
vector_dabt: bl rt_hw_trap_dabt
|
||||
vector_resv: bl rt_hw_trap_resv
|
||||
vector_undef: bl rt_hw_trap_udef
|
||||
vector_swi: bl rt_hw_trap_swi
|
||||
vector_pabt: bl rt_hw_trap_pabt
|
||||
vector_dabt: bl rt_hw_trap_dabt
|
||||
vector_resv: bl rt_hw_trap_resv
|
||||
|
||||
.globl rt_interrupt_enter
|
||||
.globl rt_interrupt_leave
|
||||
.globl rt_thread_switch_interrput_flag
|
||||
.globl rt_interrupt_from_thread
|
||||
.globl rt_interrupt_to_thread
|
||||
vector_irq:
|
||||
stmfd sp!, {r0-r12,lr}
|
||||
bl rt_interrupt_enter
|
||||
bl rt_hw_trap_irq
|
||||
bl rt_interrupt_leave
|
||||
vector_irq:
|
||||
stmfd sp!, {r0-r12,lr}
|
||||
bl rt_interrupt_enter
|
||||
bl rt_hw_trap_irq
|
||||
bl rt_interrupt_leave
|
||||
|
||||
/* if rt_thread_switch_interrput_flag set, jump to _interrupt_thread_switch and don't return */
|
||||
ldr r0, =rt_thread_switch_interrput_flag
|
||||
ldr r1, [r0]
|
||||
cmp r1, #1
|
||||
beq _interrupt_thread_switch
|
||||
/* if rt_thread_switch_interrput_flag set,
|
||||
* jump to _interrupt_thread_switch and don't return
|
||||
*/
|
||||
ldr r0, =rt_thread_switch_interrput_flag
|
||||
ldr r1, [r0]
|
||||
cmp r1, #1
|
||||
beq _interrupt_thread_switch
|
||||
|
||||
ldmfd sp!, {r0-r12,lr}
|
||||
subs pc, lr, #4
|
||||
ldmfd sp!, {r0-r12,lr}
|
||||
subs pc, lr, #4
|
||||
|
||||
.align 5
|
||||
.align 5
|
||||
vector_fiq:
|
||||
stmfd sp!,{r0-r7,lr}
|
||||
bl rt_hw_trap_fiq
|
||||
ldmfd sp!,{r0-r7,lr}
|
||||
subs pc,lr,#4
|
||||
stmfd sp!,{r0-r7,lr}
|
||||
bl rt_hw_trap_fiq
|
||||
ldmfd sp!,{r0-r7,lr}
|
||||
subs pc,lr,#4
|
||||
|
||||
_interrupt_thread_switch:
|
||||
mov r1, #0 @ clear rt_thread_switch_interrput_flag
|
||||
str r1, [r0]
|
||||
mov r1, #0 /* clear rt_thread_switch_interrput_flag */
|
||||
str r1, [r0]
|
||||
|
||||
ldmfd sp!, {r0-r12,lr} @ reload saved registers
|
||||
stmfd sp!, {r0-r3} @ save r0-r3
|
||||
mov r1, sp
|
||||
add sp, sp, #16 @ restore sp
|
||||
sub r2, lr, #4 @ save old task's pc to r2
|
||||
ldmfd sp!, {r0-r12,lr} /* reload saved registers */
|
||||
stmfd sp!, {r0-r3} /* save r0-r3 */
|
||||
mov r1, sp
|
||||
add sp, sp, #16 /* restore sp */
|
||||
sub r2, lr, #4 /* save old task's pc to r2 */
|
||||
|
||||
mrs r3, spsr @ disable interrupt
|
||||
orr r0, r3, #NOINT
|
||||
msr spsr_c, r0
|
||||
mrs r3, spsr /* disable interrupt */
|
||||
orr r0, r3, #NOINT
|
||||
msr spsr_c, r0
|
||||
|
||||
ldr r0, =.+8 @ switch to interrupted task's stack
|
||||
movs pc, r0
|
||||
ldr r0, =.+8 /* switch to interrupted task's stack */
|
||||
movs pc, r0
|
||||
|
||||
stmfd sp!, {r2} @ push old task's pc
|
||||
stmfd sp!, {r4-r12,lr} @ push old task's lr,r12-r4
|
||||
mov r4, r1 @ Special optimised code below
|
||||
mov r5, r3
|
||||
ldmfd r4!, {r0-r3}
|
||||
stmfd sp!, {r0-r3} @ push old task's r3-r0
|
||||
stmfd sp!, {r5} @ push old task's psr
|
||||
mrs r4, spsr
|
||||
stmfd sp!, {r4} @ push old task's spsr
|
||||
stmfd sp!, {r2} /* push old task's pc */
|
||||
stmfd sp!, {r4-r12,lr} /* push old task's lr,r12-r4 */
|
||||
mov r4, r1 /* Special optimised code below */
|
||||
mov r5, r3
|
||||
ldmfd r4!, {r0-r3}
|
||||
stmfd sp!, {r0-r3} /* push old task's r3-r0 */
|
||||
stmfd sp!, {r5} /* push old task's psr */
|
||||
mrs r4, spsr
|
||||
stmfd sp!, {r4} /* push old task's spsr */
|
||||
|
||||
ldr r4, =rt_interrupt_from_thread
|
||||
ldr r5, [r4]
|
||||
str sp, [r5] @ store sp in preempted tasks's TCB
|
||||
ldr r4, =rt_interrupt_from_thread
|
||||
ldr r5, [r4]
|
||||
str sp, [r5] /* store sp in preempted tasks's TCB */
|
||||
|
||||
ldr r6, =rt_interrupt_to_thread
|
||||
ldr r6, [r6]
|
||||
ldr sp, [r6] @ get new task's stack pointer
|
||||
ldr r6, =rt_interrupt_to_thread
|
||||
ldr r6, [r6]
|
||||
ldr sp, [r6] /* get new task's stack pointer */
|
||||
|
||||
ldmfd sp!, {r4} @ pop new task's spsr
|
||||
msr SPSR_cxsf, r4
|
||||
ldmfd sp!, {r4} @ pop new task's psr
|
||||
msr CPSR_cxsf, r4
|
||||
ldmfd sp!, {r4} /* pop new task's spsr */
|
||||
msr SPSR_cxsf, r4
|
||||
ldmfd sp!, {r4} /* pop new task's psr */
|
||||
msr CPSR_cxsf, r4
|
||||
|
||||
ldmfd sp!, {r0-r12,lr,pc} @ pop new task's r0-r12,lr & pc
|
||||
ldmfd sp!, {r0-r12,lr,pc} /* pop new task's r0-r12,lr & pc */
|
||||
|
||||
/* each mode stack memory */
|
||||
stack_setup:
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #MODEMASK
|
||||
orr r1, r0, #UNDEFMODE|NOINT
|
||||
msr cpsr_cxsf, r1 @ undef mode
|
||||
ldr sp, =__UndStack_end
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #MODEMASK
|
||||
orr r1, r0, #UNDEFMODE|NOINT
|
||||
msr cpsr_cxsf, r1 /* undef mode */
|
||||
ldr sp, =UDF_STACK
|
||||
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #MODEMASK
|
||||
orr r1,r0,#ABORTMODE|NOINT
|
||||
msr cpsr_cxsf,r1 @ abort mode
|
||||
ldr sp,=__ABTStack_end
|
||||
orr r1,r0,#ABORTMODE|NOINT
|
||||
msr cpsr_cxsf,r1 /* abort mode */
|
||||
ldr sp, =ABT_STACK
|
||||
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #MODEMASK
|
||||
orr r1,r0,#IRQMODE|NOINT
|
||||
msr cpsr_cxsf,r1 @ IRQ mode
|
||||
ldr sp,=__IRQStack_end
|
||||
orr r1,r0,#IRQMODE|NOINT
|
||||
msr cpsr_cxsf,r1 /* IRQ mode */
|
||||
ldr sp, =IRQ_STACK
|
||||
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #MODEMASK
|
||||
orr r1,r0,#FIQMODE|NOINT
|
||||
msr cpsr_cxsf,r1 @ FIQ mode
|
||||
ldr sp,=__FIQStack_end
|
||||
orr r1,r0,#FIQMODE|NOINT
|
||||
msr cpsr_cxsf,r1 /* FIQ mode */
|
||||
ldr sp, =FIQ_STACK
|
||||
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #MODEMASK
|
||||
orr r1,r0,#SVCMODE|NOINT
|
||||
msr cpsr_cxsf,r1 @ SVC mode
|
||||
ldr sp,=__SVCStack_end
|
||||
|
||||
/* USER mode is not initialized. */
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #MODEMASK|0x80 //IRQ enable and FIQ disable
|
||||
orr r1,r0,#USERMODE
|
||||
msr cpsr_cxsf,r1 @ usr mode
|
||||
ldr sp,=__USRStack_end
|
||||
|
||||
ldr pc, _rtthread_startup
|
||||
bic r0,r0,#MODEMASK
|
||||
orr r1,r0,#SVCMODE|NOINT
|
||||
msr cpsr_cxsf,r1 /* SVC mode */
|
||||
ldr sp, =SVC_STACK
|
||||
|
||||
/* USER mode is not initialized. */
|
||||
mov pc,lr /* The LR register may be not valid for the mode changes.*/
|
||||
|
|
|
|||
|
|
@ -121,6 +121,8 @@ void rt_hw_trap_irq()
|
|||
rt_isr_handler_t isr_func;
|
||||
|
||||
isr_func = (rt_isr_handler_t) VICVectAddr;
|
||||
|
||||
/* fixme, how to get interrupt number */
|
||||
isr_func(0);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue