update stm32f10x

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1517 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/stm32f10x/Libraries/SConscript

@@ -5,6 +5,7 @@ from building import *
 # The set of source files associated with this SConscript file.
 src = Split("""
 CMSIS/CM3/CoreSupport/core_cm3.c
+CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
 STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c
 STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
 STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c
@@ -30,11 +31,30 @@ STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c
 STM32F10x_StdPeriph_Driver/src/misc.c
 """)
 
-path = [RTT_ROOT + '/bsp/stm3210/Libraries/STM32F10x_StdPeriph_Driver/inc', 
+# starupt scripts for each STM32 kind
-    RTT_ROOT + '/bsp/stm3210/Libraries/CMSIS/CM3/CoreSupport',
+startup_scripts = {}
-    RTT_ROOT + '/bsp/stm3210/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x']
+startup_scripts['STM32F10X_CL']     = 'startup_stm32f10x_cl.s'
+startup_scripts['STM32F10X_HD']     = 'startup_stm32f10x_hd.s'
+startup_scripts['STM32F10X_HD_VL']  = 'startup_stm32f10x_hd_vl.s'
+startup_scripts['STM32F10X_LD']     = 'startup_stm32f10x_ld.s'
+startup_scripts['STM32F10X_LD_VL']  = 'startup_stm32f10x_ld_vl.s'
+startup_scripts['STM32F10X_MD']     = 'startup_stm32f10x_md.s'
+startup_scripts['STM32F10X_MD_VL']  = 'startup_stm32f10x_md_vl.s'
+startup_scripts['STM32F10X_XL']	    = 'startup_stm32f10x_xl.s'
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+    src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/gcc_ride7/' + startup_scripts[rtconfig.STM32_TYPE]]
+elif rtconfig.CROSS_TOOL == 'keil':
+    src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/' + startup_scripts[rtconfig.STM32_TYPE]]
+elif rtconfig.CROSS_TOOL == 'iar':
+    src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/' + startup_scripts[rtconfig.STM32_TYPE]]
+
+path = [RTT_ROOT + '/bsp/stm32f10x/Libraries/STM32F10x_StdPeriph_Driver/inc', 
+    RTT_ROOT + '/bsp/stm32f10x/Libraries/CMSIS/CM3/CoreSupport',
+    RTT_ROOT + '/bsp/stm32f10x/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x']
 
 CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
-group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path)
+group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
 
 Return('group')

bsp/stm32f10x/SConscript

@@ -2,8 +2,8 @@ import rtconfig
 Import('RTT_ROOT')
 from building import *
 
-src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f10x_it.c', 'system_stm32f10x.c']
+src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f10x_it.c']
-src_drv = ['rtc.c', 'usart.c', 'led.c']
+src_drv = ['rtc.c', 'usart.c', 'serial.c', 'led.c']
 
 if GetDepend('RT_USING_DFS'):
 	if rtconfig.STM32_TYPE == 'STM32F10X_HD':
@@ -18,8 +18,8 @@ if GetDepend('RT_USING_LWIP'):
 		src_drv += ['enc28j60.c']
 
 src = src_bsp + src_drv
-CPPPATH = [RTT_ROOT + '/bsp/stm3210']
+CPPPATH = [RTT_ROOT + '/bsp/stm32f10x']
-CPPDEFINES = ['USE_STDPERIPH_DRIVER', rtconfig.STM32_TYPE]
+CPPDEFINES = []
 group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
 
 Return('group')

bsp/stm32f10x/SConstruct

@@ -26,7 +26,7 @@ Export('rtconfig')
 objs = PrepareBuilding(env, RTT_ROOT)
 
 # STM32 firemare library building script
-objs = objs + SConscript(RTT_ROOT + '/bsp/stm3210/Libraries/SConscript', variant_dir='build/bsp/Libraries', duplicate=0)
+objs = objs + SConscript(RTT_ROOT + '/bsp/stm32f10x/Libraries/SConscript', variant_dir='build/bsp/Libraries', duplicate=0)
 
 # build program 
 env.Program(TARGET, objs)

bsp/stm32f10x/project.Uv2

@@ -15,9 +15,9 @@ File 1,1,<.\application.c><application.c>
 File 1,1,<.\startup.c><startup.c>
 File 1,1,<.\board.c><board.c>
 File 1,1,<.\stm32f10x_it.c><stm32f10x_it.c>
-File 1,1,<.\system_stm32f10x.c><system_stm32f10x.c>
 File 1,1,<.\rtc.c><rtc.c>
 File 1,1,<.\usart.c><usart.c>
+File 1,1,<.\serial.c><serial.c>
 File 1,1,<.\led.c><led.c>
 File 1,1,<.\sdcard.c><sdcard.c>
 File 1,1,<.\enc28j60.c><enc28j60.c>
@@ -36,14 +36,8 @@ File 2,1,<..\..\src\scheduler.c><scheduler.c>
 File 2,1,<..\..\src\slab.c><slab.c>
 File 2,1,<..\..\src\thread.c><thread.c>
 File 2,1,<..\..\src\timer.c><timer.c>
-File 3,1,<..\..\libcpu\arm\stm32\cpu.c><cpu.c>
+File 3,1,<..\..\libcpu\arm\stm32\cpuport.c><cpuport.c>
-File 3,1,<..\..\libcpu\arm\stm32\fault.c><fault.c>
-File 3,1,<..\..\libcpu\arm\stm32\interrupt.c><interrupt.c>
-File 3,1,<..\..\libcpu\arm\stm32\serial.c><serial.c>
-File 3,1,<..\..\libcpu\arm\stm32\stack.c><stack.c>
 File 3,2,<..\..\libcpu\arm\stm32\context_rvds.S><context_rvds.S>
-File 3,2,<..\..\libcpu\arm\stm32\fault_rvds.S><fault_rvds.S>
-File 3,2,<..\..\libcpu\arm\stm32\start_rvds.S><start_rvds.S>
 File 3,1,<..\..\libcpu\arm\common\backtrace.c><backtrace.c>
 File 3,1,<..\..\libcpu\arm\common\div0.c><div0.c>
 File 3,1,<..\..\libcpu\arm\common\showmem.c><showmem.c>
@@ -97,30 +91,12 @@ File 6,1,<..\..\components\net\lwip\src\core\ipv4\inet_chksum.c><inet_chksum.c>
 File 6,1,<..\..\components\net\lwip\src\core\ipv4\ip.c><ip.c>
 File 6,1,<..\..\components\net\lwip\src\core\ipv4\ip_addr.c><ip_addr.c>
 File 6,1,<..\..\components\net\lwip\src\core\ipv4\ip_frag.c><ip_frag.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\asn1_dec.c><asn1_dec.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\asn1_enc.c><asn1_enc.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\mib2.c><mib2.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\mib_structs.c><mib_structs.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\msg_in.c><msg_in.c>
-File 6,1,<..\..\components\net\lwip\src\core\snmp\msg_out.c><msg_out.c>
 File 6,1,<..\..\components\net\lwip\src\netif\etharp.c><etharp.c>
 File 6,1,<..\..\components\net\lwip\src\netif\ethernetif.c><ethernetif.c>
 File 6,1,<..\..\components\net\lwip\src\netif\loopif.c><loopif.c>
 File 6,1,<..\..\components\net\lwip\src\netif\slipif.c><slipif.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\auth.c><auth.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\chap.c><chap.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\chpms.c><chpms.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\fsm.c><fsm.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\ipcp.c><ipcp.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\lcp.c><lcp.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\magic.c><magic.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\md5.c><md5.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\pap.c><pap.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\ppp.c><ppp.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\ppp_oe.c><ppp_oe.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\randm.c><randm.c>
-File 6,1,<..\..\components\net\lwip\src\netif\ppp\vj.c><vj.c>
 File 7,1,<Libraries\CMSIS\CM3\CoreSupport\core_cm3.c><core_cm3.c>
+File 7,1,<Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c><system_stm32f10x.c>
 File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c><stm32f10x_crc.c>
 File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c><stm32f10x_rcc.c>
 File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c><stm32f10x_wwdg.c>
@@ -144,6 +120,7 @@ File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c><stm32f10x_dm
 File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c><stm32f10x_can.c>
 File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c><stm32f10x_cec.c>
 File 7,1,<Libraries\STM32F10x_StdPeriph_Driver\src\misc.c><misc.c>
+File 7,2,<Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_hd.s><startup_stm32f10x_hd.s>
 
 
 Options 1,0,0  // Target 'RT-Thread STM32'
@@ -178,7 +155,7 @@ Options 1,0,0  // Target 'RT-Thread STM32'
  GenHex=0
  Debug=1
  Browse=0
- LstDir (.\obj\)
+ LstDir (.\)
  HexSel=1
  MG32K=0
  TGMORE=0
@@ -204,7 +181,7 @@ Options 1,0,0  // Target 'RT-Thread STM32'
  ADSCMISC ()
  ADSCDEFN (STM32F10X_HD, USE_STDPERIPH_DRIVER)
  ADSCUDEF ()
- ADSCINCD (Libraries\STM32F10x_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\CoreSupport;..\..\components\dfs;..\..\components\finsh;..\..\components\net\lwip\src\include;.;..\..\components\net\lwip\src\include\ipv4;..\..\include;..\..\components\net\lwip\src\arch\include;..\..\components\dfs\include;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\components\net\lwip\src\netif\ppp;..\..\libcpu\arm\stm32;..\..\components\net\lwip\src\include\netif;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x)
+ ADSCINCD (Libraries\STM32F10x_StdPeriph_Driver\inc;Libraries\CMSIS\CM3\CoreSupport;..\..\components\dfs;..\..\components\finsh;..\..\components\net\lwip\src\include;.;..\..\components\net\lwip\src\include\ipv4;..\..\include;..\..\components\net\lwip\src\arch\include;..\..\components\dfs\include;..\..\components\net\lwip\src;..\..\libcpu\arm\common;..\..\libcpu\arm\stm32;..\..\components\net\lwip\src\include\netif;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x)
  ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
  ADSAMISC ()
  ADSADEFN ()
@@ -229,7 +206,7 @@ Options 1,0,0  // Target 'RT-Thread STM32'
  ADSLDIF ()
  ADSLDDW ()
   OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103ZE)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103ZE)
-  OPTDBG 49150,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
+  OPTDBG 49149,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
  FLASH1 { 1,0,0,0,1,0,0,0,6,16,0,0,0,0,0,0,0,0,0,0 }
  FLASH2 (Segger\JL2CM3.dll)
  FLASH3 ("" ())

bsp/stm32f10x/serial.c

@@ -0,0 +1,418 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-02-05     Bernard      first version
+ * 2009-10-25     Bernard      fix rt_serial_read bug when there is no data
+ *                             in the buffer.
+ * 2010-03-29     Bernard      cleanup code.
+ */
+
+#include "serial.h"
+#include <stm32f10x_dma.h>
+#include <stm32f10x_usart.h>
+
+static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
+	rt_uint32_t address, rt_uint32_t size);
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+	struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data;
+
+	if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+	{
+		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+		{
+			rt_memset(uart->int_rx->rx_buffer, 0,
+				sizeof(uart->int_rx->rx_buffer));
+			uart->int_rx->read_index = 0;
+			uart->int_rx->save_index = 0;
+		}
+
+		if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+		{
+			RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL);
+			uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
+
+			/* init data node memory pool */
+			rt_mp_init(&(uart->dma_tx->data_node_mp), "dn",
+				uart->dma_tx->data_node_mem_pool,
+				sizeof(uart->dma_tx->data_node_mem_pool),
+				sizeof(struct stm32_serial_data_node));
+		}
+
+		/* Enable USART */
+		USART_Cmd(uart->uart_device, ENABLE);
+
+		dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	rt_err_t err_code;
+	struct stm32_serial_device* uart;
+
+	ptr = buffer;
+	err_code = RT_EOK;
+	uart = (struct stm32_serial_device*)dev->user_data;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* interrupt mode Rx */
+		while (size)
+		{
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			if (uart->int_rx->read_index != uart->int_rx->save_index)
+			{
+				/* read a character */
+				*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+				size--;
+
+				/* move to next position */
+				uart->int_rx->read_index ++;
+				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+					uart->int_rx->read_index = 0;
+			}
+			else
+			{
+				/* set error code */
+				err_code = -RT_EEMPTY;
+
+				/* enable interrupt */
+				rt_hw_interrupt_enable(level);
+				break;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+	}
+	else
+	{
+		/* polling mode */
+		while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+		{
+			while (uart->uart_device->SR & USART_FLAG_RXNE)
+			{
+				*ptr = uart->uart_device->DR & 0xff;
+				ptr ++;
+			}
+		}
+	}
+
+	/* set error code */
+	rt_set_errno(err_code);
+	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static void rt_serial_enable_dma(DMA_Channel_TypeDef* dma_channel,
+	rt_uint32_t address, rt_uint32_t size)
+{
+	RT_ASSERT(dma_channel != RT_NULL);
+
+	/* disable DMA */
+	DMA_Cmd(dma_channel, DISABLE);
+
+	/* set buffer address */
+	dma_channel->CMAR = address;
+	/* set size */
+	dma_channel->CNDTR = size;
+
+	/* enable DMA */
+	DMA_Cmd(dma_channel, ENABLE);
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	rt_err_t err_code;
+	struct stm32_serial_device* uart;
+
+	err_code = RT_EOK;
+	ptr = (rt_uint8_t*)buffer;
+	uart = (struct stm32_serial_device*)dev->user_data;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+	{
+		/* interrupt mode Tx, does not support */
+		RT_ASSERT(0);
+	}
+	else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+	{
+		/* DMA mode Tx */
+
+		/* allocate a data node */
+		struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*)
+			rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER);
+		if (data_node == RT_NULL)
+		{
+			/* set error code */
+			err_code = -RT_ENOMEM;
+		}
+		else
+		{
+			rt_uint32_t level;
+
+			/* fill data node */
+			data_node->data_ptr 	= ptr;
+			data_node->data_size 	= size;
+
+			/* insert to data link */
+			data_node->next = RT_NULL;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			data_node->prev = uart->dma_tx->list_tail;
+			if (uart->dma_tx->list_tail != RT_NULL)
+				uart->dma_tx->list_tail->next = data_node;
+			uart->dma_tx->list_tail = data_node;
+
+			if (uart->dma_tx->list_head == RT_NULL)
+			{
+				/* start DMA to transmit data */
+				uart->dma_tx->list_head = data_node;
+
+				/* Enable DMA Channel */
+				rt_serial_enable_dma(uart->dma_tx->dma_channel,
+					(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+					uart->dma_tx->list_head->data_size);
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+	}
+	else
+	{
+		/* polling mode */
+		if (dev->flag & RT_DEVICE_FLAG_STREAM)
+		{
+			/* stream mode */
+			while (size)
+			{
+				if (*ptr == '\n')
+				{
+					while (!(uart->uart_device->SR & USART_FLAG_TXE));
+					uart->uart_device->DR = '\r';
+				}
+
+				while (!(uart->uart_device->SR & USART_FLAG_TXE));
+				uart->uart_device->DR = (*ptr & 0x1FF);
+
+				++ptr; --size;
+			}
+		}
+		else
+		{
+			/* write data directly */
+			while (size)
+			{
+				while (!(uart->uart_device->SR & USART_FLAG_TXE));
+				uart->uart_device->DR = (*ptr & 0x1FF);
+
+				++ptr; --size;
+			}
+		}
+	}
+
+	/* set error code */
+	rt_set_errno(err_code);
+
+	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	struct stm32_serial_device* uart;
+
+	RT_ASSERT(dev != RT_NULL);
+
+	uart = (struct stm32_serial_device*)dev->user_data;
+	switch (cmd)
+	{
+	case RT_DEVICE_CTRL_SUSPEND:
+		/* suspend device */
+		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+		USART_Cmd(uart->uart_device, DISABLE);
+		break;
+
+	case RT_DEVICE_CTRL_RESUME:
+		/* resume device */
+		dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+		USART_Cmd(uart->uart_device, ENABLE);
+		break;
+	}
+
+	return RT_EOK;
+}
+
+/*
+ * serial register for STM32
+ * support STM32F103VB and STM32F103ZE
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
+{
+	RT_ASSERT(device != RT_NULL);
+
+	if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
+		(flag & RT_DEVICE_FLAG_INT_TX))
+	{
+		RT_ASSERT(0);
+	}
+
+	device->type 		= RT_Device_Class_Char;
+	device->rx_indicate = RT_NULL;
+	device->tx_complete = RT_NULL;
+	device->init 		= rt_serial_init;
+	device->open		= rt_serial_open;
+	device->close		= rt_serial_close;
+	device->read 		= rt_serial_read;
+	device->write 		= rt_serial_write;
+	device->control 	= rt_serial_control;
+	device->user_data	= serial;
+
+	/* register a character device */
+	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+	struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+
+	if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
+	{
+		/* interrupt mode receive */
+		RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+		/* save on rx buffer */
+		while (uart->uart_device->SR & USART_FLAG_RXNE)
+		{
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			/* save character */
+			uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff;
+			uart->int_rx->save_index ++;
+			if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+				uart->int_rx->save_index = 0;
+
+			/* if the next position is read index, discard this 'read char' */
+			if (uart->int_rx->save_index == uart->int_rx->read_index)
+			{
+				uart->int_rx->read_index ++;
+				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+					uart->int_rx->read_index = 0;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+
+		/* clear interrupt */
+		USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
+
+		/* invoke callback */
+		if (device->rx_indicate != RT_NULL)
+		{
+			rt_size_t rx_length;
+
+			/* get rx length */
+			rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+				UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+				uart->int_rx->save_index - uart->int_rx->read_index;
+
+			device->rx_indicate(device, rx_length);
+		}
+	}
+
+	if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
+	{
+		/* clear interrupt */
+		USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
+	}
+}
+
+/*
+ * ISR for DMA mode Tx
+ */
+void rt_hw_serial_dma_tx_isr(rt_device_t device)
+{
+	rt_uint32_t level;
+	struct stm32_serial_data_node* data_node;
+	struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+
+	/* DMA mode receive */
+	RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
+
+	/* get the first data node */
+	data_node = uart->dma_tx->list_head;
+	RT_ASSERT(data_node != RT_NULL);
+
+	/* invoke call to notify tx complete */
+	if (device->tx_complete != RT_NULL)
+		device->tx_complete(device, data_node->data_ptr);
+
+	/* disable interrupt */
+	level = rt_hw_interrupt_disable();
+
+	/* remove list head */
+	uart->dma_tx->list_head = data_node->next;
+	if (uart->dma_tx->list_head == RT_NULL) /* data link empty */
+		uart->dma_tx->list_tail = RT_NULL;
+
+	/* enable interrupt */
+	rt_hw_interrupt_enable(level);
+
+	/* release data node memory */
+	rt_mp_free(data_node);
+
+	if (uart->dma_tx->list_head != RT_NULL)
+	{
+		/* transmit next data node */
+		rt_serial_enable_dma(uart->dma_tx->dma_channel,
+			(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+			uart->dma_tx->list_head->data_size);
+	}
+	else
+	{
+		/* no data to be transmitted, disable DMA */
+		DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
+	}
+}
+
+/*@}*/

bsp/stm32f10x/serial.h

@@ -0,0 +1,70 @@
+/*
+ * File      : serial.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first version
+ * 2010-03-29     Bernard      remove interrupt tx and DMA rx mode.
+ */
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+/* STM32F10x library definitions */
+#include <stm32f10x.h>
+
+#define UART_RX_BUFFER_SIZE		64
+#define UART_TX_DMA_NODE_SIZE	4
+
+/* data node for Tx Mode */
+struct stm32_serial_data_node
+{
+	rt_uint8_t *data_ptr;
+	rt_size_t  data_size;
+	struct stm32_serial_data_node *next, *prev;
+};
+struct stm32_serial_dma_tx
+{
+	/* DMA Channel */
+	DMA_Channel_TypeDef* dma_channel;
+
+	/* data list head and tail */
+	struct stm32_serial_data_node *list_head, *list_tail;
+
+	/* data node memory pool */
+	struct rt_mempool data_node_mp;
+	rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE *
+		(sizeof(struct stm32_serial_data_node) + sizeof(void*))];
+};
+
+struct stm32_serial_int_rx
+{
+	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+	rt_uint32_t read_index, save_index;
+};
+
+struct stm32_serial_device
+{
+	USART_TypeDef* uart_device;
+
+	/* rx structure */
+	struct stm32_serial_int_rx* int_rx;
+
+	/* tx structure */
+	struct stm32_serial_dma_tx* dma_tx;
+};
+
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial);
+
+void rt_hw_serial_isr(rt_device_t device);
+void rt_hw_serial_dma_tx_isr(rt_device_t device);
+
+#endif

bsp/stm32f10x/stm32f10x_it.c

@@ -1,14 +1,14 @@
 /**
   ******************************************************************************
-  * @file    Project/Template/stm32f10x_it.c 
+  * @file    Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c
   * @author  MCD Application Team
-  * @version V3.1.0
+  * @version V3.5.0
-  * @date    06/19/2009
+  * @date    08-April-2011
   * @brief   Main Interrupt Service Routines.
-  *          This file provides template for all exceptions handler and 
+  *          This file provides template for all exceptions handler and
   *          peripherals interrupt service routine.
   ******************************************************************************
-  * @copy
+  * @attention
   *
   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
@@ -17,8 +17,9 @@
   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
   *
-  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
-  */ 
+  ******************************************************************************
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f10x_it.h"
@@ -49,19 +50,6 @@ void NMI_Handler(void)
 {
 }
 
-/**
-  * @brief  This function handles Hard Fault exception.
-  * @param  None
-  * @retval None
-  */
-void HardFault_Handler(void)
-{
-  /* Go to infinite loop when Hard Fault exception occurs */
-  while (1)
-  {
-  }
-}
-
 /**
   * @brief  This function handles Memory Manage exception.
   * @param  None
@@ -119,6 +107,12 @@ void DebugMon_Handler(void)
 {
 }
 
+void SysTick_Handler(void)
+{
+    extern void rt_hw_timer_handler(void);
+    rt_hw_timer_handler();
+}
+
 /******************************************************************************/
 /*                 STM32F10x Peripherals Interrupt Handlers                   */
 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
@@ -168,7 +162,7 @@ void USART1_IRQHandler(void)
 #ifdef RT_USING_UART1
     extern struct rt_device uart1_device;
 	extern void rt_hw_serial_isr(struct rt_device *device);
-	
+
     /* enter interrupt */
     rt_interrupt_enter();
 
@@ -260,10 +254,10 @@ void SDIO_IRQHandler(void)
 void ETH_IRQHandler(void)
 {
 	extern void rt_hw_stm32_eth_isr(void);
-	
+
     /* enter interrupt */
     rt_interrupt_enter();
-	
+
 	rt_hw_stm32_eth_isr();
 
     /* leave interrupt */
@@ -324,7 +318,7 @@ void EXTI9_5_IRQHandler(void)
 
 /**
   * @}
-  */ 
+  */
 
 
 /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/