[bsp] added Ethernet driver and lwip in stm32f429-apollo board
* use uart1 as default console device
* add pcf8574 support(a general-purpose remote I/O expansion chip)
This commit is contained in:
tanek liang
parent
269a7683b5
commit
a157b25f55
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@ -18,7 +18,7 @@ drv_mpu.c
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# add Ethernet drivers.
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if GetDepend('RT_USING_LWIP'):
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src += ['drv_eth.c']
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src += ['drv_eth.c', 'drv_iic.c', 'drv_pcf8574.c']
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# add gpio drivers.
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if GetDepend('RT_USING_PIN'):
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@ -61,7 +61,7 @@ extern int __bss_end;
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// <o> Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
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// <i>Default: 1
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#define STM32_CONSOLE_USART 2
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#define STM32_CONSOLE_USART 1
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void rt_hw_board_init(void);
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@ -0,0 +1,596 @@
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2017-06-08 tanek first implementation
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*/
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#include <rtthread.h>
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#include <netif/ethernetif.h>
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#include "lwipopts.h"
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#include "board.h"
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#include "drv_pcf8574.h"
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#include <rtdevice.h>
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#include <finsh.h>
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/* debug option */
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//#define DEBUG
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//#define ETH_RX_DUMP
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//#define ETH_TX_DUMP
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#ifdef DEBUG
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#define STM32_ETH_PRINTF rt_kprintf
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#else
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#define STM32_ETH_PRINTF(...)
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#endif
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/*ÍøÂçÒý½ÅÉèÖà RMII½Ó¿Ú
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ETH_MDIO -------------------------> PA2
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ETH_MDC --------------------------> PC1
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ETH_RMII_REF_CLK------------------> PA1
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ETH_RMII_CRS_DV ------------------> PA7
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ETH_RMII_RXD0 --------------------> PC4
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ETH_RMII_RXD1 --------------------> PC5
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ETH_RMII_TX_EN -------------------> PB11
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ETH_RMII_TXD0 --------------------> PG13
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ETH_RMII_TXD1 --------------------> PG14
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ETH_RESET-------------------------> PCF8574À©Õ¹IO
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*/
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#define ETH_MDIO_PORN GPIOA
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#define ETH_MDIO_PIN GPIO_PIN_2
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#define ETH_MDC_PORN GPIOC
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#define ETH_MDC_PIN GPIO_PIN_1
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#define ETH_RMII_REF_CLK_PORN GPIOA
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#define ETH_RMII_REF_CLK_PIN GPIO_PIN_1
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#define ETH_RMII_CRS_DV_PORN GPIOA
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#define ETH_RMII_CRS_DV_PIN GPIO_PIN_7
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#define ETH_RMII_RXD0_PORN GPIOC
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#define ETH_RMII_RXD0_PIN GPIO_PIN_4
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#define ETH_RMII_RXD1_PORN GPIOC
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#define ETH_RMII_RXD1_PIN GPIO_PIN_5
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#define ETH_RMII_TX_EN_PORN GPIOB
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#define ETH_RMII_TX_EN_PIN GPIO_PIN_11
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#define ETH_RMII_TXD0_PORN GPIOG
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#define ETH_RMII_TXD0_PIN GPIO_PIN_13
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#define ETH_RMII_TXD1_PORN GPIOG
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#define ETH_RMII_TXD1_PIN GPIO_PIN_14
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#define LAN8742A_PHY_ADDRESS 0x00
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#define MAX_ADDR_LEN 6
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struct rt_stm32_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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/* interface address info. */
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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uint32_t ETH_Speed; /*!< @ref ETH_Speed */
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uint32_t ETH_Mode; /*!< @ref ETH_Duplex_Mode */
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};
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static ETH_DMADescTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB];
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static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE];
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static rt_bool_t tx_is_waiting = RT_FALSE;
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static ETH_HandleTypeDef EthHandle;
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static struct rt_stm32_eth stm32_eth_device;
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static struct rt_semaphore tx_wait;
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/* interrupt service routine */
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void ETH_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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HAL_ETH_IRQHandler(&EthHandle);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
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{
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if (tx_is_waiting == RT_TRUE)
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{
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tx_is_waiting = RT_FALSE;
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rt_sem_release(&tx_wait);
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}
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}
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void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
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{
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rt_err_t result;
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result = eth_device_ready(&(stm32_eth_device.parent));
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if( result != RT_EOK )
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rt_kprintf("RX err =%d\n", result );
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}
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void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
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{
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rt_kprintf("eth err\n");
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}
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static void phy_pin_reset(void)
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{
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rt_base_t level;
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extern void delay_ms(rt_uint32_t nms);
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level = rt_hw_interrupt_disable();
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rt_pcf8574_write_bit(ETH_RESET_IO, 1);
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delay_ms(100);
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rt_pcf8574_write_bit(ETH_RESET_IO, 0);
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delay_ms(100);
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rt_hw_interrupt_enable(level);
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}
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#ifdef DEBUG
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FINSH_FUNCTION_EXPORT(phy_pin_reset, phy hardware reset);
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#endif
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/* initialize the interface */
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static rt_err_t rt_stm32_eth_init(rt_device_t dev)
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{
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STM32_ETH_PRINTF("rt_stm32_eth_init...\n");
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__HAL_RCC_ETH_CLK_ENABLE();
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rt_pcf8574_init();
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phy_pin_reset();
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/* ETHERNET Configuration --------------------------------------------------*/
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EthHandle.Instance = ETH;
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EthHandle.Init.MACAddr = (rt_uint8_t*)&stm32_eth_device.dev_addr[0];
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EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
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EthHandle.Init.Speed = ETH_SPEED_100M;
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EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
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EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
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EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
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EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
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//EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
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EthHandle.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
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HAL_ETH_DeInit(&EthHandle);
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/* configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */
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if (HAL_ETH_Init(&EthHandle) == HAL_OK)
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{
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STM32_ETH_PRINTF("eth hardware init sucess...\n");
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}
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else
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{
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STM32_ETH_PRINTF("eth hardware init faild...\n");
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}
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/* Initialize Tx Descriptors list: Chain Mode */
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HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
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/* Initialize Rx Descriptors list: Chain Mode */
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HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB);
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/* Enable MAC and DMA transmission and reception */
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if (HAL_ETH_Start(&EthHandle) == HAL_OK)
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{
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STM32_ETH_PRINTF("eth hardware start success...\n");
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}
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else
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{
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STM32_ETH_PRINTF("eth hardware start faild...\n");
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}
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//phy_monitor_thread_entry(NULL);
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return RT_EOK;
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}
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static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
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{
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STM32_ETH_PRINTF("rt_stm32_eth_open...\n");
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return RT_EOK;
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}
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static rt_err_t rt_stm32_eth_close(rt_device_t dev)
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{
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STM32_ETH_PRINTF("rt_stm32_eth_close...\n");
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return RT_EOK;
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}
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static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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STM32_ETH_PRINTF("rt_stm32_eth_read...\n");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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STM32_ETH_PRINTF("rt_stm32_eth_write...\n");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t rt_stm32_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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{
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STM32_ETH_PRINTF("rt_stm32_eth_control...\n");
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switch(cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
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else return -RT_ERROR;
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/* ethernet device interface */
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/* transmit packet. */
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rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p)
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{
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rt_err_t ret = RT_ERROR;
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HAL_StatusTypeDef state;
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struct pbuf *q;
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uint8_t *buffer = (uint8_t *)(EthHandle.TxDesc->Buffer1Addr);
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__IO ETH_DMADescTypeDef *DmaTxDesc;
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uint32_t framelength = 0;
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uint32_t bufferoffset = 0;
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uint32_t byteslefttocopy = 0;
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uint32_t payloadoffset = 0;
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DmaTxDesc = EthHandle.TxDesc;
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bufferoffset = 0;
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STM32_ETH_PRINTF("rt_stm32_eth_tx...\n");
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/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
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while ((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
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{
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rt_err_t result;
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rt_uint32_t level;
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level = rt_hw_interrupt_disable();
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tx_is_waiting = RT_TRUE;
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rt_hw_interrupt_enable(level);
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/* it's own bit set, wait it */
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result = rt_sem_take(&tx_wait, RT_WAITING_FOREVER);
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if (result == RT_EOK) break;
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if (result == -RT_ERROR) return -RT_ERROR;
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}
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/* copy frame from pbufs to driver buffers */
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for(q = p; q != NULL; q = q->next)
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{
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/* Is this buffer available? If not, goto error */
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if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
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{
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STM32_ETH_PRINTF("buffer not valid ...\n");
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ret = ERR_USE;
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goto error;
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}
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STM32_ETH_PRINTF("copy one frame\n");
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/* Get bytes in current lwIP buffer */
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byteslefttocopy = q->len;
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payloadoffset = 0;
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/* Check if the length of data to copy is bigger than Tx buffer size*/
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while( (byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE )
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{
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/* Copy data to Tx buffer*/
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memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset) );
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/* Point to next descriptor */
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DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
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/* Check if the buffer is available */
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if((DmaTxDesc->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
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{
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STM32_ETH_PRINTF("dmatxdesc buffer not valid ...\n");
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ret = ERR_USE;
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goto error;
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}
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buffer = (uint8_t *)(DmaTxDesc->Buffer1Addr);
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byteslefttocopy = byteslefttocopy - (ETH_TX_BUF_SIZE - bufferoffset);
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payloadoffset = payloadoffset + (ETH_TX_BUF_SIZE - bufferoffset);
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framelength = framelength + (ETH_TX_BUF_SIZE - bufferoffset);
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bufferoffset = 0;
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}
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/* Copy the remaining bytes */
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memcpy( (uint8_t*)((uint8_t*)buffer + bufferoffset), (uint8_t*)((uint8_t*)q->payload + payloadoffset), byteslefttocopy );
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bufferoffset = bufferoffset + byteslefttocopy;
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framelength = framelength + byteslefttocopy;
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}
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#ifdef ETH_TX_DUMP
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{
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rt_uint32_t i;
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rt_uint8_t *ptr = buffer;
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STM32_ETH_PRINTF("tx_dump, len:%d\r\n", p->tot_len);
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for(i=0; i<p->tot_len; i++)
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{
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STM32_ETH_PRINTF("%02x ",*ptr);
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ptr++;
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if(((i+1)%8) == 0)
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{
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STM32_ETH_PRINTF(" ");
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}
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if(((i+1)%16) == 0)
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{
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STM32_ETH_PRINTF("\r\n");
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}
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}
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STM32_ETH_PRINTF("\r\ndump done!\r\n");
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}
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#endif
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/* Prepare transmit descriptors to give to DMA */
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STM32_ETH_PRINTF("transmit frame, length: %d\n", framelength);
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state = HAL_ETH_TransmitFrame(&EthHandle, framelength);
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if (state != HAL_OK)
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{
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STM32_ETH_PRINTF("eth transmit frame faild: %d\n", state);
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}
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ret = ERR_OK;
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error:
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/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
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if ((EthHandle.Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET)
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{
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/* Clear TUS ETHERNET DMA flag */
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EthHandle.Instance->DMASR = ETH_DMASR_TUS;
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/* Resume DMA transmission*/
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EthHandle.Instance->DMATPDR = 0;
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}
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return ret;
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}
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/* reception packet. */
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struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
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{
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struct pbuf *p = NULL;
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struct pbuf *q = NULL;
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HAL_StatusTypeDef state;
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uint16_t len = 0;
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uint8_t *buffer;
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__IO ETH_DMADescTypeDef *dmarxdesc;
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uint32_t bufferoffset = 0;
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uint32_t payloadoffset = 0;
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uint32_t byteslefttocopy = 0;
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uint32_t i=0;
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STM32_ETH_PRINTF("rt_stm32_eth_rx\n");
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/* Get received frame */
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state = HAL_ETH_GetReceivedFrame_IT(&EthHandle);
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if (state != HAL_OK)
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{
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STM32_ETH_PRINTF("receive frame faild\n");
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return NULL;
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}
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/* Obtain the size of the packet and put it into the "len" variable. */
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len = EthHandle.RxFrameInfos.length;
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buffer = (uint8_t *)EthHandle.RxFrameInfos.buffer;
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STM32_ETH_PRINTF("receive frame len : %d\n", len);
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if (len > 0)
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{
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/* We allocate a pbuf chain of pbufs from the Lwip buffer pool */
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p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
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}
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#ifdef ETH_RX_DUMP
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{
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rt_uint32_t i;
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rt_uint8_t *ptr = buffer;
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STM32_ETH_PRINTF("rx_dump, len:%d\r\n", p->tot_len);
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for (i = 0; i < len; i++)
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{
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STM32_ETH_PRINTF("%02x ", *ptr);
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ptr++;
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if (((i + 1) % 8) == 0)
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{
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STM32_ETH_PRINTF(" ");
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}
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if (((i + 1) % 16) == 0)
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{
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STM32_ETH_PRINTF("\r\n");
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}
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}
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STM32_ETH_PRINTF("\r\ndump done!\r\n");
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}
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#endif
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if (p != NULL)
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{
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dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
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bufferoffset = 0;
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for(q = p; q != NULL; q = q->next)
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{
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byteslefttocopy = q->len;
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payloadoffset = 0;
|
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|
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/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/
|
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while( (byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE )
|
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{
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/* Copy data to pbuf */
|
||||
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
|
||||
|
||||
/* Point to next descriptor */
|
||||
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
|
||||
buffer = (uint8_t *)(dmarxdesc->Buffer1Addr);
|
||||
|
||||
byteslefttocopy = byteslefttocopy - (ETH_RX_BUF_SIZE - bufferoffset);
|
||||
payloadoffset = payloadoffset + (ETH_RX_BUF_SIZE - bufferoffset);
|
||||
bufferoffset = 0;
|
||||
}
|
||||
/* Copy remaining data in pbuf */
|
||||
memcpy( (uint8_t*)((uint8_t*)q->payload + payloadoffset), (uint8_t*)((uint8_t*)buffer + bufferoffset), byteslefttocopy);
|
||||
bufferoffset = bufferoffset + byteslefttocopy;
|
||||
}
|
||||
}
|
||||
|
||||
/* Release descriptors to DMA */
|
||||
/* Point to first descriptor */
|
||||
dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
|
||||
/* Set Own bit in Rx descriptors: gives the buffers back to DMA */
|
||||
for (i=0; i< EthHandle.RxFrameInfos.SegCount; i++)
|
||||
{
|
||||
dmarxdesc->Status |= ETH_DMARXDESC_OWN;
|
||||
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
|
||||
}
|
||||
|
||||
/* Clear Segment_Count */
|
||||
EthHandle.RxFrameInfos.SegCount =0;
|
||||
|
||||
/* When Rx Buffer unavailable flag is set: clear it and resume reception */
|
||||
if ((EthHandle.Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)
|
||||
{
|
||||
/* Clear RBUS ETHERNET DMA flag */
|
||||
EthHandle.Instance->DMASR = ETH_DMASR_RBUS;
|
||||
/* Resume DMA reception */
|
||||
EthHandle.Instance->DMARPDR = 0;
|
||||
}
|
||||
|
||||
return p;
|
||||
}
|
||||
|
||||
static void NVIC_Configuration(void)
|
||||
{
|
||||
/* Enable the Ethernet global Interrupt */
|
||||
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
}
|
||||
|
||||
/*
|
||||
* GPIO Configuration for ETH
|
||||
*/
|
||||
static void GPIO_Configuration(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
|
||||
STM32_ETH_PRINTF("GPIO_Configuration...\n");
|
||||
|
||||
/* Enable SYSCFG clock */
|
||||
__HAL_RCC_ETH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
|
||||
GPIO_InitStructure.Pull = GPIO_NOPULL;
|
||||
|
||||
GPIO_InitStructure.Pin = ETH_MDIO_PIN;
|
||||
HAL_GPIO_Init(ETH_MDIO_PORN,&GPIO_InitStructure);
|
||||
GPIO_InitStructure.Pin = ETH_MDC_PIN;
|
||||
HAL_GPIO_Init(ETH_MDC_PORN,&GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.Pin = ETH_RMII_REF_CLK_PIN;
|
||||
HAL_GPIO_Init(ETH_RMII_REF_CLK_PORN,&GPIO_InitStructure);
|
||||
GPIO_InitStructure.Pin = ETH_RMII_CRS_DV_PIN;
|
||||
HAL_GPIO_Init(ETH_RMII_CRS_DV_PORN,&GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.Pin = ETH_RMII_REF_CLK_PIN;
|
||||
HAL_GPIO_Init(ETH_RMII_REF_CLK_PORN,&GPIO_InitStructure);
|
||||
GPIO_InitStructure.Pin = ETH_RMII_CRS_DV_PIN;
|
||||
HAL_GPIO_Init(ETH_RMII_CRS_DV_PORN,&GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.Pin = ETH_RMII_RXD0_PIN;
|
||||
HAL_GPIO_Init(ETH_RMII_RXD0_PORN,&GPIO_InitStructure);
|
||||
GPIO_InitStructure.Pin = ETH_RMII_RXD1_PIN;
|
||||
HAL_GPIO_Init(ETH_RMII_RXD1_PORN,&GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.Pin = ETH_RMII_TX_EN_PIN;
|
||||
HAL_GPIO_Init(ETH_RMII_TX_EN_PORN,&GPIO_InitStructure);
|
||||
GPIO_InitStructure.Pin = ETH_RMII_TXD0_PIN;
|
||||
HAL_GPIO_Init(ETH_RMII_TXD0_PORN,&GPIO_InitStructure);
|
||||
GPIO_InitStructure.Pin = ETH_RMII_TXD1_PIN;
|
||||
HAL_GPIO_Init(ETH_RMII_TXD1_PORN,&GPIO_InitStructure);
|
||||
|
||||
HAL_NVIC_SetPriority(ETH_IRQn,1,0);
|
||||
HAL_NVIC_EnableIRQ(ETH_IRQn);
|
||||
}
|
||||
|
||||
|
||||
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
|
||||
{
|
||||
GPIO_Configuration();
|
||||
NVIC_Configuration();
|
||||
}
|
||||
|
||||
static int rt_hw_stm32_eth_init(void)
|
||||
{
|
||||
rt_err_t state;
|
||||
|
||||
stm32_eth_device.ETH_Speed = ETH_SPEED_100M;
|
||||
stm32_eth_device.ETH_Mode = ETH_MODE_FULLDUPLEX;
|
||||
|
||||
/* OUI 00-80-E1 STMICROELECTRONICS. */
|
||||
stm32_eth_device.dev_addr[0] = 0x00;
|
||||
stm32_eth_device.dev_addr[1] = 0x80;
|
||||
stm32_eth_device.dev_addr[2] = 0xE1;
|
||||
/* generate MAC addr from 96bit unique ID (only for test). */
|
||||
stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(UID_BASE+4);
|
||||
stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(UID_BASE+2);
|
||||
stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(UID_BASE+0);
|
||||
|
||||
stm32_eth_device.parent.parent.init = rt_stm32_eth_init;
|
||||
stm32_eth_device.parent.parent.open = rt_stm32_eth_open;
|
||||
stm32_eth_device.parent.parent.close = rt_stm32_eth_close;
|
||||
stm32_eth_device.parent.parent.read = rt_stm32_eth_read;
|
||||
stm32_eth_device.parent.parent.write = rt_stm32_eth_write;
|
||||
stm32_eth_device.parent.parent.control = rt_stm32_eth_control;
|
||||
stm32_eth_device.parent.parent.user_data = RT_NULL;
|
||||
|
||||
stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
|
||||
stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
|
||||
|
||||
STM32_ETH_PRINTF("sem init: tx_wait\r\n");
|
||||
/* init tx semaphore */
|
||||
rt_sem_init(&tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO);
|
||||
|
||||
/* register eth device */
|
||||
STM32_ETH_PRINTF("eth_device_init start\r\n");
|
||||
state = eth_device_init(&(stm32_eth_device.parent), "e0");
|
||||
if (RT_EOK == state)
|
||||
{
|
||||
STM32_ETH_PRINTF("eth_device_init success\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
STM32_ETH_PRINTF("eth_device_init faild: %d\r\n", state);
|
||||
}
|
||||
return state;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef __DRV_ETH_H__
|
||||
#define __DRV_ETH_H__
|
||||
|
||||
void rt_hw_stm32_eth_init(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* File : drv_iic.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2017 RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-06-05 tanek first implementation.
|
||||
*/
|
||||
|
||||
#include "drv_iic.h"
|
||||
|
||||
#include <board.h>
|
||||
#include <finsh.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rthw.h>
|
||||
|
||||
#define DEBUG
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
|
||||
#else
|
||||
#define DEBUG_PRINTF(...)
|
||||
#endif
|
||||
|
||||
static void stm32f4_i2c_gpio_init()
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_Initure;
|
||||
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
|
||||
GPIO_Initure.Pin = GPIO_PIN_4 | GPIO_PIN_5;
|
||||
GPIO_Initure.Mode = GPIO_MODE_OUTPUT_OD;
|
||||
GPIO_Initure.Pull = GPIO_PULLUP;
|
||||
GPIO_Initure.Speed = GPIO_SPEED_FAST;
|
||||
HAL_GPIO_Init(GPIOH, &GPIO_Initure);
|
||||
|
||||
HAL_GPIO_WritePin(GPIOH, GPIO_PIN_5, GPIO_PIN_SET);
|
||||
HAL_GPIO_WritePin(GPIOH, GPIO_PIN_4, GPIO_PIN_SET);
|
||||
}
|
||||
|
||||
static void stm32f4_set_sda(void *data, rt_int32_t state)
|
||||
{
|
||||
HAL_GPIO_WritePin(GPIOH, GPIO_PIN_5, (GPIO_PinState)state);
|
||||
}
|
||||
|
||||
static void stm32f4_set_scl(void *data, rt_int32_t state)
|
||||
{
|
||||
HAL_GPIO_WritePin(GPIOH, GPIO_PIN_4, (GPIO_PinState)state);
|
||||
}
|
||||
|
||||
static rt_int32_t stm32f4_get_sda(void *data)
|
||||
{
|
||||
return (rt_int32_t)HAL_GPIO_ReadPin(GPIOH, GPIO_PIN_5);
|
||||
}
|
||||
|
||||
static rt_int32_t stm32f4_get_scl(void *data)
|
||||
{
|
||||
return (rt_int32_t)HAL_GPIO_ReadPin(GPIOH, GPIO_PIN_4);
|
||||
}
|
||||
|
||||
static void stm32f4_udelay(rt_uint32_t us)
|
||||
{
|
||||
rt_int32_t i;
|
||||
for (; us > 0; us--)
|
||||
{
|
||||
i = 50;
|
||||
while (i > 0)
|
||||
{
|
||||
i--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static const struct rt_i2c_bit_ops bit_ops = {
|
||||
RT_NULL,
|
||||
stm32f4_set_sda,
|
||||
stm32f4_set_scl,
|
||||
stm32f4_get_sda,
|
||||
stm32f4_get_scl,
|
||||
|
||||
stm32f4_udelay,
|
||||
|
||||
5,
|
||||
100
|
||||
};
|
||||
|
||||
int stm32f4_i2c_init(void)
|
||||
{
|
||||
struct rt_i2c_bus_device *bus;
|
||||
|
||||
bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
|
||||
if (bus == RT_NULL)
|
||||
{
|
||||
rt_kprintf("rt_malloc failed\n");
|
||||
return -RT_ENOMEM;
|
||||
}
|
||||
|
||||
rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
|
||||
|
||||
bus->priv = (void *)&bit_ops;
|
||||
|
||||
stm32f4_i2c_gpio_init();
|
||||
|
||||
rt_i2c_bit_add_bus(bus, "i2c0");
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_DEVICE_EXPORT(stm32f4_i2c_init);
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* File : drv_iic.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2017 RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-06-05 tanek first implementation.
|
||||
*/
|
||||
|
||||
#ifndef STM32F4XX_IIC_INCLUDED
|
||||
#define STM32F4XX_IIC_INCLUDED
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <drivers/spi.h>
|
||||
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
|
||||
#endif // STM32F20X_40X_SPI_H_INCLUDED
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* File : drv_iic.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2017 RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-06-09 tanek first implementation.
|
||||
*/
|
||||
#include "drv_pcf8574.h"
|
||||
#include <board.h>
|
||||
#include <rthw.h>
|
||||
#include <finsh.h>
|
||||
|
||||
//#define DEBUG
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DEBUG_PRINTF(...) rt_kprintf(__VA_ARGS__)
|
||||
#else
|
||||
#define DEBUG_PRINTF(...)
|
||||
#endif
|
||||
|
||||
#define I2C_BUS_NAME "i2c0"
|
||||
#define PCF8574_ADDR 0x20
|
||||
|
||||
static uint8_t rt_pcf8574_read_onebyte(void);
|
||||
static void rt_pcf8574_write_onebyte(rt_uint8_t value);
|
||||
|
||||
static struct rt_i2c_bus_device * i2c_bus;
|
||||
|
||||
rt_err_t rt_pcf8574_init(void)
|
||||
{
|
||||
rt_uint8_t buffer[] = { 0xFF };
|
||||
rt_off_t pos = PCF8574_ADDR;
|
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
|
||||
i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME);
|
||||
if (i2c_bus == RT_NULL)
|
||||
{
|
||||
DEBUG_PRINTF("\ni2c_bus %s for PCF8574 not found!\n", I2C_BUS_NAME);
|
||||
return -RT_ENOSYS;
|
||||
}
|
||||
|
||||
if (rt_device_open(&i2c_bus->parent, RT_NULL) != RT_EOK)
|
||||
{
|
||||
DEBUG_PRINTF("\ni2c_bus %s for cs43l22 opened failed!\n", I2C_BUS_NAME);
|
||||
return -RT_EEMPTY;
|
||||
}
|
||||
|
||||
rt_device_write(&i2c_bus->parent, pos, &buffer, 1);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static uint8_t rt_pcf8574_read_onebyte(void)
|
||||
{
|
||||
rt_uint8_t value;
|
||||
|
||||
rt_device_read(&i2c_bus->parent, PCF8574_ADDR, &value, 1);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
static void rt_pcf8574_write_onebyte(rt_uint8_t value)
|
||||
{
|
||||
rt_device_write(&i2c_bus->parent, PCF8574_ADDR, &value, 1);
|
||||
}
|
||||
|
||||
|
||||
void rt_pcf8574_write_bit(rt_uint8_t bit, rt_uint8_t state)
|
||||
{
|
||||
rt_uint8_t data;
|
||||
data = rt_pcf8574_read_onebyte();
|
||||
|
||||
if (state == 0)
|
||||
data &= ~(1 << bit);
|
||||
else
|
||||
data |= 1 << bit;
|
||||
|
||||
rt_pcf8574_write_onebyte(data);
|
||||
}
|
||||
|
||||
|
||||
rt_uint8_t rt_pcf8574_read_bit(rt_uint8_t bit)
|
||||
{
|
||||
rt_uint8_t data;
|
||||
data = rt_pcf8574_read_onebyte();
|
||||
|
||||
if (data&(1 << bit))
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
#ifndef __DRV_PCF8574_H
|
||||
#define __DRV_PCF8574_H
|
||||
|
||||
#include <board.h>
|
||||
#include <finsh.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rthw.h>
|
||||
|
||||
//PCF8574各个IO的功能
|
||||
#define BEEP_IO 0 //蜂鸣器控制引脚 P0
|
||||
#define AP_INT_IO 1 //AP3216C中断引脚 P1
|
||||
#define DCMI_PWDN_IO 2 //DCMI的电源控制引脚 P2
|
||||
#define USB_PWR_IO 3 //USB电源控制引脚 P3
|
||||
#define EX_IO 4 //扩展IO,自定义使用 P4
|
||||
#define MPU_INT_IO 5 //MPU9250中断引脚 P5
|
||||
#define RS485_RE_IO 6 //RS485_RE引脚 P6
|
||||
#define ETH_RESET_IO 7 //以太网复位引脚 P7
|
||||
|
||||
rt_err_t rt_pcf8574_init(void);
|
||||
|
||||
void rt_pcf8574_write_bit(rt_uint8_t bit, rt_uint8_t state);
|
||||
rt_uint8_t rt_pcf8574_read_bit(rt_uint8_t bit);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -186,7 +186,9 @@
|
|||
/* Enable DNS */
|
||||
#define RT_LWIP_DNS
|
||||
/* Enable DHCP */
|
||||
//#define RT_LWIP_DHCP
|
||||
#define RT_LWIP_DHCP
|
||||
/* Enable DEBUG */
|
||||
//#define RT_LWIP_DEBUG
|
||||
|
||||
/* the number of simulatenously active TCP connections*/
|
||||
#define RT_LWIP_TCP_PCB_NUM 5
|
||||
|
|
@ -228,9 +230,9 @@
|
|||
#define CHECKSUM_CHECK_IP 0
|
||||
#define CHECKSUM_CHECK_UDP 0
|
||||
|
||||
#define CHECKSUM_GEN_TCP 0
|
||||
#define CHECKSUM_GEN_IP 0
|
||||
#define CHECKSUM_GEN_UDP 0
|
||||
//#define CHECKSUM_GEN_TCP 0
|
||||
//#define CHECKSUM_GEN_IP 0
|
||||
//#define CHECKSUM_GEN_UDP 0
|
||||
|
||||
/* RT_GDB_STUB */
|
||||
//#define RT_USING_GDB
|
||||
|
|
@ -246,4 +248,7 @@
|
|||
/* serial flash discoverable parameters by JEDEC standard */
|
||||
#define RT_SFUD_USING_SFDP
|
||||
|
||||
#define RT_USING_I2C
|
||||
#define RT_USING_I2C_BITOPS
|
||||
|
||||
#endif
|
||||
|
|
|
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Reference in New Issue