Merge pull request #77 from weety/at91sam9260
Fixed At91sam9260 context switch issue, enable mmu, update SDIO and EMAC drivers
This commit is contained in:
Bernard Xiong
commit
9cac0ca416
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@ -27,6 +27,12 @@
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#define mci_dbg(fmt, ...)
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#endif
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#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
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extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
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extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
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#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
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| AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
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| AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
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@ -334,6 +340,7 @@ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd
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* Handle a read
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*/
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mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
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at91_mci_init_dma_read(mci);
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ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
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}
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@ -359,13 +366,15 @@ static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd
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return;
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}
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rt_memset(mci->buf, 0, 12);
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rt_memcpy(mci->buf, data->buf, block_length * blocks);
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rt_memcpy(mci->buf, data->buf, length);
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mmu_clean_dcache((rt_uint32_t)mci->buf, length);
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at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf));
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at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
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length : length / 4);
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}
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else
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{
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mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
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at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf));
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at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
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length : length / 4);
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@ -839,7 +848,8 @@ rt_int32_t at91_mci_init(void)
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host->freq_min = 375000;
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host->freq_max = 25000000;
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host->valid_ocr = VDD_32_33 | VDD_33_34;
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host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE;
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host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
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MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
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host->max_seg_size = 65535;
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host->max_dma_segs = 2;
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host->max_blk_size = 512;
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@ -341,7 +341,7 @@ void rt_hw_board_init()
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rt_hw_uart_init();
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/* initialize mmu */
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//rt_hw_mmu_init();
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rt_hw_mmu_init();
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/* initialize timer0 */
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rt_hw_timer_init();
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@ -18,6 +18,26 @@
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#include <at91sam926x.h>
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#include "macb.h"
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#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
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extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
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extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
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/* Cache macros - Packet buffers would be from pbuf pool which is cached */
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#define EMAC_VIRT_NOCACHE(addr) (addr)
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#define EMAC_CACHE_INVALIDATE(addr, size) \
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mmu_invalidate_dcache((rt_uint32_t)addr, size)
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#define EMAC_CACHE_WRITEBACK(addr, size) \
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mmu_clean_dcache((rt_uint32_t)addr, size)
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#define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
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mmu_clean_invalidated_dcache((rt_uint32_t)addr, size)
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/* EMAC has BD's in cached memory - so need cache functions */
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#define BD_CACHE_INVALIDATE(addr, size)
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#define BD_CACHE_WRITEBACK(addr, size)
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#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size)
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#define CONFIG_RMII
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#define MACB_RX_BUFFER_SIZE 4096*4
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@ -378,6 +398,8 @@ static rt_err_t rt_macb_init(rt_device_t dev)
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}
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macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
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BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
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BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
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macb_writel(macb, RBQP, macb->rx_ring_dma);
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macb_writel(macb, TBQP, macb->tx_ring_dma);
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@ -470,28 +492,12 @@ static rt_err_t rt_macb_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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/* transmit packet. */
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rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p)
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{
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struct pbuf* q;
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rt_uint8_t* bufptr, *buf = RT_NULL;
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unsigned long ctrl;
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struct rt_macb_eth *macb = dev->user_data;
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unsigned int tx_head = macb->tx_head;
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/* lock macb device */
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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buf = rt_malloc(p->tot_len);
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if (!buf) {
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rt_kprintf("%s:alloc buf failed\n", __func__);
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return -RT_ENOMEM;
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}
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bufptr = buf;
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for (q = p; q != NULL; q = q->next)
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{
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memcpy(bufptr, q->payload, q->len);
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bufptr += q->len;
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}
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EMAC_CACHE_WRITEBACK(p->payload, p->tot_len);
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ctrl = p->tot_len & TXBUF_FRMLEN_MASK;
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ctrl |= TXBUF_FRAME_END;
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if (tx_head == (MACB_TX_RING_SIZE - 1)) {
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@ -499,17 +505,14 @@ rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p)
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macb->tx_head = 0;
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} else
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macb->tx_head++;
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macb->tx_ring[tx_head].ctrl = ctrl;
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macb->tx_ring[tx_head].addr = (rt_uint32_t)buf;
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macb->tx_ring[tx_head].addr = (rt_uint32_t)p->payload;
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BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring[tx_head], sizeof(struct macb_dma_desc));
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macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
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/* unlock macb device */
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rt_sem_release(&sem_lock);
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/* wait ack */
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rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
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rt_free(buf);
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return RT_EOK;
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}
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@ -546,12 +549,7 @@ struct pbuf *rt_macb_rx(rt_device_t dev)
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int wrapped = 0;
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rt_uint32_t status;
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struct pbuf* q;
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rt_uint8_t *buf = RT_NULL;
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/* lock macb device */
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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for (;;) {
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if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
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break;
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@ -574,39 +572,18 @@ struct pbuf *rt_macb_rx(rt_device_t dev)
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}
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if (wrapped) {
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unsigned int headlen, taillen;
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buf = rt_malloc(len);
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if (!buf)
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{
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rt_kprintf("%s:alloc memory failed\n", __func__);
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pbuf_free(p);
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p = RT_NULL;
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break;
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}
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headlen = 128 * (MACB_RX_RING_SIZE
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- macb->rx_tail);
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taillen = len - headlen;
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memcpy((void *)buf,
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buffer, headlen);
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memcpy((void *)((unsigned int)buf + headlen),
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EMAC_CACHE_INVALIDATE(buffer, headlen);
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EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen);
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memcpy((void *)p->payload, buffer, headlen);
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memcpy((void *)((unsigned int)p->payload + headlen),
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macb->rx_buffer, taillen);
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buffer = (void *)buf;
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for (q = p; q != RT_NULL; q= q->next)
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{
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/* read data from device */
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memcpy((void *)q->payload, buffer, q->len);
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buffer = (void *)((unsigned int)buffer + q->len);
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}
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rt_free(buf);
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buf = RT_NULL;
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} else {
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for (q = p; q != RT_NULL; q= q->next)
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{
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/* read data from device */
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memcpy((void *)q->payload, buffer, q->len);
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buffer = (void *)((unsigned int)buffer + q->len);
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}
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EMAC_CACHE_INVALIDATE(buffer, len);
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memcpy((void *)p->payload, buffer, p->len);
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}
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if (++rx_tail >= MACB_RX_RING_SIZE)
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@ -620,7 +597,7 @@ struct pbuf *rt_macb_rx(rt_device_t dev)
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}
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}
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}
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/* unlock macb device */
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rt_sem_release(&sem_lock);
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return p;
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@ -648,10 +625,16 @@ void macb_initialize()
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macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
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macb->tx_ring = rt_malloc(MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
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EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc));
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EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc));
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macb->rx_buffer_dma = (unsigned long)macb->rx_buffer;
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macb->rx_ring_dma = (unsigned long)macb->rx_ring;
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macb->tx_ring_dma = (unsigned long)macb->tx_ring;
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macb->rx_ring = MMU_NOCACHE_ADDR(macb->rx_ring);
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macb->tx_ring = MMU_NOCACHE_ADDR(macb->tx_ring);
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macb->regs = AT91SAM9260_BASE_EMAC;
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macb->phy_addr = 0x00;
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@ -141,8 +141,6 @@
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#define RT_USING_LWIP
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#define RT_LWIP_DNS
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#define LWIP_NETIF_LINK_CALLBACK 1
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/* Trace LwIP protocol */
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// #define RT_LWIP_DEBUG
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@ -59,9 +59,9 @@ rt_hw_context_switch:
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ldmfd sp!, {r4} @ pop new task spsr
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msr spsr_cxsf, r4
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ldmfd sp!, {r4} @ pop new task cpsr
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msr cpsr_cxsf, r4
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msr spsr_cxsf, r4
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ldmfd sp!, {r0-r12, lr, pc} @ pop new task r0-r12, lr & pc
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ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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@ -60,9 +60,9 @@ rt_hw_context_switch PROC
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LDMFD sp!, {r4} ; pop new task spsr
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MSR spsr_cxsf, r4
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LDMFD sp!, {r4} ; pop new task cpsr
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MSR cpsr_cxsf, r4
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MSR spsr_cxsf, r4
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LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
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LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc
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ENDP
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;/*
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@ -9,19 +9,17 @@
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety modified from mini2440
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*/
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#include <rtthread.h>
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#include "at91sam926x.h"
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#define _MMUTT_STARTADDRESS 0x33FF0000
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#define CACHE_LINE_SIZE 32
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#define DESC_SEC (0x2|(1<<4))
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#define CB (3<<2) //cache_on, write_back
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#define CNB (2<<2) //cache_on, write_through
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#define NCB (1<<2) //cache_off,WR_BUF on
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#define NCNB (0<<2) //cache_off,WR_BUF off
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#define NCNB (0<<2) //cache_off,WR_BUF off
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#define AP_RW (3<<10) //supervisor=RW, user=RW
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#define AP_RO (2<<10) //supervisor=RW, user=RO
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@ -34,147 +32,31 @@
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#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
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#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
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#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
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#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
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#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
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#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
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#ifdef __GNUC__
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void mmu_setttbase(register rt_uint32_t i)
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{
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asm ("mcr p15, 0, %0, c2, c0, 0": :"r" (i));
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}
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void mmu_set_domain(register rt_uint32_t i)
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{
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asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
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}
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void mmu_enable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= 0x1;
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~0x1;
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 12);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 2);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_icache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 12);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_dcache()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 2);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_enable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i |= (1 << 1);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_disable_alignfault()
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{
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register rt_uint32_t i;
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/* read control register */
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asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
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i &= ~(1 << 1);
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/* write back to control register */
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asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
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}
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void mmu_clean_invalidated_cache_index(int index)
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{
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asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
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}
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void mmu_invalidate_tlb()
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{
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asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
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}
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void mmu_invalidate_icache()
|
||||
{
|
||||
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
|
||||
}
|
||||
#endif
|
||||
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
|
||||
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
|
||||
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
|
||||
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
|
||||
|
||||
#ifdef __CC_ARM
|
||||
void mmu_setttbase(rt_uint32_t i)
|
||||
{
|
||||
register rt_uint32_t value;
|
||||
|
||||
/* Invalidates all TLBs.Domain access is selected as
|
||||
* client by configuring domain access register,
|
||||
* in that case access controlled by permission value
|
||||
* set by page table entry
|
||||
*/
|
||||
value = 0;
|
||||
__asm
|
||||
{
|
||||
mcr p15, 0, value, c8, c7, 0
|
||||
}
|
||||
|
||||
value = 0x55555555;
|
||||
__asm
|
||||
{
|
||||
mcr p15, 0, value, c3, c0, 0
|
||||
mcr p15, 0, i, c2, c0, 0
|
||||
}
|
||||
}
|
||||
|
|
@ -291,6 +173,54 @@ void mmu_clean_invalidated_cache_index(int index)
|
|||
}
|
||||
}
|
||||
|
||||
void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
|
||||
{
|
||||
unsigned int ptr;
|
||||
|
||||
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
|
||||
|
||||
while(ptr < buffer + size)
|
||||
{
|
||||
__asm
|
||||
{
|
||||
MCR p15, 0, ptr, c7, c14, 1
|
||||
}
|
||||
ptr += CACHE_LINE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
|
||||
{
|
||||
unsigned int ptr;
|
||||
|
||||
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
|
||||
|
||||
while (ptr < buffer + size)
|
||||
{
|
||||
__asm
|
||||
{
|
||||
MCR p15, 0, ptr, c7, c10, 1
|
||||
}
|
||||
ptr += CACHE_LINE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
|
||||
{
|
||||
unsigned int ptr;
|
||||
|
||||
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
|
||||
|
||||
while (ptr < buffer + size)
|
||||
{
|
||||
__asm
|
||||
{
|
||||
MCR p15, 0, ptr, c7, c6, 1
|
||||
}
|
||||
ptr += CACHE_LINE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
void mmu_invalidate_tlb()
|
||||
{
|
||||
register rt_uint32_t value;
|
||||
|
|
@ -313,13 +243,214 @@ void mmu_invalidate_icache()
|
|||
mcr p15, 0, value, c7, c5, 0
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void mmu_invalidate_dcache_all()
|
||||
{
|
||||
register rt_uint32_t value;
|
||||
|
||||
value = 0;
|
||||
|
||||
__asm
|
||||
{
|
||||
mcr p15, 0, value, c7, c6, 0
|
||||
}
|
||||
}
|
||||
#elif defined(__GNUC__)
|
||||
void mmu_setttbase(register rt_uint32_t i)
|
||||
{
|
||||
register rt_uint32_t value;
|
||||
|
||||
/* Invalidates all TLBs.Domain access is selected as
|
||||
* client by configuring domain access register,
|
||||
* in that case access controlled by permission value
|
||||
* set by page table entry
|
||||
*/
|
||||
value = 0;
|
||||
asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
|
||||
|
||||
value = 0x55555555;
|
||||
asm ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
|
||||
asm ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
|
||||
}
|
||||
|
||||
void mmu_set_domain(register rt_uint32_t i)
|
||||
{
|
||||
asm ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
|
||||
}
|
||||
|
||||
void mmu_enable()
|
||||
{
|
||||
register rt_uint32_t i;
|
||||
|
||||
/* read control register */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
|
||||
i |= 0x1;
|
||||
|
||||
/* write back to control register */
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
}
|
||||
|
||||
void mmu_disable()
|
||||
{
|
||||
register rt_uint32_t i;
|
||||
|
||||
/* read control register */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
|
||||
i &= ~0x1;
|
||||
|
||||
/* write back to control register */
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
}
|
||||
|
||||
void mmu_enable_icache()
|
||||
{
|
||||
register rt_uint32_t i;
|
||||
|
||||
/* read control register */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
|
||||
i |= (1 << 12);
|
||||
|
||||
/* write back to control register */
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
}
|
||||
|
||||
void mmu_enable_dcache()
|
||||
{
|
||||
register rt_uint32_t i;
|
||||
|
||||
/* read control register */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
|
||||
i |= (1 << 2);
|
||||
|
||||
/* write back to control register */
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
}
|
||||
|
||||
void mmu_disable_icache()
|
||||
{
|
||||
register rt_uint32_t i;
|
||||
|
||||
/* read control register */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
|
||||
i &= ~(1 << 12);
|
||||
|
||||
/* write back to control register */
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
}
|
||||
|
||||
void mmu_disable_dcache()
|
||||
{
|
||||
register rt_uint32_t i;
|
||||
|
||||
/* read control register */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
|
||||
i &= ~(1 << 2);
|
||||
|
||||
/* write back to control register */
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
}
|
||||
|
||||
void mmu_enable_alignfault()
|
||||
{
|
||||
register rt_uint32_t i;
|
||||
|
||||
/* read control register */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
|
||||
i |= (1 << 1);
|
||||
|
||||
/* write back to control register */
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
}
|
||||
|
||||
void mmu_disable_alignfault()
|
||||
{
|
||||
register rt_uint32_t i;
|
||||
|
||||
/* read control register */
|
||||
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
|
||||
|
||||
i &= ~(1 << 1);
|
||||
|
||||
/* write back to control register */
|
||||
asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
|
||||
}
|
||||
|
||||
void mmu_clean_invalidated_cache_index(int index)
|
||||
{
|
||||
asm ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
|
||||
}
|
||||
|
||||
void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
|
||||
{
|
||||
unsigned int ptr;
|
||||
|
||||
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
|
||||
|
||||
while(ptr < buffer + size)
|
||||
{
|
||||
asm ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
|
||||
ptr += CACHE_LINE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
|
||||
{
|
||||
unsigned int ptr;
|
||||
|
||||
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
|
||||
|
||||
while (ptr < buffer + size)
|
||||
{
|
||||
asm ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
|
||||
ptr += CACHE_LINE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
|
||||
{
|
||||
unsigned int ptr;
|
||||
|
||||
ptr = buffer & ~(CACHE_LINE_SIZE - 1);
|
||||
|
||||
while (ptr < buffer + size)
|
||||
{
|
||||
asm ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
|
||||
ptr += CACHE_LINE_SIZE;
|
||||
}
|
||||
}
|
||||
|
||||
void mmu_invalidate_tlb()
|
||||
{
|
||||
asm ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
|
||||
}
|
||||
|
||||
void mmu_invalidate_icache()
|
||||
{
|
||||
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
|
||||
}
|
||||
|
||||
void mmu_invalidate_dcache_all()
|
||||
{
|
||||
asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
|
||||
}
|
||||
#endif
|
||||
|
||||
void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
|
||||
/* level1 page table */
|
||||
static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)));
|
||||
void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr)
|
||||
{
|
||||
volatile rt_uint32_t *pTT;
|
||||
volatile int i,nSec;
|
||||
pTT=(rt_uint32_t *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
|
||||
pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
|
||||
nSec=(vaddrEnd>>20)-(vaddrStart>>20);
|
||||
for(i=0;i<=nSec;i++)
|
||||
{
|
||||
|
|
@ -330,66 +461,32 @@ void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
|
|||
|
||||
void rt_hw_mmu_init(void)
|
||||
{
|
||||
#if 0
|
||||
int i,j;
|
||||
//========================== IMPORTANT NOTE =========================
|
||||
//The current stack and code area can't be re-mapped in this routine.
|
||||
//If you want memory map mapped freely, your own sophiscated mmu
|
||||
//initialization code is needed.
|
||||
//===================================================================
|
||||
|
||||
/* disable I/D cache */
|
||||
mmu_disable_dcache();
|
||||
mmu_disable_icache();
|
||||
|
||||
//If write-back is used,the DCache should be cleared.
|
||||
for(i=0;i<64;i++)
|
||||
for(j=0;j<8;j++)
|
||||
mmu_clean_invalidated_cache_index((i<<26)|(j<<5));
|
||||
|
||||
mmu_invalidate_icache();
|
||||
|
||||
//To complete mmu_Init() fast, Icache may be turned on here.
|
||||
mmu_enable_icache();
|
||||
|
||||
mmu_disable();
|
||||
mmu_invalidate_tlb();
|
||||
|
||||
//mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr);
|
||||
mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0
|
||||
mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0
|
||||
mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0
|
||||
mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1
|
||||
mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2
|
||||
mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3
|
||||
//mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4
|
||||
mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000
|
||||
mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5
|
||||
//30f00000->30100000, 31000000->30200000
|
||||
mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1
|
||||
mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2
|
||||
/* set page table */
|
||||
mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */
|
||||
mmu_setmtt(0x20000000, 0x24000000-1, 0x20000000, RW_CB); /* 64M cached SDRAM memory */
|
||||
mmu_setmtt(0x00000000, 0x100000, 0x20000000, RW_CB); /* isr vector table */
|
||||
mmu_setmtt(0x90000000, 0x100000, 0x00000000, RW_CB); /* 4K cached internal memory */
|
||||
mmu_setmtt(0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB); /* 64M none-cached SDRAM memory */
|
||||
|
||||
mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3
|
||||
mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7
|
||||
/* set MMU table address */
|
||||
mmu_setttbase((rt_uint32_t)_page_table);
|
||||
|
||||
mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
|
||||
mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
|
||||
mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
|
||||
mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used
|
||||
mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR
|
||||
/* enables MMU */
|
||||
mmu_enable();
|
||||
|
||||
mmu_setttbase(_MMUTT_STARTADDRESS);
|
||||
/* enable Instruction Cache */
|
||||
mmu_enable_icache();
|
||||
|
||||
/* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */
|
||||
mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR);
|
||||
/* enable Data Cache */
|
||||
mmu_enable_dcache();
|
||||
|
||||
mmu_enable_alignfault();
|
||||
|
||||
mmu_enable();
|
||||
|
||||
/* ICache enable */
|
||||
mmu_enable_icache();
|
||||
/* DCache should be turned on after mmu is turned on. */
|
||||
mmu_enable_dcache();
|
||||
#endif
|
||||
mmu_invalidate_icache();
|
||||
mmu_invalidate_dcache_all();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -51,8 +51,8 @@
|
|||
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
|
||||
#define AT91_RSTC_PERRST (1 << 2)
|
||||
#define AT91_RSTC_KEY (0xa5 << 24)
|
||||
#define AT91_MATRIX_BASE 0xffffee00
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX_BASE + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_BASE 0xffffee00
|
||||
#define AT91_MATRIX_MRCR (AT91_MATRIX_BASE + 0x100) /* Master Remap Control Register */
|
||||
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
|
||||
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
|
||||
#define AT91_AIC_BASE 0xfffff000
|
||||
|
|
@ -172,9 +172,7 @@ reset:
|
|||
str r1, [r0]
|
||||
|
||||
/* set interrupt vector */
|
||||
#if 1
|
||||
ldr r0, _TEXT_BASE//_load_address
|
||||
//ldr r1, =0x200000 /* target address */
|
||||
ldr r0, _TEXT_BASE
|
||||
mov r1, #0x00
|
||||
add r2, r0, #0x40 /* size, 32bytes */
|
||||
|
||||
|
|
@ -183,7 +181,6 @@ copy_loop:
|
|||
stmia r1!, {r3-r10} /* copy to target address [r1] */
|
||||
cmp r0, r2 /* until source end addreee [r2] */
|
||||
ble copy_loop
|
||||
#endif
|
||||
|
||||
/* setup stack */
|
||||
bl stack_setup
|
||||
|
|
|
|||
Loading…
Reference in New Issue