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Merge pull request #1346 from TanekLiang/imxrt-eth-fixed 

[bsp][imxrt1052-evk] update eth driver
This commit is contained in:
Bernard Xiong 2018-04-09 13:54:45 +08:00 committed by GitHub
parent 0e1ab3d54a ae1536b2a0
commit 962a9b012c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 331 additions and 306 deletions
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8
bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c
View File

@ -1345,7 +1345,13 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
#else #else
address = (uint32_t)curBuffDescrip->buffer; address = (uint32_t)curBuffDescrip->buffer;
#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
memcpy((void *)address, data, length);
{
// Change SDK to reduce memory copy
extern void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len);
pbuf2mem(data, (void *)address, length);
}
//memcpy((void *)address, data, length);
/* Set data length. */ /* Set data length. */
curBuffDescrip->length = length; curBuffDescrip->length = length;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE

593
bsp/imxrt1052-evk/drivers/drv_eth.c
View File

@ -16,7 +16,7 @@
#include <rtdevice.h> #include <rtdevice.h>
#ifdef RT_USING_FINSH #ifdef RT_USING_FINSH
#include <finsh.h> #include <finsh.h>
#endif #endif
#include "fsl_enet.h" #include "fsl_enet.h"
@ -50,13 +50,13 @@
struct rt_imxrt_eth struct rt_imxrt_eth
{ {
/* inherit from ethernet device */ /* inherit from ethernet device */
struct eth_device parent; struct eth_device parent;
enet_handle_t enet_handle; enet_handle_t enet_handle;
ENET_Type *enet_base; ENET_Type *enet_base;
enet_data_error_stats_t error_statistic; enet_data_error_stats_t error_statistic;
rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
rt_bool_t tx_is_waiting; rt_bool_t tx_is_waiting;
struct rt_semaphore tx_wait; struct rt_semaphore tx_wait;
@ -73,18 +73,18 @@ ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_
static struct rt_imxrt_eth imxrt_eth_device; static struct rt_imxrt_eth imxrt_eth_device;
void _enet_rx_callback(struct rt_imxrt_eth * eth) void _enet_rx_callback(struct rt_imxrt_eth *eth)
{ {
rt_err_t result; rt_err_t result;
ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt); ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt);
result = eth_device_ready(&(eth->parent)); result = eth_device_ready(&(eth->parent));
if( result != RT_EOK ) if (result != RT_EOK)
rt_kprintf("RX err =%d\n", result ); rt_kprintf("RX err =%d\n", result);
} }
void _enet_tx_callback(struct rt_imxrt_eth * eth) void _enet_tx_callback(struct rt_imxrt_eth *eth)
{ {
if (eth->tx_is_waiting == RT_TRUE) if (eth->tx_is_waiting == RT_TRUE)
{ {
@ -95,7 +95,7 @@ void _enet_tx_callback(struct rt_imxrt_eth * eth)
void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData) void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData)
{ {
switch(event) switch (event)
{ {
case kENET_RxEvent: case kENET_RxEvent:
@ -130,53 +130,53 @@ void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event,
static void _enet_io_init(void) static void _enet_io_init(void)
{ {
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */ CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */ IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */ IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */ IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */ IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */ IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */ IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */ IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */ IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */ IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */ 1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */ IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */ IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux( IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */ IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
0U); /* Software Input On Field: Input Path is determined by functionality */ 0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */ IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
0xB0A9u); /* Slew Rate Field: Fast Slew Rate 0xB0A9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: medium(100MHz) Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -184,9 +184,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */ IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
0xB0A9u); /* Slew Rate Field: Fast Slew Rate 0xB0A9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: medium(100MHz) Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -194,9 +194,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */ IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate 0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6 Drive Strength Field: R0/6
Speed Field: medium(100MHz) Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -204,9 +204,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Keeper Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */ IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate 0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6 Drive Strength Field: R0/6
Speed Field: medium(100MHz) Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -214,9 +214,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Keeper Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: max(200MHz) Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -224,9 +224,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: max(200MHz) Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -234,9 +234,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */ IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: max(200MHz) Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -244,9 +244,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */ IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: max(200MHz) Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -254,9 +254,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */ IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: max(200MHz) Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -264,9 +264,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */ IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: max(200MHz) Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -274,9 +274,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */ IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
0x31u); /* Slew Rate Field: Fast Slew Rate 0x31u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/6 Drive Strength Field: R0/6
Speed Field: low(50MHz) Speed Field: low(50MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -284,9 +284,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Keeper Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */ IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: max(200MHz) Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -294,9 +294,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */ IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate 0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: max(200MHz) Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled Open Drain Enable Field: Open Drain Disabled
@ -304,9 +304,9 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig( IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */ IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
0xB829u); /* Slew Rate Field: Fast Slew Rate 0xB829u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5 Drive Strength Field: R0/5
Speed Field: low(50MHz) Speed Field: low(50MHz)
Open Drain Enable Field: Open Drain Enabled Open Drain Enable Field: Open Drain Enabled
@ -314,8 +314,6 @@ static void _enet_io_init(void)
Pull / Keep Select Field: Pull Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */ Hyst. Enable Field: Hysteresis Disabled */
} }
static void _enet_clk_init(void) static void _enet_clk_init(void)
@ -353,7 +351,8 @@ static void _enet_config(void)
uint32_t sysClock; uint32_t sysClock;
/* prepare the buffer configuration. */ /* prepare the buffer configuration. */
enet_buffer_config_t buffConfig = { enet_buffer_config_t buffConfig =
{
ENET_RXBD_NUM, ENET_RXBD_NUM,
ENET_TXBD_NUM, ENET_TXBD_NUM,
SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT), SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
@ -390,6 +389,43 @@ static void _enet_config(void)
ENET_ActiveRead(imxrt_eth_device.enet_base); ENET_ActiveRead(imxrt_eth_device.enet_base);
} }
#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
static void packet_dump(const char *msg, const struct pbuf *p)
{
const struct pbuf *q;
rt_uint32_t i, j;
rt_uint8_t *ptr;
rt_kprintf("%s %d byte\n", msg, p->tot_len);
i = 0;
for (q = p; q != RT_NULL; q = q->next)
{
ptr = q->payload;
for (j = 0; j < q->len; j++)
{
if ((i % 8) == 0)
{
rt_kprintf(" ");
}
if ((i % 16) == 0)
{
rt_kprintf("\r\n");
}
rt_kprintf("%02x ", *ptr);
i++;
ptr++;
}
}
rt_kprintf("\n\n");
}
#else
#define packet_dump(...)
#endif /* dump */
/* initialize the interface */ /* initialize the interface */
static rt_err_t rt_imxrt_eth_init(rt_device_t dev) static rt_err_t rt_imxrt_eth_init(rt_device_t dev)
{ {
@ -402,127 +438,112 @@ static rt_err_t rt_imxrt_eth_init(rt_device_t dev)
static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag) static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag)
{ {
dbg_log(DBG_LOG, "rt_imxrt_eth_open...\n"); dbg_log(DBG_LOG, "rt_imxrt_eth_open...\n");
return RT_EOK; return RT_EOK;
} }
static rt_err_t rt_imxrt_eth_close(rt_device_t dev) static rt_err_t rt_imxrt_eth_close(rt_device_t dev)
{ {
dbg_log(DBG_LOG, "rt_imxrt_eth_close...\n"); dbg_log(DBG_LOG, "rt_imxrt_eth_close...\n");
return RT_EOK; return RT_EOK;
} }
static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{ {
dbg_log(DBG_LOG, "rt_imxrt_eth_read...\n"); dbg_log(DBG_LOG, "rt_imxrt_eth_read...\n");
rt_set_errno(-RT_ENOSYS); rt_set_errno(-RT_ENOSYS);
return 0; return 0;
} }
static rt_size_t rt_imxrt_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) static rt_size_t rt_imxrt_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{ {
dbg_log(DBG_LOG, "rt_imxrt_eth_write...\n"); dbg_log(DBG_LOG, "rt_imxrt_eth_write...\n");
rt_set_errno(-RT_ENOSYS); rt_set_errno(-RT_ENOSYS);
return 0; return 0;
} }
static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args) static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args)
{ {
dbg_log(DBG_LOG, "rt_imxrt_eth_control...\n"); dbg_log(DBG_LOG, "rt_imxrt_eth_control...\n");
switch(cmd) switch (cmd)
{ {
case NIOCTL_GADDR: case NIOCTL_GADDR:
/* get mac address */ /* get mac address */
if(args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6); if (args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6);
else return -RT_ERROR; else return -RT_ERROR;
break; break;
default : default :
break; break;
} }
return RT_EOK; return RT_EOK;
} }
/* ethernet device interface */ /* ethernet device interface */
/* transmit packet. */ /* transmit packet. */
rt_err_t rt_imxrt_eth_tx( rt_device_t dev, struct pbuf* p) rt_err_t rt_imxrt_eth_tx(rt_device_t dev, struct pbuf *p)
{ {
rt_err_t result = RT_EOK; rt_err_t result = RT_EOK;
enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle;
RT_ASSERT(p != NULL); RT_ASSERT(p != NULL);
RT_ASSERT(enet_handle != RT_NULL); RT_ASSERT(enet_handle != RT_NULL);
dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len); dbg_log(DBG_LOG, "rt_imxrt_eth_tx: %d\n", p->len);
#ifdef ETH_TX_DUMP #ifdef ETH_TX_DUMP
{ packet_dump("send", p);
int i;
uint8_t * buf;
buf = (uint8_t *)p->payload;
for (i = 0; i < p->len; i++)
{
dbg_log(DBG_LOG, "%02X ", buf[i]);
if (i % 16 == 15)
dbg_log(DBG_LOG, "\n");
}
dbg_log(DBG_LOG, "\n");
}
#endif #endif
do do
{ {
result = ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, p->payload, p->len); result = ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, (const uint8_t *)p, p->tot_len);
if (result == kStatus_ENET_TxFrameBusy) if (result == kStatus_ENET_TxFrameBusy)
{ {
rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER); imxrt_eth_device.tx_is_waiting = RT_TRUE;
} rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER);
}
} while (result == kStatus_ENET_TxFrameBusy); }
while (result == kStatus_ENET_TxFrameBusy);
return RT_EOK; return RT_EOK;
}
void pbuf2mem(const uint8_t *data, void *dataptr, uint32_t len)
{
pbuf_copy_partial((const struct pbuf *)data, dataptr, len, 0);
} }
/* reception packet. */ /* reception packet. */
struct pbuf *rt_imxrt_eth_rx(rt_device_t dev) struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
{ {
uint32_t length = 0; uint32_t length = 0;
status_t status; status_t status;
struct pbuf* p = RT_NULL; struct pbuf *p = RT_NULL;
enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle; enet_handle_t *enet_handle = &imxrt_eth_device.enet_handle;
ENET_Type *enet_base = imxrt_eth_device.enet_base; ENET_Type *enet_base = imxrt_eth_device.enet_base;
enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic; enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic;
/* Get the Frame size */ /* Get the Frame size */
status = ENET_GetRxFrameSize(enet_handle, &length); status = ENET_GetRxFrameSize(enet_handle, &length);
/* Call ENET_ReadFrame when there is a received frame. */ /* Call ENET_ReadFrame when there is a received frame. */
if (length != 0) if (length != 0)
{ {
/* Received valid frame. Deliver the rx buffer with the size equal to length. */ /* Received valid frame. Deliver the rx buffer with the size equal to length. */
p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL); p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
if (p != NULL) if (p != NULL)
{ {
status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length); status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length);
if (status == kStatus_Success) if (status == kStatus_Success)
{ {
#ifdef ETH_RX_DUMP #ifdef ETH_RX_DUMP
uint8_t *buf; packet_dump("recv", p);
int i; #endif
ETH_PRINTF("A frame received. the length:%d\n", p->len);
buf = (uint8_t *)p->payload;
for (i = 0; i < p->len; i++)
{
dbg_log(DBG_LOG, "%02X ", buf[i]);
if (i % 16 == 15)
dbg_log(DBG_LOG, "\n");
}
dbg_log(DBG_LOG, "\n");
#endif
return p; return p;
} }
else else
@ -535,16 +556,16 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
{ {
dbg_log(DBG_LOG, " pbuf_alloc faild\n"); dbg_log(DBG_LOG, " pbuf_alloc faild\n");
} }
} }
else if (status == kStatus_ENET_RxFrameError) else if (status == kStatus_ENET_RxFrameError)
{ {
dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n"); dbg_log(DBG_WARNING, "ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
/* Update the received buffer when error happened. */ /* Update the received buffer when error happened. */
/* Get the error information of the received g_frame. */ /* Get the error information of the received g_frame. */
ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic); ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic);
/* update the receive buffer. */ /* update the receive buffer. */
ENET_ReadFrame(enet_base, enet_handle, NULL, 0); ENET_ReadFrame(enet_base, enet_handle, NULL, 0);
} }
ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt); ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt);
return NULL; return NULL;
@ -552,7 +573,6 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
static void phy_monitor_thread_entry(void *parameter) static void phy_monitor_thread_entry(void *parameter)
{ {
phy_speed_t speed; phy_speed_t speed;
phy_duplex_t duplex; phy_duplex_t duplex;
bool link = false; bool link = false;
@ -594,7 +614,7 @@ static void phy_monitor_thread_entry(void *parameter)
} }
if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed)
|| (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex)) || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex))
{ {
imxrt_eth_device.speed = (enet_mii_speed_t)speed; imxrt_eth_device.speed = (enet_mii_speed_t)speed;
imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex; imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex;
@ -629,12 +649,12 @@ static int rt_hw_imxrt_eth_init(void)
/* OUI 00-80-E1 STMICROELECTRONICS. */ /* OUI 00-80-E1 STMICROELECTRONICS. */
imxrt_eth_device.dev_addr[0] = 0x00; imxrt_eth_device.dev_addr[0] = 0x00;
imxrt_eth_device.dev_addr[1] = 0x80; imxrt_eth_device.dev_addr[1] = 0x04;
imxrt_eth_device.dev_addr[2] = 0xE1; imxrt_eth_device.dev_addr[2] = 0x9F;
/* generate MAC addr from 96bit unique ID (only for test). */ /* generate MAC addr from 96bit unique ID (only for test). */
imxrt_eth_device.dev_addr[3] = 0x12; imxrt_eth_device.dev_addr[3] = 0x05;
imxrt_eth_device.dev_addr[4] = 0x34; imxrt_eth_device.dev_addr[4] = 0x44;
imxrt_eth_device.dev_addr[5] = 0x56; imxrt_eth_device.dev_addr[5] = 0xE5;
imxrt_eth_device.speed = kENET_MiiSpeed100M; imxrt_eth_device.speed = kENET_MiiSpeed100M;
imxrt_eth_device.duplex = kENET_MiiFullDuplex; imxrt_eth_device.duplex = kENET_MiiFullDuplex;
@ -756,102 +776,102 @@ void enet_reg_dump(void)
#define DUMP_REG(__REG) \ #define DUMP_REG(__REG) \
rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG) rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG)
DUMP_REG(EIR); DUMP_REG(EIR);
DUMP_REG(EIMR); DUMP_REG(EIMR);
DUMP_REG(RDAR); DUMP_REG(RDAR);
DUMP_REG(TDAR); DUMP_REG(TDAR);
DUMP_REG(ECR); DUMP_REG(ECR);
DUMP_REG(MMFR); DUMP_REG(MMFR);
DUMP_REG(MSCR); DUMP_REG(MSCR);
DUMP_REG(MIBC); DUMP_REG(MIBC);
DUMP_REG(RCR); DUMP_REG(RCR);
DUMP_REG(TCR); DUMP_REG(TCR);
DUMP_REG(PALR); DUMP_REG(PALR);
DUMP_REG(PAUR); DUMP_REG(PAUR);
DUMP_REG(OPD); DUMP_REG(OPD);
DUMP_REG(TXIC); DUMP_REG(TXIC);
DUMP_REG(RXIC); DUMP_REG(RXIC);
DUMP_REG(IAUR); DUMP_REG(IAUR);
DUMP_REG(IALR); DUMP_REG(IALR);
DUMP_REG(GAUR); DUMP_REG(GAUR);
DUMP_REG(GALR); DUMP_REG(GALR);
DUMP_REG(TFWR); DUMP_REG(TFWR);
DUMP_REG(RDSR); DUMP_REG(RDSR);
DUMP_REG(TDSR); DUMP_REG(TDSR);
DUMP_REG(MRBR); DUMP_REG(MRBR);
DUMP_REG(RSFL); DUMP_REG(RSFL);
DUMP_REG(RSEM); DUMP_REG(RSEM);
DUMP_REG(RAEM); DUMP_REG(RAEM);
DUMP_REG(RAFL); DUMP_REG(RAFL);
DUMP_REG(TSEM); DUMP_REG(TSEM);
DUMP_REG(TAEM); DUMP_REG(TAEM);
DUMP_REG(TAFL); DUMP_REG(TAFL);
DUMP_REG(TIPG); DUMP_REG(TIPG);
DUMP_REG(FTRL); DUMP_REG(FTRL);
DUMP_REG(TACC); DUMP_REG(TACC);
DUMP_REG(RACC); DUMP_REG(RACC);
DUMP_REG(RMON_T_DROP); DUMP_REG(RMON_T_DROP);
DUMP_REG(RMON_T_PACKETS); DUMP_REG(RMON_T_PACKETS);
DUMP_REG(RMON_T_BC_PKT); DUMP_REG(RMON_T_BC_PKT);
DUMP_REG(RMON_T_MC_PKT); DUMP_REG(RMON_T_MC_PKT);
DUMP_REG(RMON_T_CRC_ALIGN); DUMP_REG(RMON_T_CRC_ALIGN);
DUMP_REG(RMON_T_UNDERSIZE); DUMP_REG(RMON_T_UNDERSIZE);
DUMP_REG(RMON_T_OVERSIZE); DUMP_REG(RMON_T_OVERSIZE);
DUMP_REG(RMON_T_FRAG); DUMP_REG(RMON_T_FRAG);
DUMP_REG(RMON_T_JAB); DUMP_REG(RMON_T_JAB);
DUMP_REG(RMON_T_COL); DUMP_REG(RMON_T_COL);
DUMP_REG(RMON_T_P64); DUMP_REG(RMON_T_P64);
DUMP_REG(RMON_T_P65TO127); DUMP_REG(RMON_T_P65TO127);
DUMP_REG(RMON_T_P128TO255); DUMP_REG(RMON_T_P128TO255);
DUMP_REG(RMON_T_P256TO511); DUMP_REG(RMON_T_P256TO511);
DUMP_REG(RMON_T_P512TO1023); DUMP_REG(RMON_T_P512TO1023);
DUMP_REG(RMON_T_P1024TO2047); DUMP_REG(RMON_T_P1024TO2047);
DUMP_REG(RMON_T_P_GTE2048); DUMP_REG(RMON_T_P_GTE2048);
DUMP_REG(RMON_T_OCTETS); DUMP_REG(RMON_T_OCTETS);
DUMP_REG(IEEE_T_DROP); DUMP_REG(IEEE_T_DROP);
DUMP_REG(IEEE_T_FRAME_OK); DUMP_REG(IEEE_T_FRAME_OK);
DUMP_REG(IEEE_T_1COL); DUMP_REG(IEEE_T_1COL);
DUMP_REG(IEEE_T_MCOL); DUMP_REG(IEEE_T_MCOL);
DUMP_REG(IEEE_T_DEF); DUMP_REG(IEEE_T_DEF);
DUMP_REG(IEEE_T_LCOL); DUMP_REG(IEEE_T_LCOL);
DUMP_REG(IEEE_T_EXCOL); DUMP_REG(IEEE_T_EXCOL);
DUMP_REG(IEEE_T_MACERR); DUMP_REG(IEEE_T_MACERR);
DUMP_REG(IEEE_T_CSERR); DUMP_REG(IEEE_T_CSERR);
DUMP_REG(IEEE_T_SQE); DUMP_REG(IEEE_T_SQE);
DUMP_REG(IEEE_T_FDXFC); DUMP_REG(IEEE_T_FDXFC);
DUMP_REG(IEEE_T_OCTETS_OK); DUMP_REG(IEEE_T_OCTETS_OK);
DUMP_REG(RMON_R_PACKETS); DUMP_REG(RMON_R_PACKETS);
DUMP_REG(RMON_R_BC_PKT); DUMP_REG(RMON_R_BC_PKT);
DUMP_REG(RMON_R_MC_PKT); DUMP_REG(RMON_R_MC_PKT);
DUMP_REG(RMON_R_CRC_ALIGN); DUMP_REG(RMON_R_CRC_ALIGN);
DUMP_REG(RMON_R_UNDERSIZE); DUMP_REG(RMON_R_UNDERSIZE);
DUMP_REG(RMON_R_OVERSIZE); DUMP_REG(RMON_R_OVERSIZE);
DUMP_REG(RMON_R_FRAG); DUMP_REG(RMON_R_FRAG);
DUMP_REG(RMON_R_JAB); DUMP_REG(RMON_R_JAB);
DUMP_REG(RMON_R_RESVD_0); DUMP_REG(RMON_R_RESVD_0);
DUMP_REG(RMON_R_P64); DUMP_REG(RMON_R_P64);
DUMP_REG(RMON_R_P65TO127); DUMP_REG(RMON_R_P65TO127);
DUMP_REG(RMON_R_P128TO255); DUMP_REG(RMON_R_P128TO255);
DUMP_REG(RMON_R_P256TO511); DUMP_REG(RMON_R_P256TO511);
DUMP_REG(RMON_R_P512TO1023); DUMP_REG(RMON_R_P512TO1023);
DUMP_REG(RMON_R_P1024TO2047); DUMP_REG(RMON_R_P1024TO2047);
DUMP_REG(RMON_R_P_GTE2048); DUMP_REG(RMON_R_P_GTE2048);
DUMP_REG(RMON_R_OCTETS); DUMP_REG(RMON_R_OCTETS);
DUMP_REG(IEEE_R_DROP); DUMP_REG(IEEE_R_DROP);
DUMP_REG(IEEE_R_FRAME_OK); DUMP_REG(IEEE_R_FRAME_OK);
DUMP_REG(IEEE_R_CRC); DUMP_REG(IEEE_R_CRC);
DUMP_REG(IEEE_R_ALIGN); DUMP_REG(IEEE_R_ALIGN);
DUMP_REG(IEEE_R_MACERR); DUMP_REG(IEEE_R_MACERR);
DUMP_REG(IEEE_R_FDXFC); DUMP_REG(IEEE_R_FDXFC);
DUMP_REG(IEEE_R_OCTETS_OK); DUMP_REG(IEEE_R_OCTETS_OK);
DUMP_REG(ATCR); DUMP_REG(ATCR);
DUMP_REG(ATVR); DUMP_REG(ATVR);
DUMP_REG(ATOFF); DUMP_REG(ATOFF);
DUMP_REG(ATPER); DUMP_REG(ATPER);
DUMP_REG(ATCOR); DUMP_REG(ATCOR);
DUMP_REG(ATINC); DUMP_REG(ATINC);
DUMP_REG(ATSTMP); DUMP_REG(ATSTMP);
DUMP_REG(TGSR); DUMP_REG(TGSR);
} }
void enet_nvic_tog(void) void enet_nvic_tog(void)
@ -891,24 +911,23 @@ void enet_rx_stat(void)
void enet_buf_info(void) void enet_buf_info(void)
{ {
int i = 0; int i = 0;
for (i = 0; i < ENET_RXBD_NUM; i++) for (i = 0; i < ENET_RXBD_NUM; i++)
{ {
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
i, i,
g_rxBuffDescrip[i].length, g_rxBuffDescrip[i].length,
g_rxBuffDescrip[i].control, g_rxBuffDescrip[i].control,
g_rxBuffDescrip[i].buffer); g_rxBuffDescrip[i].buffer);
} }
for (i = 0; i < ENET_TXBD_NUM; i++) for (i = 0; i < ENET_TXBD_NUM; i++)
{ {
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n", rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
i, i,
g_txBuffDescrip[i].length, g_txBuffDescrip[i].length,
g_txBuffDescrip[i].control, g_txBuffDescrip[i].control,
g_txBuffDescrip[i].buffer); g_txBuffDescrip[i].buffer);
} }
} }