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[bsp] remove error_handler() and resume RT_ASSERT()

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This commit is contained in:
tanek liang 2017-06-14 17:25:42 +08:00
parent 1d6c38f42f
commit 761a793a4b
1 changed files with 8 additions and 8 deletions
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16
bsp/stm32l072/board/board.c
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@ -40,12 +40,6 @@ void NVIC_Configuration(void)
// NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); // NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
} }
void error_handler(void)
{
rt_kprintf("error_handler\n");
while(1);
}
/** /**
* This RCC initial for system. * This RCC initial for system.
* use HSE clock source * use HSE clock source
@ -68,7 +62,10 @@ static void RCC_Configuration(void)
OscInit.PLL.PLLDIV = RCC_PLLDIV_2; OscInit.PLL.PLLDIV = RCC_PLLDIV_2;
OscInit.PLL.PLLMUL = RCC_PLLMUL_4; OscInit.PLL.PLLMUL = RCC_PLLMUL_4;
OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI; OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI;
HAL_RCC_OscConfig(&OscInit); if (HAL_RCC_OscConfig(&OscInit) != HAL_OK)
{
RT_ASSERT(RT_NULL);
}
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */ clocks dividers */
@ -81,7 +78,10 @@ static void RCC_Configuration(void)
ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1; ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1;
ClkInit.APB1CLKDivider = RCC_HCLK_DIV1; ClkInit.APB1CLKDivider = RCC_HCLK_DIV1;
ClkInit.APB2CLKDivider = RCC_HCLK_DIV1; ClkInit.APB2CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1); if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK)
{
RT_ASSERT(RT_NULL);
}
} }
#ifdef PRINT_RCC_FREQ_INFO #ifdef PRINT_RCC_FREQ_INFO