update mini2440
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1634 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong
parent
5b063d3030
commit
71f793e3e9
@ -153,75 +153,66 @@ void rt_dm9000_isr(int irqno)
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rt_uint16_t last_io;
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rt_uint32_t eint_pend;
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eint_pend = EINTPEND;
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/* EINT7 for DM9000 */
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//if((eint_pend & 0x80) == 0x80)
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last_io = DM9000_IO;
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/* Disable all interrupts */
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dm9000_io_write(DM9000_IMR, IMR_PAR);
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/* Got DM9000 interrupt status */
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int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */
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dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */
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DM9000_TRACE("dm9000 isr: int status %04x\n", int_status);
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/* receive overflow */
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if (int_status & ISR_ROS)
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{
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last_io = DM9000_IO;
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/* Disable all interrupts */
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dm9000_io_write(DM9000_IMR, IMR_PAR);
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/* Got DM9000 interrupt status */
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int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */
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dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */
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DM9000_TRACE("dm9000 isr: int status %04x\n", int_status);
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/* receive overflow */
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if (int_status & ISR_ROS)
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{
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rt_kprintf("overflow\n");
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}
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if (int_status & ISR_ROOS)
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{
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rt_kprintf("overflow counter overflow\n");
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}
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/* Received the coming packet */
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if (int_status & ISR_PRS)
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{
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/* a frame has been received */
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eth_device_ready(&(dm9000_device.parent));
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}
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/* Transmit Interrupt check */
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if (int_status & ISR_PTS)
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{
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/* transmit done */
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int tx_status = dm9000_io_read(DM9000_NSR); /* Got TX status */
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if (tx_status & (NSR_TX2END | NSR_TX1END))
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{
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dm9000_device.packet_cnt --;
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if (dm9000_device.packet_cnt > 0)
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{
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DM9000_TRACE("dm9000 isr: tx second packet\n");
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/* transmit packet II */
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/* Set TX length to DM9000 */
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dm9000_io_write(DM9000_TXPLL, dm9000_device.queue_packet_len & 0xff);
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dm9000_io_write(DM9000_TXPLH, (dm9000_device.queue_packet_len >> 8) & 0xff);
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/* Issue TX polling command */
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dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
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}
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/* One packet sent complete */
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rt_sem_release(&sem_ack);
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}
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}
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/* Re-enable interrupt mask */
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dm9000_io_write(DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
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DM9000_IO = last_io;
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rt_kprintf("overflow\n");
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}
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/* clear EINT pending bit */
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EINTPEND = eint_pend;
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if (int_status & ISR_ROOS)
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{
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rt_kprintf("overflow counter overflow\n");
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}
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/* Received the coming packet */
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if (int_status & ISR_PRS)
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{
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/* a frame has been received */
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eth_device_ready(&(dm9000_device.parent));
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}
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/* Transmit Interrupt check */
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if (int_status & ISR_PTS)
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{
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/* transmit done */
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int tx_status = dm9000_io_read(DM9000_NSR); /* Got TX status */
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if (tx_status & (NSR_TX2END | NSR_TX1END))
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{
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dm9000_device.packet_cnt --;
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if (dm9000_device.packet_cnt > 0)
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{
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DM9000_TRACE("dm9000 isr: tx second packet\n");
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/* transmit packet II */
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/* Set TX length to DM9000 */
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dm9000_io_write(DM9000_TXPLL, dm9000_device.queue_packet_len & 0xff);
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dm9000_io_write(DM9000_TXPLH, (dm9000_device.queue_packet_len >> 8) & 0xff);
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/* Issue TX polling command */
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dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
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}
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/* One packet sent complete */
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rt_sem_release(&sem_ack);
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}
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}
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/* Re-enable interrupt mask */
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dm9000_io_write(DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM);
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DM9000_IO = last_io;
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}
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/* RT-Thread Device Interface */
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@ -282,12 +273,13 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
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if (dm9000_device.mode == DM9000_AUTO)
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{
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i = 0;
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while (!(phy_read(1) & 0x20))
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{
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/* autonegation complete bit */
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rt_thread_delay( 10 );
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rt_thread_delay( RT_TICK_PER_SECOND/10 );
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i++;
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if (i > 20)
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if (i > 30 ) /* wait 3s */
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{
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rt_kprintf("could not establish link\n");
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return 0;
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@ -580,6 +572,22 @@ __error_retry:
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#define B4_Tacp 0x0
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#define B4_PMC 0x0
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void INTEINT4_7_handler(int irqno)
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{
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rt_uint32_t eint_pend;
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eint_pend = EINTPEND;
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/* EINT7 : DM9000AEP */
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if( eint_pend & (1<<7) )
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{
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rt_dm9000_isr(0);
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}
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/* clear EINT pending bit */
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EINTPEND = eint_pend;
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}
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void rt_hw_dm9000_init()
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{
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/* Set GPF7 as EINT7 */
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@ -608,7 +616,7 @@ void rt_hw_dm9000_init()
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* Packet Transmitted, Packet Received
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*/
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dm9000_device.dev_addr[0] = 0x01;
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dm9000_device.dev_addr[0] = 0x00;
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dm9000_device.dev_addr[1] = 0x60;
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dm9000_device.dev_addr[2] = 0x6E;
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dm9000_device.dev_addr[3] = 0x11;
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@ -617,9 +625,9 @@ void rt_hw_dm9000_init()
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dm9000_device.parent.parent.init = rt_dm9000_init;
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dm9000_device.parent.parent.open = rt_dm9000_open;
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dm9000_device.parent.parent.close = rt_dm9000_close;
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dm9000_device.parent.parent.close = rt_dm9000_close;
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dm9000_device.parent.parent.read = rt_dm9000_read;
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dm9000_device.parent.parent.write = rt_dm9000_write;
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dm9000_device.parent.parent.write = rt_dm9000_write;
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dm9000_device.parent.parent.control = rt_dm9000_control;
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dm9000_device.parent.parent.user_data = RT_NULL;
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@ -629,26 +637,26 @@ void rt_hw_dm9000_init()
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eth_device_init(&(dm9000_device.parent), "e0");
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/* instal interrupt */
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rt_hw_interrupt_install(INTEINT4_7, rt_dm9000_isr, RT_NULL);
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rt_hw_interrupt_install(INTEINT4_7, INTEINT4_7_handler, RT_NULL);
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rt_hw_interrupt_umask(INTEINT4_7);
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}
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void dm9000a(void)
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{
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rt_kprintf("\n");
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rt_kprintf("NCR (0x00): %02x\n", dm9000_io_read(DM9000_NCR));
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rt_kprintf("NSR (0x01): %02x\n", dm9000_io_read(DM9000_NSR));
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rt_kprintf("TCR (0x02): %02x\n", dm9000_io_read(DM9000_TCR));
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rt_kprintf("TSRI (0x03): %02x\n", dm9000_io_read(DM9000_TSR1));
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rt_kprintf("TSRII (0x04): %02x\n", dm9000_io_read(DM9000_TSR2));
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rt_kprintf("RCR (0x05): %02x\n", dm9000_io_read(DM9000_RCR));
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rt_kprintf("RSR (0x06): %02x\n", dm9000_io_read(DM9000_RSR));
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rt_kprintf("ORCR (0x07): %02x\n", dm9000_io_read(DM9000_ROCR));
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rt_kprintf("CRR (0x2C): %02x\n", dm9000_io_read(DM9000_CHIPR));
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rt_kprintf("CSCR (0x31): %02x\n", dm9000_io_read(DM9000_CSCR));
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rt_kprintf("RCSSR (0x32): %02x\n", dm9000_io_read(DM9000_RCSSR));
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rt_kprintf("ISR (0xFE): %02x\n", dm9000_io_read(DM9000_ISR));
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rt_kprintf("IMR (0xFF): %02x\n", dm9000_io_read(DM9000_IMR));
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rt_kprintf("NCR (%02X): %02x\n", DM9000_NCR, dm9000_io_read(DM9000_NCR));
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rt_kprintf("NSR (%02X): %02x\n", DM9000_NSR, dm9000_io_read(DM9000_NSR));
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rt_kprintf("TCR (%02X): %02x\n", DM9000_TCR, dm9000_io_read(DM9000_TCR));
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rt_kprintf("TSRI (%02X): %02x\n", DM9000_TSR1, dm9000_io_read(DM9000_TSR1));
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rt_kprintf("TSRII (%02X): %02x\n", DM9000_TSR2, dm9000_io_read(DM9000_TSR2));
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rt_kprintf("RCR (%02X): %02x\n", DM9000_RCR, dm9000_io_read(DM9000_RCR));
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rt_kprintf("RSR (%02X): %02x\n", DM9000_RSR, dm9000_io_read(DM9000_RSR));
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rt_kprintf("ORCR (%02X): %02x\n", DM9000_ROCR, dm9000_io_read(DM9000_ROCR));
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rt_kprintf("CRR (%02X): %02x\n", DM9000_CHIPR, dm9000_io_read(DM9000_CHIPR));
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rt_kprintf("CSCR (%02X): %02x\n", DM9000_CSCR, dm9000_io_read(DM9000_CSCR));
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rt_kprintf("RCSSR (%02X): %02x\n", DM9000_RCSSR, dm9000_io_read(DM9000_RCSSR));
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rt_kprintf("ISR (%02X): %02x\n", DM9000_ISR, dm9000_io_read(DM9000_ISR));
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rt_kprintf("IMR (%02X): %02x\n", DM9000_IMR, dm9000_io_read(DM9000_IMR));
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rt_kprintf("\n");
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}
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@ -156,10 +156,8 @@ void rtthread_startup(void)
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int main(void)
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{
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rt_uint32_t UNUSED level;
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/* disable interrupt first */
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level = rt_hw_interrupt_disable();
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rt_hw_interrupt_disable();
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/* startup RT-Thread RTOS */
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rtthread_startup();
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