add init Jz47xx porting.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@791 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong
parent
214e44c3f9
commit
64a7365af5
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Import('env')
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Import('projects')
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Import('RTT_ROOT')
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Import('rtconfig')
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# group definitions
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group = {}
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group['name'] = 'Startup'
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group['CCFLAGS'] = ''
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group['CPPPATH'] = [RTT_ROOT + '/bsp/jz47xx']
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group['CPPDEFINES'] = []
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group['LINKFLAGS'] = ''
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src_bsp = ['application.c', 'startup.c', 'board.c']
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src_drv = ['uart.c']
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group['src'] = File(src_bsp + src_drv)
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# add group to project list
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projects.append(group)
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env.Append(CCFLAGS = group['CCFLAGS'])
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env.Append(CPPPATH = group['CPPPATH'])
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env.Append(CPPDEFINES = group['CPPDEFINES'])
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env.Append(LINKFLAGS = group['LINKFLAGS'])
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obj = env.Object(group['src'])
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Return('obj')
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import os
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import sys
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import rtconfig
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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import mdk
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target = 'rtthread-jz47xx'
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projects = []
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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Export('env')
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Export('RTT_ROOT')
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Export('rtconfig')
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Export('projects')
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# kernel building script
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objs = SConscript(RTT_ROOT + '/src/SConscript', variant_dir='build/src', duplicate=0)
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# arch building script
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objs = objs + SConscript(RTT_ROOT + '/libcpu/SConscript', variant_dir='build/libcpu', duplicate=0)
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# component script
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Repository(RTT_ROOT)
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objs = objs + SConscript('components/SConscript')
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# board build script
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objs = objs + SConscript('SConscript', variant_dir='build/bsp', duplicate=0)
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TARGET = target + '.' + rtconfig.TARGET_EXT
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env.Program(TARGET, objs)
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env.AddPostAction(TARGET, rtconfig.POST_ACTION)
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@ -0,0 +1,26 @@
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/*
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* File : app.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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*/
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/**
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* @addtogroup JZ47xx
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*/
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/*@{*/
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#include <rtthread.h>
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int rt_application_init()
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{
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return 0;
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}
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/*@}*/
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "board.h"
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#include "uart.h"
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/**
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* @addtogroup JZ47xx
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*/
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/*@{*/
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/**
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* This is the timer interrupt service routine.
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*/
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void rt_hw_timer_handler()
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/**
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* This function will initial sam7s64 board.
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*/
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void rt_hw_board_init()
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{
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#ifdef RT_USING_UART
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/* init hardware UART device */
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rt_hw_uart_init();
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#endif
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device("uart");
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#endif
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}
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/*@}*/
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/*
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* File : board.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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void rt_hw_board_init(void);
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#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024)
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#endif
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/* RT-Thread config file */
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#ifndef __RTTHREAD_CFG_H__
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#define __RTTHREAD_CFG_H__
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/* RT_NAME_MAX*/
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#define RT_NAME_MAX 8
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/* RT_ALIGN_SIZE*/
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#define RT_ALIGN_SIZE 4
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/* PRIORITY_MAX */
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#define RT_THREAD_PRIORITY_MAX 32
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/* Tick per Second */
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#define RT_TICK_PER_SECOND 100
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/* SECTION: RT_DEBUG */
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/* Thread Debug */
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#define RT_DEBUG
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#define RT_USING_OVERFLOW_CHECK
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/* Using Hook */
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#define RT_USING_HOOK
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/* Using Software Timer */
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/* #define RT_USING_TIMER_SOFT */
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#define RT_TIMER_THREAD_PRIO 4
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#define RT_TIMER_THREAD_STACK_SIZE 512
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#define RT_TIMER_TICK_PER_SECOND 10
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/* SECTION: IPC */
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/* Using Semaphore */
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#define RT_USING_SEMAPHORE
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/* Using Mutex */
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#define RT_USING_MUTEX
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/* Using Event */
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#define RT_USING_EVENT
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/* Using MailBox */
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#define RT_USING_MAILBOX
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/* Using Message Queue */
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#define RT_USING_MESSAGEQUEUE
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/* SECTION: Memory Management */
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/* Using Memory Pool Management*/
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#define RT_USING_MEMPOOL
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/* Using Dynamic Heap Management */
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#define RT_USING_HEAP
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/* Using Small MM */
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#define RT_USING_SMALL_MEM
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/* SECTION: Device System */
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/* Using Device System */
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#define RT_USING_DEVICE
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/* RT_USING_UART */
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#define RT_USING_UART0
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#define RT_UART_RX_BUFFER_SIZE 64
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/* SECTION: Console options */
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/* the buffer size of console */
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#define RT_CONSOLEBUF_SIZE 128
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/* SECTION: finsh, a C-Express shell */
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/* Using FinSH as Shell*/
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#define RT_USING_FINSH
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/* Using symbol table */
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#define FINSH_USING_SYMTAB
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#define FINSH_USING_DESCRIPTION
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#define FINSH_DEVICE_NAME "uart"
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/* SECTION: device filesystem support */
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#define RT_USING_DFS
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#define RT_USING_DFS_ELMFAT
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/* the max number of mounted filesystem */
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#define DFS_FILESYSTEMS_MAX 2
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/* the max number of opened files */
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#define DFS_FD_MAX 4
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/* the max number of cached sector */
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#define DFS_CACHE_MAX_NUM 4
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/* SECTION: lwip, a lighwight TCP/IP protocol stack */
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/* #define RT_USING_LWIP */
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#define RT_LWIP_USING_RT_MEM
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/* Enable ICMP protocol*/
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#define RT_LWIP_ICMP
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/* Enable UDP protocol*/
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#define RT_LWIP_UDP
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/* Enable TCP protocol*/
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#define RT_LWIP_TCP
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/* Enable DNS */
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#define RT_LWIP_DNS
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/* the number of simulatenously active TCP connections*/
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#define RT_LWIP_TCP_PCB_NUM 5
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/* ip address of target*/
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#define RT_LWIP_IPADDR0 192
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#define RT_LWIP_IPADDR1 168
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#define RT_LWIP_IPADDR2 1
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#define RT_LWIP_IPADDR3 30
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/* gateway address of target*/
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#define RT_LWIP_GWADDR0 192
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#define RT_LWIP_GWADDR1 168
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#define RT_LWIP_GWADDR2 1
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#define RT_LWIP_GWADDR3 1
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/* mask address of target*/
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#define RT_LWIP_MSKADDR0 255
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#define RT_LWIP_MSKADDR1 255
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#define RT_LWIP_MSKADDR2 255
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#define RT_LWIP_MSKADDR3 0
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/* tcp thread options */
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#define RT_LWIP_TCPTHREAD_PRIORITY 12
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#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
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#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
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/* ethernet if thread options */
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#define RT_LWIP_ETHTHREAD_PRIORITY 15
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
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#define RT_LWIP_ETHTHREAD_STACKSIZE 512
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/* SECTION: RT-Thread/GUI */
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/* #define RT_USING_RTGUI */
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/* name length of RTGUI object */
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#define RTGUI_NAME_MAX 12
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/* support 16 weight font */
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#define RTGUI_USING_FONT16
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/* support Chinese font */
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#define RTGUI_USING_FONTHZ
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/* use DFS as file interface */
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#define RTGUI_USING_DFS_FILERW
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/* use font file as Chinese font */
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#define RTGUI_USING_HZ_FILE
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/* use small size in RTGUI */
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#define RTGUI_USING_SMALL_SIZE
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/* use mouse cursor */
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/* #define RTGUI_USING_MOUSE_CURSOR */
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/* default font size in RTGUI */
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#define RTGUI_DEFAULT_FONT_SIZE 16
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#endif
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import SCons.cpp
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# component options
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# make all component false
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RT_USING_FINSH = False
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RT_USING_DFS = False
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RT_USING_DFS_ELMFAT = False
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RT_USING_DFS_YAFFS2 = False
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RT_USING_LWIP = False
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RT_USING_WEBSERVER = False
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RT_USING_RTGUI = False
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# parse rtconfig.h to get used component
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PreProcessor = SCons.cpp.PreProcessor()
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f = file('rtconfig.h', 'r')
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contents = f.read()
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f.close()
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PreProcessor.process_contents(contents)
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rtconfig_ns = PreProcessor.cpp_namespace
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# finsh shell options
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if rtconfig_ns.has_key('RT_USING_FINSH'):
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RT_USING_FINSH = True
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# device virtual filesystem options
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if rtconfig_ns.has_key('RT_USING_DFS'):
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RT_USING_DFS = True
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if rtconfig_ns.has_key('RT_USING_DFS_ELMFAT'):
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RT_USING_DFS_ELMFAT = True
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if rtconfig_ns.has_key('RT_USING_DFS_YAFFS2'):
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RT_USING_DFS_YAFFS2 = True
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# lwip options
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if rtconfig_ns.has_key('RT_USING_LWIP'):
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RT_USING_LWIP = True
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if rtconfig_ns.has_key('RT_USING_WEBSERVER'):
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RT_USING_WEBSERVER = True
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# rtgui options
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if rtconfig_ns.has_key('RT_USING_RTGUI'):
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RT_USING_RTGUI = True
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# toolchains options
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ARCH='mips'
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CPU='jz47xx'
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CROSS_TOOL = 'gcc'
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PLATFORM = 'gcc'
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EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
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BUILD = 'debug'
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# toolchains
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PREFIX = 'mips-sde-elf-'
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CC = PREFIX + 'gcc'
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AS = PREFIX + 'gcc'
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AR = PREFIX + 'ar'
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LINK = PREFIX + 'gcc'
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TARGET_EXT = 'elf'
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SIZE = PREFIX + 'size'
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OBJDUMP = PREFIX + 'objdump'
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OBJCPY = PREFIX + 'objcopy'
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DEVICE = ' -mips32 -msoft-float'
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CFLAGS = DEVICE + ' -G0 -DRT_USING_MINILIBC -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
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AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
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LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-jz47xx.map,-cref,-u,Reset_Handler -T jz47xx_ram.ld'
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CPATH = ''
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LPATH = ''
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if BUILD == 'debug':
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CFLAGS += ' -O0 -gdwarf-2'
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AFLAGS += ' -gdwarf-2'
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else:
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CFLAGS += ' -O2'
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RT_USING_MINILIBC = True
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POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
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@ -0,0 +1,74 @@
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/*
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* File : startup.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
|
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* found in the file LICENSE in this distribution or at
|
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2010-06-25 Bernard first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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/**
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* @addtogroup jz47xx
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*/
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/*@{*/
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extern unsigned char __bss_start;
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extern unsigned char __bss_end;
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extern int rt_application_init(void);
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/**
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* This function will startup RT-Thread RTOS.
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*/
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void rtthread_startup(void)
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{
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/* init board */
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rt_hw_board_init();
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rt_show_version();
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/* init tick */
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rt_system_tick_init();
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/* init timer system */
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rt_system_timer_init();
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rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
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/* init scheduler system */
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rt_system_scheduler_init();
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#ifdef RT_USING_DEVICE
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/* init all device */
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rt_device_init_all();
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#endif
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/* init application */
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rt_application_init();
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#ifdef RT_USING_FINSH
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/* init finsh */
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finsh_system_init();
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finsh_set_device(FINSH_DEVICE_NAME);
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#endif
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/* init idle thread */
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rt_thread_idle_init();
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/* start scheduler */
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rt_system_scheduler_start();
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/* never reach here */
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return ;
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}
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/*@}*/
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@ -0,0 +1,354 @@
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#include <rthw.h>
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#include <rtthread.h>
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/**
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* @addtogroup Jz47xx
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*/
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/*@{*/
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#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
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#define UART_BAUDRATE 115200
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#define DEV_CLK 12000000
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/*
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* Define macros for UARTIER
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* UART Interrupt Enable Register
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*/
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#define UARTIER_RIE (1 << 0) /* 0: receive fifo "full" interrupt disable */
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#define UARTIER_TIE (1 << 1) /* 0: transmit fifo "empty" interrupt disable */
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#define UARTIER_RLIE (1 << 2) /* 0: receive line status interrupt disable */
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#define UARTIER_MIE (1 << 3) /* 0: modem status interrupt disable */
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#define UARTIER_RTIE (1 << 4) /* 0: receive timeout interrupt disable */
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/*
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* Define macros for UARTISR
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* UART Interrupt Status Register
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*/
|
||||
#define UARTISR_IP (1 << 0) /* 0: interrupt is pending 1: no interrupt */
|
||||
#define UARTISR_IID (7 << 1) /* Source of Interrupt */
|
||||
#define UARTISR_IID_MSI (0 << 1) /* Modem status interrupt */
|
||||
#define UARTISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
|
||||
#define UARTISR_IID_RDI (2 << 1) /* Receiver data interrupt */
|
||||
#define UARTISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
|
||||
#define UARTISR_FFMS (3 << 6) /* FIFO mode select, set when UARTFCR.FE is set to 1 */
|
||||
#define UARTISR_FFMS_NO_FIFO (0 << 6)
|
||||
#define UARTISR_FFMS_FIFO_MODE (3 << 6)
|
||||
|
||||
/*
|
||||
* Define macros for UARTFCR
|
||||
* UART FIFO Control Register
|
||||
*/
|
||||
#define UARTFCR_FE (1 << 0) /* 0: non-FIFO mode 1: FIFO mode */
|
||||
#define UARTFCR_RFLS (1 << 1) /* write 1 to flush receive FIFO */
|
||||
#define UARTFCR_TFLS (1 << 2) /* write 1 to flush transmit FIFO */
|
||||
#define UARTFCR_DMS (1 << 3) /* 0: disable DMA mode */
|
||||
#define UARTFCR_UUE (1 << 4) /* 0: disable UART */
|
||||
#define UARTFCR_RTRG (3 << 6) /* Receive FIFO Data Trigger */
|
||||
#define UARTFCR_RTRG_1 (0 << 6)
|
||||
#define UARTFCR_RTRG_4 (1 << 6)
|
||||
#define UARTFCR_RTRG_8 (2 << 6)
|
||||
#define UARTFCR_RTRG_15 (3 << 6)
|
||||
|
||||
/*
|
||||
* Define macros for UARTLCR
|
||||
* UART Line Control Register
|
||||
*/
|
||||
#define UARTLCR_WLEN (3 << 0) /* word length */
|
||||
#define UARTLCR_WLEN_5 (0 << 0)
|
||||
#define UARTLCR_WLEN_6 (1 << 0)
|
||||
#define UARTLCR_WLEN_7 (2 << 0)
|
||||
#define UARTLCR_WLEN_8 (3 << 0)
|
||||
#define UARTLCR_STOP (1 << 2) /* 0: 1 stop bit when word length is 5,6,7,8
|
||||
1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
|
||||
#define UARTLCR_PE (1 << 3) /* 0: parity disable */
|
||||
#define UARTLCR_PROE (1 << 4) /* 0: even parity 1: odd parity */
|
||||
#define UARTLCR_SPAR (1 << 5) /* 0: sticky parity disable */
|
||||
#define UARTLCR_SBRK (1 << 6) /* write 0 normal, write 1 send break */
|
||||
#define UARTLCR_DLAB (1 << 7) /* 0: access UARTRDR/TDR/IER 1: access UARTDLLR/DLHR */
|
||||
|
||||
/*
|
||||
* Define macros for UARTLSR
|
||||
* UART Line Status Register
|
||||
*/
|
||||
#define UARTLSR_DR (1 << 0) /* 0: receive FIFO is empty 1: receive data is ready */
|
||||
#define UARTLSR_ORER (1 << 1) /* 0: no overrun error */
|
||||
#define UARTLSR_PER (1 << 2) /* 0: no parity error */
|
||||
#define UARTLSR_FER (1 << 3) /* 0; no framing error */
|
||||
#define UARTLSR_BRK (1 << 4) /* 0: no break detected 1: receive a break signal */
|
||||
#define UARTLSR_TDRQ (1 << 5) /* 1: transmit FIFO half "empty" */
|
||||
#define UARTLSR_TEMT (1 << 6) /* 1: transmit FIFO and shift registers empty */
|
||||
#define UARTLSR_RFER (1 << 7) /* 0: no receive error 1: receive error in FIFO mode */
|
||||
|
||||
/*
|
||||
* Define macros for UARTMCR
|
||||
* UART Modem Control Register
|
||||
*/
|
||||
#define UARTMCR_DTR (1 << 0) /* 0: DTR_ ouput high */
|
||||
#define UARTMCR_RTS (1 << 1) /* 0: RTS_ output high */
|
||||
#define UARTMCR_OUT1 (1 << 2) /* 0: UARTMSR.RI is set to 0 and RI_ input high */
|
||||
#define UARTMCR_OUT2 (1 << 3) /* 0: UARTMSR.DCD is set to 0 and DCD_ input high */
|
||||
#define UARTMCR_LOOP (1 << 4) /* 0: normal 1: loopback mode */
|
||||
#define UARTMCR_MCE (1 << 7) /* 0: modem function is disable */
|
||||
|
||||
/*
|
||||
* Define macros for UARTMSR
|
||||
* UART Modem Status Register
|
||||
*/
|
||||
#define UARTMSR_DCTS (1 << 0) /* 0: no change on CTS_ pin since last read of UARTMSR */
|
||||
#define UARTMSR_DDSR (1 << 1) /* 0: no change on DSR_ pin since last read of UARTMSR */
|
||||
#define UARTMSR_DRI (1 << 2) /* 0: no change on RI_ pin since last read of UARTMSR */
|
||||
#define UARTMSR_DDCD (1 << 3) /* 0: no change on DCD_ pin since last read of UARTMSR */
|
||||
#define UARTMSR_CTS (1 << 4) /* 0: CTS_ pin is high */
|
||||
#define UARTMSR_DSR (1 << 5) /* 0: DSR_ pin is high */
|
||||
#define UARTMSR_RI (1 << 6) /* 0: RI_ pin is high */
|
||||
#define UARTMSR_DCD (1 << 7) /* 0: DCD_ pin is high */
|
||||
|
||||
/*
|
||||
* Define macros for SIRCR
|
||||
* Slow IrDA Control Register
|
||||
*/
|
||||
#define SIRCR_TSIRE (1 << 0) /* 0: transmitter is in UART mode 1: IrDA mode */
|
||||
#define SIRCR_RSIRE (1 << 1) /* 0: receiver is in UART mode 1: IrDA mode */
|
||||
#define SIRCR_TPWS (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
|
||||
1: 0 pulse width is 1.6us for 115.2Kbps */
|
||||
#define SIRCR_TXPL (1 << 3) /* 0: encoder generates a positive pulse for 0 */
|
||||
#define SIRCR_RXPL (1 << 4) /* 0: decoder interprets positive pulse as 0 */
|
||||
|
||||
struct rt_uart_jz
|
||||
{
|
||||
struct rt_device parent;
|
||||
|
||||
rt_uint32_t hw_base;
|
||||
rt_uint32_t irq;
|
||||
|
||||
/* buffer for reception */
|
||||
rt_uint8_t read_index, save_index;
|
||||
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
|
||||
}uart_device;
|
||||
|
||||
static void rt_uart_irqhandler(void)
|
||||
{
|
||||
rt_ubase_t level, isr;
|
||||
struct rt_uart_jz* uart = &uart_device;
|
||||
|
||||
/* read interrupt status and clear it */
|
||||
isr = UART_ISR(uart->hw_base);
|
||||
|
||||
if (isr & UARTISR_IID_RDI) /* Receive Data Available */
|
||||
{
|
||||
/* Receive Data Available */
|
||||
while (UART_LSR(uart->hw_base) & UARTLSR_DR)
|
||||
{
|
||||
uart->rx_buffer[uart->save_index] = UART_RDR(uart->hw_base);
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
uart->save_index ++;
|
||||
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
uart->save_index = 0;
|
||||
rt_hw_interrupt_enable(level);
|
||||
}
|
||||
|
||||
/* invoke callback */
|
||||
if(uart->parent.rx_indicate != RT_NULL)
|
||||
{
|
||||
rt_size_t length;
|
||||
if (uart->read_index > uart->save_index)
|
||||
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
|
||||
else
|
||||
length = uart->save_index - uart->read_index;
|
||||
|
||||
uart->parent.rx_indicate(&uart->parent, length);
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_init (rt_device_t dev)
|
||||
{
|
||||
rt_uint32_t baud_div;
|
||||
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
/* Init UART Hardware */
|
||||
UART_IER(uart->hw_base) = 0; /* clear interrupt */
|
||||
UART_FCR(uart->hw_base) = ~UARTFCR_UUE; /* disable UART unite */
|
||||
|
||||
/* Enable UART clock */
|
||||
|
||||
/* Set both receiver and transmitter in UART mode (not SIR) */
|
||||
UART_SIRCR(uart->hw_base) = ~(SIRCR_RSIRE | SIRCR_TSIRE);
|
||||
|
||||
/* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
|
||||
UART_LCR(uart->hw_base) = UARTLCR_WLEN_8;
|
||||
|
||||
/* set baudrate */
|
||||
baud_div = DEV_CLK / 16 / UART_BAUDRATE;
|
||||
UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
|
||||
|
||||
UART_DLHR(uart->hw_base) = (baud_div >> 8) & 0xff;
|
||||
UART_DLLR(uart->hw_base) = baud_div & 0xff;
|
||||
|
||||
UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
|
||||
|
||||
/* Enable UART unit, enable and clear FIFO */
|
||||
UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* Enable the UART Interrupt */
|
||||
UART_IER(uart->hw_base) |= (UARTIER_RIE | UARTIER_RTIE);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_uart_close(rt_device_t dev)
|
||||
{
|
||||
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* Disable the UART Interrupt */
|
||||
UART_IER(uart->hw_base) &= ~(UARTIER_RIE | UARTIER_RTIE);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
{
|
||||
rt_uint8_t* ptr;
|
||||
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
/* point to buffer */
|
||||
ptr = (rt_uint8_t*) buffer;
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
/* interrupt receive */
|
||||
rt_base_t level;
|
||||
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
if (uart->read_index != uart->save_index)
|
||||
{
|
||||
*ptr = uart->rx_buffer[uart->read_index];
|
||||
|
||||
uart->read_index ++;
|
||||
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
uart->read_index = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* no data in rx buffer */
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
break;
|
||||
}
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
|
||||
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
char *ptr;
|
||||
struct rt_uart_jz *uart = (struct rt_uart_jz*)dev;
|
||||
|
||||
RT_ASSERT(uart != RT_NULL);
|
||||
|
||||
ptr = (char*)buffer;
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
||||
{
|
||||
/* stream mode */
|
||||
while (size)
|
||||
{
|
||||
if (*ptr == '\n')
|
||||
{
|
||||
/* FIFO status, contain valid data */
|
||||
while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
|
||||
/* write data */
|
||||
UART_TDR(uart->hw_base) = '\r';
|
||||
}
|
||||
|
||||
/* FIFO status, contain valid data */
|
||||
while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
|
||||
/* write data */
|
||||
UART_TDR(uart->hw_base) = *ptr;
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while ( size != 0 )
|
||||
{
|
||||
/* FIFO status, contain valid data */
|
||||
while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
|
||||
|
||||
/* write data */
|
||||
UART_TDR(uart->hw_base) = *ptr;
|
||||
|
||||
ptr++;
|
||||
size--;
|
||||
}
|
||||
}
|
||||
|
||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||
}
|
||||
|
||||
void rt_hw_uart_init(void)
|
||||
{
|
||||
struct rt_uart_jz* uart;
|
||||
|
||||
/* get uart device */
|
||||
uart = &uart_device;
|
||||
|
||||
/* device initialization */
|
||||
uart->parent.type = RT_Device_Class_Char;
|
||||
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
|
||||
uart->read_index = uart->save_index = 0;
|
||||
|
||||
/* device interface */
|
||||
uart->parent.init = rt_uart_init;
|
||||
uart->parent.open = rt_uart_open;
|
||||
uart->parent.close = rt_uart_close;
|
||||
uart->parent.read = rt_uart_read;
|
||||
uart->parent.write = rt_uart_write;
|
||||
uart->parent.control = RT_NULL;
|
||||
uart->parent.private = RT_NULL;
|
||||
|
||||
rt_device_register(&uart->parent,
|
||||
"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
|
||||
}
|
||||
#endif /* end of UART */
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
void rt_hw_uart_init(void);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue