update dm9000 driver, init and isr.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@293 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
parent
0d6cd9bf51
commit
582dd70930
|
@ -24,8 +24,6 @@
|
||||||
//--------------------------------------------------------
|
//--------------------------------------------------------
|
||||||
|
|
||||||
#define DM9000_PHY 0x40 /* PHY address 0x01 */
|
#define DM9000_PHY 0x40 /* PHY address 0x01 */
|
||||||
#define RST_1() GPIO_SetBits(GPIOF,GPIO_Pin_6)
|
|
||||||
#define RST_0() GPIO_ResetBits(GPIOF,GPIO_Pin_6)
|
|
||||||
|
|
||||||
#define MAX_ADDR_LEN 6
|
#define MAX_ADDR_LEN 6
|
||||||
enum DM9000_PHY_mode
|
enum DM9000_PHY_mode
|
||||||
|
@ -155,6 +153,12 @@ void rt_dm9000_isr(int irqno)
|
||||||
{
|
{
|
||||||
rt_uint16_t int_status;
|
rt_uint16_t int_status;
|
||||||
rt_uint16_t last_io;
|
rt_uint16_t last_io;
|
||||||
|
rt_uint32_t eint_pend;
|
||||||
|
|
||||||
|
eint_pend = EINTPEND;
|
||||||
|
/* EINT7 for DM9000 */
|
||||||
|
if((eint_pend & 0x80) == 0x80)
|
||||||
|
{
|
||||||
|
|
||||||
last_io = DM9000_IO;
|
last_io = DM9000_IO;
|
||||||
|
|
||||||
|
@ -221,6 +225,10 @@ void rt_dm9000_isr(int irqno)
|
||||||
DM9000_IO = last_io;
|
DM9000_IO = last_io;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* clear EINT pending bit */
|
||||||
|
EINTPEND = eint_pend;
|
||||||
|
}
|
||||||
|
|
||||||
/* RT-Thread Device Interface */
|
/* RT-Thread Device Interface */
|
||||||
/* initialize the interface */
|
/* initialize the interface */
|
||||||
static rt_err_t rt_dm9000_init(rt_device_t dev)
|
static rt_err_t rt_dm9000_init(rt_device_t dev)
|
||||||
|
@ -575,10 +583,18 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
|
||||||
|
|
||||||
void rt_hw_dm9000_init()
|
void rt_hw_dm9000_init()
|
||||||
{
|
{
|
||||||
// GPFCON = 0x000055AA;
|
/* Set GPF7 as EINT7 */
|
||||||
// GPFUP = 0x000000FF;
|
GPFCON = GPFCON & (~(3 << 14)) | (2 << 14);
|
||||||
|
GPFUP = GPFUP | (1 << 7);
|
||||||
// BANKCON4 = ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC));
|
/* EINT7 High level interrupt */
|
||||||
|
EXTINT0 = (EXTINT0 & (~(0x7 << 28))) | (0x1 << 28);
|
||||||
|
/* Enable EINT7 */
|
||||||
|
EINTMASK = EINTMASK & (~(1<<7));
|
||||||
|
/* Set GPA15 as nGCS4 */
|
||||||
|
//GPACON |= 1 << 15;
|
||||||
|
/* DM9000 width 16, wait enable */
|
||||||
|
//BWSCON = BWSCON & (~(0x7<<16)) | (0x5<<16);
|
||||||
|
//BANKCON4 = (1<<13) | (1<<11) | (0x6<<8) | (1<<6) | (1<<4) | (0<<2) | (0);
|
||||||
|
|
||||||
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
|
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
|
||||||
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
||||||
|
@ -615,8 +631,8 @@ void rt_hw_dm9000_init()
|
||||||
eth_device_init(&(dm9000_device.parent), "e0");
|
eth_device_init(&(dm9000_device.parent), "e0");
|
||||||
|
|
||||||
/* instal interrupt */
|
/* instal interrupt */
|
||||||
// rt_hw_interrupt_install(INT_EXIT7, rt_dm9000_isr, RT_NULL);
|
rt_hw_interrupt_install(INTEINT4_7, rt_dm9000_isr, RT_NULL);
|
||||||
// rt_hw_interrupt_umask(INT_EXIT7);
|
rt_hw_interrupt_umask(INTEINT4_7);
|
||||||
}
|
}
|
||||||
|
|
||||||
void dm9000a(void)
|
void dm9000a(void)
|
||||||
|
|
|
@ -1,8 +1,8 @@
|
||||||
#ifndef __DM9000_H__
|
#ifndef __DM9000_H__
|
||||||
#define __DM9000_H__
|
#define __DM9000_H__
|
||||||
|
|
||||||
#define DM9000_IO_BASE 0x20000000
|
#define DM9000_IO_BASE 0x20000300
|
||||||
#define DM9000_DATA_BASE 0x20000004
|
#define DM9000_DATA_BASE 0x20000304
|
||||||
|
|
||||||
#define DM9000_IO (*((volatile rt_uint16_t *) DM9000_IO_BASE)) // CMD = 0
|
#define DM9000_IO (*((volatile rt_uint16_t *) DM9000_IO_BASE)) // CMD = 0
|
||||||
#define DM9000_DATA (*((volatile rt_uint16_t *) DM9000_DATA_BASE)) // CMD = 1
|
#define DM9000_DATA (*((volatile rt_uint16_t *) DM9000_DATA_BASE)) // CMD = 1
|
||||||
|
|
Loading…
Reference in New Issue