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chinesebear add bsp & libcpu

This commit is contained in:
chinesebear 2015-07-09 07:38:07 +08:00
parent dee31a7103
commit 4ad1b35537
25 changed files with 2748 additions and 0 deletions
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12
bsp/ls1cdev/SConscript Normal file
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from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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bsp/ls1cdev/SConstruct Normal file
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
if GetDepend('RT_USING_RTGUI'):
objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
# make a building
DoBuilding(TARGET, objs)

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bsp/ls1cdev/applications/SConscript Normal file
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from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

66
bsp/ls1cdev/applications/application.c Normal file
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/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
* 2011-08-08 lgnq modified for Loongson LS1B
* 2015-07-06 chinesebear modified for Loongson LS1C
*/
#include <rtthread.h>
#include <ls1c.h>
#ifdef RT_USING_COMPONENTS_INIT
#include <components.h>
#endif
#ifdef RT_USING_RTGUI
#include <rtgui/rtgui.h>
extern void rt_hw_dc_init(void);
#endif
void rt_init_thread_entry(void *parameter)
{
#ifdef RT_USING_RTGUI
{
rt_device_t dc;
/* init Display Controller */
rt_hw_dc_init();
/* find Display Controller device */
dc = rt_device_find("dc");
/* set Display Controller device as rtgui graphic driver */
rtgui_graphic_set_device(dc);
}
#endif
#ifdef RT_USING_COMPONENTS_INIT
/* initialization RT-Thread Components */
rt_components_init();
#endif
}
int rt_application_init(void)
{
rt_thread_t tid;
/* create initialization thread */
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
4096, 8, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}

93
bsp/ls1cdev/applications/startup.c Normal file
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/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
* 2011-08-08 lgnq modified for Loongson LS1B
* 2015-07-06 chinesebear modified for Loongson LS1C
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#define A_K0BASE 0x80000000
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
extern unsigned char __bss_end;
extern int rt_application_init(void);
extern void tlb_refill_exception(void);
extern void general_exception(void);
extern void irq_exception(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* init cache */
rt_hw_cache_init();
/* init hardware interrupt */
rt_hw_interrupt_init();
/* copy vector */
rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x20);
rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
/* init board */
rt_hw_board_init();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
#endif
/* init scheduler system */
rt_system_scheduler_init();
/* initialize timer */
rt_system_timer_init();
/* initialize timer thread */
rt_system_timer_thread_init();
/* init idle thread */
rt_thread_idle_init();
/* init application */
rt_application_init();
/* init finsh*/
#ifdef RT_USING_FINSH
finsh_system_init();
finsh_set_device("uart2");
#endif
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return;
}
/*@}*/

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from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
# remove no need file.
if GetDepend('RT_USING_RTGUI') == False:
SrcRemove(src, 'display_controller.c')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

114
bsp/ls1cdev/drivers/board.c Normal file
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/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
* 2011-08-08 lgnq modified for Loongson LS1B
* 2015-07-06 chinesebear modified for Loongson LS1C
*/
#include <rtthread.h>
#include <rthw.h>
#include "board.h"
#include "uart.h"
#include "ls1c.h"
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
/**
* This is the timer interrupt service routine.
*/
void rt_hw_timer_handler(void)
{
unsigned int count;
count = read_c0_compare();
write_c0_compare(count);
write_c0_count(0);
/* increase a OS tick */
rt_tick_increase();
}
/**
* This function will initial OS timer
*/
void rt_hw_timer_init(void)
{
write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
write_c0_count(0);
}
/**
* This function will initial sam7s64 board.
*/
void rt_hw_board_init(void)
{
#ifdef RT_USING_UART
/* init hardware UART device */
rt_hw_uart_init();
#endif
#ifdef RT_USING_CONSOLE
/* set console device */
rt_console_set_device("uart2");
#endif
/* init operating system timer */
rt_hw_timer_init();
rt_kprintf("current sr: 0x%08x\n", read_c0_status());
}
#define __raw_out_put(unr) \
while (*ptr) \
{ \
if (*ptr == '\n') \
{ \
/* FIFO status, contain valid data */ \
while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
/* write data */ \
UART_DAT(UART##unr##_BASE) = '\r'; \
} \
/* FIFO status, contain valid data */ \
while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
/* write data */ \
UART_DAT(UART##unr##_BASE) = *ptr; \
ptr ++; \
}
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
void rt_hw_console_output(const char *ptr)
{
#if defined(RT_USING_UART0)
__raw_out_put(0);
#elif defined(RT_USING_UART2)
__raw_out_put(2);
#elif defined(RT_USING_UART3)
__raw_out_put(3);
#endif
}
/*@}*/

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/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-06-25 Bernard first version
* 2011-08-08 lgnq modified for Loongson LS1B
* 2015-07-06 chinesebear modified for Loongson LS1C
*/
#ifndef __BOARD_H__
#define __BOARD_H__
void rt_hw_board_init(void);
/* 32M SDRAM */
#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024)
#define CPU_HZ (252 * 1000000)
#endif

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/*
* File : display_controller.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-09 lgnq first version for LS1B DC
*/
#include <rtthread.h>
#include "display_controller.h"
struct vga_struct vga_mode[] =
{
{/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, },
{/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, },
{/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, },
{/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, },
{/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, },
{/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, },
{/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, },
{/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, },
{/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, },
{/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, },
{/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, },
{/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, },
{/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, },
{/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, },
{/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, },
{/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, },
{/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, },
{/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, },
};
ALIGN(16)
volatile rt_uint16_t _rt_framebuffer[FB_YSIZE][FB_XSIZE];
static struct rt_device_graphic_info _dc_info;
#define abs(x) ((x<0)?(-x):x)
#define min(a,b) ((a<b)?a:b)
int caclulate_freq(long long XIN, long long PCLK)
{
int i;
long long clk, clk1;
int start, end;
int mi;
int pll,ctrl,div,div1,frac;
pll = PLL_FREQ;
ctrl = PLL_DIV_PARAM;
rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
// rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
start = -1;
end = 1;
for (i=start; i<=end; i++)
{
clk = (12+i+(pll&0x3f))*33333333/2;
div = clk/(long)PCLK/1000;
clk1 = (12+i+1+(pll&0x3f))*33333333/2;
div1 = clk1/(long)PCLK/1000;
if (div!=div1)
break;
}
if (div!=div1)
{
frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
}
else
{
clk = (12+start+(pll&0x3f))*33333333/2;
clk1 = (12+end+(pll&0x3f))*33333333/2;
if (abs((long)clk/div/1000-PCLK)<abs((long)clk1/(div+1)/1000-PCLK))
{
pll = (pll & ~0x3ff3f)|((pll&0x3f)+start);
ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31);
}
else
{
pll = (pll & ~0x3ff3f)|((pll&0x3f)+end);
ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31);
}
}
rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl);
ctrl |= 0x2a00;
PLL_DIV_PARAM = ctrl;
PLL_FREQ = pll;
rt_thread_delay(10);
// initserial(0);
// _probe_frequencies();
// rt_kprintf("cpu freq is %d\n",tgt_pipefreq());
return 0;
}
static rt_err_t rt_dc_init(rt_device_t dev)
{
int i, out, mode=-1;
int val;
for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
{
if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
{
mode=i;
#ifdef LS1FSOC
// out = caclulatefreq(APB_CLK/1000,vga_mode[i].pclk);
// rt_kprintf("out=%x\n",out);
/*inner gpu dc logic fifo pll ctrl,must large then outclk*/
// *(volatile int *)0xbfd00414 = out+1;
/*output pix1 clock pll ctrl*/
// *(volatile int *)0xbfd00410 = out;
/*output pix2 clock pll ctrl */
// *(volatile int *)0xbfd00424 = out;
#else
caclulate_freq(APB_CLK/1000, vga_mode[i].pclk);
#endif
break;
}
}
if (mode<0)
{
rt_kprintf("\n\n\nunsupported framebuffer resolution\n\n\n");
return;
}
DC_FB_CONFIG = 0x0;
DC_FB_CONFIG = 0x3; // // framebuffer configuration RGB565
DC_FB_BUFFER_ADDR0 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
DC_FB_BUFFER_ADDR1 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
DC_DITHER_CONFIG = 0x0;
DC_DITHER_TABLE_LOW = 0x0;
DC_DITHER_TABLE_HIGH = 0x0;
DC_PANEL_CONFIG = 0x80001311;
DC_PANEL_TIMING = 0x0;
DC_HDISPLAY = (vga_mode[mode].hfl<<16) | vga_mode[mode].hr;
DC_HSYNC = 0x40000000 | (vga_mode[mode].hse<<16) | vga_mode[mode].hss;
DC_VDISPLAY = (vga_mode[mode].vfl<<16) | vga_mode[mode].vr;
DC_VSYNC = 0x40000000 | (vga_mode[mode].vse<<16) | vga_mode[mode].vss;
#if defined(CONFIG_VIDEO_32BPP)
DC_FB_CONFIG = 0x00100104;
DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
#elif defined(CONFIG_VIDEO_16BPP)
DC_FB_CONFIG = 0x00100103;
DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
#elif defined(CONFIG_VIDEO_15BPP)
DC_FB_CONFIG = 0x00100102;
DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
#elif defined(CONFIG_VIDEO_12BPP)
DC_FB_CONFIG = 0x00100101;
DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
#else //640x480-32Bits
DC_FB_CONFIG = 0x00100104;
DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
#endif //32Bits
#ifdef LS1GSOC
/*fix ls1g dc
*first switch to tile mode
*change origin register to 0
*goback nomal mode
*/
{
val = DC_FB_CONFIG;
DC_FB_CONFIG = val | 0x10;
DC_FB_BUFFER_ORIGIN = 0;
DC_FB_BUFFER_ORIGIN;
rt_thread_delay(10);
DC_FB_CONFIG;
DC_FB_CONFIG = val;
}
#endif
return RT_EOK;
}
static rt_err_t rt_dc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
switch (cmd)
{
case RTGRAPHIC_CTRL_RECT_UPDATE:
break;
case RTGRAPHIC_CTRL_POWERON:
break;
case RTGRAPHIC_CTRL_POWEROFF:
break;
case RTGRAPHIC_CTRL_GET_INFO:
rt_memcpy(args, &_dc_info, sizeof(_dc_info));
break;
case RTGRAPHIC_CTRL_SET_MODE:
break;
}
return RT_EOK;
}
void rt_hw_dc_init(void)
{
rt_device_t dc = rt_malloc(sizeof(struct rt_device));
if (dc == RT_NULL)
{
rt_kprintf("dc == RT_NULL\n");
return; /* no memory yet */
}
_dc_info.bits_per_pixel = 16;
_dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
_dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
_dc_info.width = FB_XSIZE;
_dc_info.height = FB_YSIZE;
/* init device structure */
dc->type = RT_Device_Class_Graphic;
dc->init = rt_dc_init;
dc->open = RT_NULL;
dc->close = RT_NULL;
dc->control = rt_dc_control;
dc->user_data = (void*)&_dc_info;
/* register Display Controller device to RT-Thread */
rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
}

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/*
* File : display_controller.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version for LS1B
* 2015-07-06 chinesebear modified for loongson 1c
*/
#ifndef __DISPLAY_CONTROLLER_H__
#define __DISPLAY_CONTROLLER_H__
#include <rtthread.h>
#include "ls1c.h"
#define DC_BASE 0xBC301240 //Display Controller
/* Frame Buffer registers */
#define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
#define DC_HSYNC __REG32(DC_BASE + 0x1E0)
#define DC_VDISPLAY __REG32(DC_BASE + 0x240)
#define DC_VSYNC __REG32(DC_BASE + 0x260)
#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340)
/* Display Controller driver for 1024x768 16bit */
#define FB_XSIZE 1024
#define FB_YSIZE 768
#define CONFIG_VIDEO_16BPP
#define APB_CLK 33333333
#define K1BASE 0xA0000000
#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
#define HW_FB_ADDR KSEG1(_rt_framebuffer)
#define HW_FB_PIXEL(x, y) *(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2)
struct vga_struct
{
long pclk;
int hr,hss,hse,hfl;
int vr,vss,vse,vfl;
};
#endif

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/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version
* 2015-07-09 chinesebear modified for loongson 1c
*/
#include <rthw.h>
#include <rtthread.h>
#include "uart.h"
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
struct rt_uart_ls1c
{
struct rt_device parent;
rt_uint32_t hw_base;
rt_uint32_t irq;
/* buffer for reception */
rt_uint8_t read_index, save_index;
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
}uart_device;
static void rt_uart_irqhandler(int irqno, void *param)
{
rt_ubase_t level;
rt_uint8_t isr;
struct rt_uart_ls1c *uart = &uart_device;
/* read interrupt status and clear it */
isr = UART_IIR(uart->hw_base);
isr = (isr >> 1) & 0x3;
/* receive data available */
if (isr & 0x02)
{
/* Receive Data Available */
while (UART_LSR(uart->hw_base) & UARTLSR_DR)
{
uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
level = rt_hw_interrupt_disable();
uart->save_index ++;
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
uart->save_index = 0;
rt_hw_interrupt_enable(level);
}
/* invoke callback */
if (uart->parent.rx_indicate != RT_NULL)
{
rt_size_t length;
if (uart->read_index > uart->save_index)
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
else
length = uart->save_index - uart->read_index;
uart->parent.rx_indicate(&uart->parent, length);
}
}
return;
}
static rt_err_t rt_uart_init(rt_device_t dev)
{
rt_uint32_t baud_div;
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
//#if 0
/* init UART Hardware */
UART_IER(uart->hw_base) = 0; /* clear interrupt */
UART_FCR(uart->hw_base) = 0xc3; /* reset UART Rx/Tx */
/* enable UART clock */
/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
UART_LCR(uart->hw_base) = 0x80;
/* set baudrate */
baud_div = DEV_CLK / 16 / UART_BAUDRATE /2;
UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
UART_LSB(uart->hw_base) = baud_div & 0xff;
UART_LCR(uart->hw_base) = 0x03;
/* Enable UART unit, enable and clear FIFO */
//UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
/* enable RX interrupt */
UART_IER(uart->hw_base) = UARTIER_IRXE|UARTIER_ILE;
//#endif
return RT_EOK;
}
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
{
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Enable the UART Interrupt */
UART_IER(uart->hw_base) |= UARTIER_IRXE;
/* install interrupt */
rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
rt_hw_interrupt_umask(uart->irq);
}
return RT_EOK;
}
static rt_err_t rt_uart_close(rt_device_t dev)
{
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
/* Disable the UART Interrupt */
UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
}
return RT_EOK;
}
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
rt_uint8_t *ptr;
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
/* point to buffer */
ptr = (rt_uint8_t *)buffer;
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
{
while (size)
{
/* interrupt receive */
rt_base_t level;
/* disable interrupt */
level = rt_hw_interrupt_disable();
if (uart->read_index != uart->save_index)
{
*ptr = uart->rx_buffer[uart->read_index];
uart->read_index ++;
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
uart->read_index = 0;
}
else
{
/* no data in rx buffer */
/* enable interrupt */
rt_hw_interrupt_enable(level);
break;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
ptr ++;
size --;
}
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
}
return 0;
}
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
char *ptr;
struct rt_uart_ls1c *uart = (struct rt_uart_ls1c *)dev;
RT_ASSERT(uart != RT_NULL);
ptr = (char *)buffer;
if (dev->flag & RT_DEVICE_FLAG_STREAM)
{
/* stream mode */
while (size)
{
if (*ptr == '\n')
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = '\r';
}
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr ++;
size --;
}
}
else
{
while (size != 0)
{
/* FIFO status, contain valid data */
while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
/* write data */
UART_DAT(uart->hw_base) = *ptr;
ptr++;
size--;
}
}
return (rt_size_t)ptr - (rt_size_t)buffer;
}
void rt_hw_uart_init(void)
{
struct rt_uart_ls1c *uart;
/* get uart device */
uart = &uart_device;
/* device initialization */
uart->parent.type = RT_Device_Class_Char;
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
uart->read_index = uart->save_index = 0;
#if defined(RT_USING_UART0)
uart->hw_base = UART0_BASE;
uart->irq = LS1C_UART0_IRQ;
#elif defined(RT_USING_UART2)
uart->hw_base = UART2_BASE;
uart->irq = LS1C_UART2_IRQ;
#elif defined(RT_USING_UART3)
uart->hw_base = UART3_BASE;
uart->irq = LS1C_UART3_IRQ;
#endif
/* device interface */
uart->parent.init = rt_uart_init;
uart->parent.open = rt_uart_open;
uart->parent.close = rt_uart_close;
uart->parent.read = rt_uart_read;
uart->parent.write = rt_uart_write;
uart->parent.control = RT_NULL;
uart->parent.user_data = RT_NULL;
rt_device_register(&uart->parent, "uart2",
RT_DEVICE_FLAG_RDWR |
RT_DEVICE_FLAG_STREAM |
RT_DEVICE_FLAG_INT_RX);
}
#endif /* end of UART */
/*@}*/

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/*
* File : uart.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version for LS1B
* 2015-07-06 chinesebear modified for loongson 1c
*/
#ifndef __UART_H__
#define __UART_H__
#include "ls1c.h"
#define DEV_CLK 252000000 // 252MHz
#define UART_BAUDRATE 115200
#define UART0_BASE 0xBFE40000
//#define UART0_1_BASE 0xBFE41000
#define UART1_BASE 0xBFE44000
#define UART2_BASE 0xBFE48000
#define UART3_BASE 0xBFE4C000
#define UART4_BASE 0xBFE4C400
#define UART5_BASE 0xBFE4C500
#define UART6_BASE 0xBFE4C600
#define UART7_BASE 0xBFE4C700
#define UART8_BASE 0xBFE4C800
#define UART9_BASE 0xBFE4C900
#define UART10_BASE 0xBFE4Ca00
#define UART11_BASE 0xBFE4Cb00
/* UART registers */
#define UART_DAT(base) __REG8(base + 0x00)
#define UART_IER(base) __REG8(base + 0x01)
#define UART_IIR(base) __REG8(base + 0x02)
#define UART_FCR(base) __REG8(base + 0x02)
#define UART_LCR(base) __REG8(base + 0x03)
#define UART_MCR(base) __REG8(base + 0x04)
#define UART_LSR(base) __REG8(base + 0x05)
#define UART_MSR(base) __REG8(base + 0x06)
#define UART_LSB(base) __REG8(base + 0x00)
#define UART_MSB(base) __REG8(base + 0x01)
/* UART0 registers */
#define UART0_DAT __REG8(UART0_BASE + 0x00)
#define UART0_IER __REG8(UART0_BASE + 0x01)
#define UART0_IIR __REG8(UART0_BASE + 0x02)
#define UART0_FCR __REG8(UART0_BASE + 0x02)
#define UART0_LCR __REG8(UART0_BASE + 0x03)
#define UART0_MCR __REG8(UART0_BASE + 0x04)
#define UART0_LSR __REG8(UART0_BASE + 0x05)
#define UART0_MSR __REG8(UART0_BASE + 0x06)
#define UART0_LSB __REG8(UART0_BASE + 0x00)
#define UART0_MSB __REG8(UART0_BASE + 0x01)
/* UART1 registers */
#define UART1_DAT __REG8(UART1_BASE + 0x00)
#define UART1_IER __REG8(UART1_BASE + 0x01)
#define UART1_IIR __REG8(UART1_BASE + 0x02)
#define UART1_FCR __REG8(UART1_BASE + 0x02)
#define UART1_LCR __REG8(UART1_BASE + 0x03)
#define UART1_MCR __REG8(UART1_BASE + 0x04)
#define UART1_LSR __REG8(UART1_BASE + 0x05)
#define UART1_MSR __REG8(UART1_BASE + 0x06)
#define UART1_LSB __REG8(UART1_BASE + 0x00)
#define UART1_MSB __REG8(UART1_BASE + 0x01)
/* UART interrupt enable register value */
#define UARTIER_IME (1 << 3)
#define UARTIER_ILE (1 << 2)
#define UARTIER_ITXE (1 << 1)
#define UARTIER_IRXE (1 << 0)
/* UART line control register value */
#define UARTLCR_DLAB (1 << 7)
#define UARTLCR_BCB (1 << 6)
#define UARTLCR_SPB (1 << 5)
#define UARTLCR_EPS (1 << 4)
#define UARTLCR_PE (1 << 3)
#define UARTLCR_SB (1 << 2)
/* UART line status register value */
#define UARTLSR_ERROR (1 << 7)
#define UARTLSR_TE (1 << 6)
#define UARTLSR_TFE (1 << 5)
#define UARTLSR_BI (1 << 4)
#define UARTLSR_FE (1 << 3)
#define UARTLSR_PE (1 << 2)
#define UARTLSR_OE (1 << 1)
#define UARTLSR_DR (1 << 0)
void rt_hw_uart_init(void);
#endif

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this bsp is based on LS1C for smart loong V1.0
by chinesebear swubear@163.com
# download script for RT-Thread
ifaddr syn0 192.168.1.100;load tftp://192.168.1.5/rtthread.elf;g

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#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 10
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND 100
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
// #define RT_THREAD_DEBUG
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
#define RT_USING_OVERFLOW_CHECK
// <bool name="RT_USING_INTERRUPT_INFO" description="Show more interrupt description" default="true" />
#define RT_USING_INTERRUPT_INFO
// </section>
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
#define RT_USING_HOOK
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND 10
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
#define RT_USING_SEMAPHORE
// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
#define RT_USING_MUTEX
// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
#define RT_USING_EVENT
// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
#define RT_USING_MAILBOX
// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
#define RT_USING_MESSAGEQUEUE
// </section>
// <section name="MM" description="Memory Management" default="always" >
// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
#define RT_USING_MEMPOOL
// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
#define RT_USING_MEMHEAP
// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
#define RT_USING_HEAP
// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
#define RT_USING_SMALL_MEM
// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
// #define RT_USING_SLAB
// </section>
// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
#define RT_USING_DEVICE
// <bool name="RT_USING_UART" description="Using UART" default="true" />
#define RT_USING_UART
// <bool name="RT_USING_UART2" description="Using UART0" default="true" />
#define RT_USING_UART2
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 64
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart2"
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
#define RT_USING_COMPONENTS_INIT
// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
#define RT_USING_FINSH
// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
#define FINSH_USING_SYMTAB
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
// <bool name="RT_USING_NEWLIB" description="Using newlib library, only available under GNU GCC" default="true" />
// #define RT_USING_NEWLIB
// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
// #define RT_USING_PTHREADS
// </section>
// <section name="RT_USING_DFS" description="Device file system" default="true" >
// #define RT_USING_DFS
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
// #define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">2</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 1
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="256" />
#define RT_DFS_ELM_MAX_LFN 64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
// #define RT_USING_DFS_UFFS
// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
// #define RT_USING_DFS_DEVFS
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.3.108:/"
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
// #define RT_USING_LWIP
// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
#define RT_LWIP_ICMP
// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
// #define RT_LWIP_IGMP
// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
#define RT_LWIP_UDP
// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
#define RT_LWIP_TCP
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM 4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
#define RT_LWIP_TCP_PCB_NUM 3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF 2048
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND 2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
#define RT_LWIP_TCP_SEG_NUM 4
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY 12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY 14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE 512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 3
#define RT_LWIP_IPADDR3 108
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 3
#define RT_LWIP_GWADDR3 1
// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
// </section>
// <section name="RT_USING_MODULE" description="Application module" default="true" >
// #define RT_USING_MODULE
// <bool name="RT_USING_LIBDL" description="Using dynamic library" default="true" />
// #define RT_USING_LIBDL
// </section>
// <section name="RT_USING_RTGUI" description="RTGUI, a graphic user interface" default="true" >
// #define RT_USING_RTGUI
// <integer name="RTGUI_NAME_MAX" description="Maximal size of RTGUI object name length" default="16" />
#define RTGUI_NAME_MAX 16
// <bool name="RTGUI_USING_FONT16" description="Support 16 weight font" default="true" />
#define RTGUI_USING_FONT16
// <bool name="RTGUI_USING_FONT12" description="Support 12 weight font" default="true" />
#define RTGUI_USING_FONT12
// <bool name="RTGUI_USING_FONTHZ" description="Support Chinese font" default="true" />
#define RTGUI_USING_FONTHZ
// <bool name="RTGUI_USING_DFS_FILERW" description="Using DFS as file interface " default="true" />
#define RTGUI_USING_DFS_FILERW
// <bool name="RTGUI_USING_HZ_FILE" description="Using font file as Chinese font" default="false" />
// #define RTGUI_USING_HZ_FILE
// <bool name="RTGUI_USING_HZ_BMP" description="Using Chinese bitmap font" default="true" />
#define RTGUI_USING_HZ_BMP
// <bool name="RTGUI_USING_SMALL_SIZE" description="Using small size in RTGUI" default="false" />
#define RTGUI_USING_SMALL_SIZE
// <bool name="RTGUI_USING_MOUSE_CURSOR" description="Using mouse cursor in RTGUI" default="false" />
// #define RTGUI_USING_MOUSE_CURSOR
// <bool name="RTGUI_IMAGE_XPM" description="Using xpm image in RTGUI" default="true" />
#define RTGUI_IMAGE_XPM
// <bool name="RTGUI_IMAGE_JPEG" description="Using jpeg image in RTGUI" default="true" />
// #define RTGUI_IMAGE_JPEG
// <bool name="RTGUI_IMAGE_PNG" description="Using png image in RTGUI" default="true" />
// #define RTGUI_IMAGE_PNG
// <bool name="RTGUI_IMAGE_BMP" description="Using bmp image in RTGUI" default="true" />
#define RTGUI_IMAGE_BMP
// </section>
// </RDTConfigurator>
#endif

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import os
# CPU options
ARCH='mips'
CPU ='loongson_1c'
# toolchains options
CROSS_TOOL = 'gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = '/opt/opt/gcc-4.3-ls232/bin'
else:
print '================ERROR============================'
print 'Not support %s yet!' % CROSS_TOOL
print '================================================='
exit(0)
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
PREFIX = 'mipsel-linux-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
READELF = PREFIX + 'readelf'
DEVICE = ' -mips32'
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp -DSYSTEM_STACK=0x80003fe8'
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1b_ram.lds'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
READELF_ACTION = READELF + ' -a $TARGET > rtt.map\n'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

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/*
* File : cache.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
* 2015-07-08 chinesebear modified for loongson 1c
*/
#include "../common/mipsregs.h"
#define K0BASE 0x80000000
#define PRID_LS1C 0x4220
extern void Clear_TagLo (void);
extern void Invalidate_Icache_Ls1c(unsigned int);
extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
extern void Writeback_Invalidate_Dcache(unsigned int);
typedef struct cacheinfo_t
{
unsigned int icache_size;
unsigned int dcache_size;
unsigned int icacheline_size;
unsigned int dcacheline_size;
} cacheinfo_t ;
typedef struct cacheop_t
{
void (*Clear_TagLo) (void);
void (*Invalidate_Icache) (unsigned int);
void (*Invalidate_Dcache_Fill) (unsigned int);
void (*Invalidate_Dcache_ClearTag) (unsigned int);
void (*Init_Cache)(void);
} cacheop_t ;
static cacheop_t cacheop, *pcacheop;
static cacheinfo_t cacheinfo, *pcacheinfo;
int identify_cpu(void)
{
unsigned int cpu_id;
pcacheop = &cacheop;
pcacheinfo = &cacheinfo;
rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
cpu_id = read_c0_prid();
switch (cpu_id)
{
case PRID_LS1C:
rt_kprintf("CPU:Loongson 1C\n");
pcacheop->Clear_TagLo = Clear_TagLo;
pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
break;
default:
rt_kprintf("Unknown CPU type, system halted!\n");
while (1)
{
;
}
break;
}
return 0;
}
void probe_cache(void)
{
unsigned int config1 = read_c0_config1();
unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
if ((icache_line_size = ((config1 >> 19) & 7)))
icache_line_size = 2 << icache_line_size;
else
icache_line_size = icache_line_size;
icache_sets = 64 << ((config1 >> 22) & 7);
icache_ways = 1 + ((config1 >> 16) & 7);
icache_size = icache_sets * icache_ways * icache_line_size;
if ((dcache_line_size = ((config1 >> 10) & 7)))
dcache_line_size = 2 << dcache_line_size;
else
dcache_line_size = dcache_line_size;
dcache_sets = 64 << ((config1 >> 13) & 7);
dcache_ways = 1 + ((config1 >> 7) & 7);
dcache_size = dcache_sets * dcache_ways * dcache_line_size;
rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
pcacheinfo->icache_size = icache_size;
pcacheinfo->dcache_size = dcache_size;
pcacheinfo->icacheline_size = icache_line_size;
pcacheinfo->dcacheline_size = dcache_line_size;
return ;
}
void invalidate_writeback_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
Writeback_Invalidate_Dcache(start); //hit writeback invalidate
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_writeback_dcache(unsigned long addr, int size)
{
unsigned long start, end;
start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
while (start <end)
{
Writeback_Invalidate_Dcache(start);
start += pcacheinfo->dcacheline_size;
}
}
void invalidate_icache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->icache_size);
while (start < end)
{
pcacheop->Invalidate_Icache(start);
start += pcacheinfo->icacheline_size;
}
}
void invalidate_dcache_all(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start <end)
{
Invalidate_Dcache_Fill_Gc3210I(start);
start += pcacheinfo->icacheline_size;
}
}
//with cache disabled
void init_dcache(void)
{
unsigned int start = K0BASE;
unsigned int end = (start + pcacheinfo->dcache_size);
while (start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
}
void rt_hw_cache_init(void)
{
unsigned int start, end;
/* 1. identify cpu and probe cache */
identify_cpu();
probe_cache();
start = K0BASE;
end = (start + pcacheinfo->icache_size);
/*
* 2. clear CP0 taglo/taghi register;
*/
pcacheop->Clear_TagLo();
/*
* 3. invalidate instruction cache;
*/
while (start < end)
{
pcacheop->Invalidate_Icache(start); //index invalidate icache
start += pcacheinfo->icacheline_size;
}
/*
* 4. invalidate data cache;
*/
start = K0BASE;
end = (start + pcacheinfo->dcache_size);
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_Fill(start); //index invalidate dcache
start += pcacheinfo->dcacheline_size;
}
start = K0BASE;
while(start < end)
{
pcacheop->Invalidate_Dcache_ClearTag(start);
start += pcacheinfo->dcacheline_size;
}
/* enable cache */
enable_cpu_cache();
rt_kprintf("enable cpu cache done\n");
return ;
}

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/*
* File : cache.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2011-08-08 lgnq modified for LS1B
*/
#ifndef __CACHE_H__
#define __CACHE_H__
/*
* Cache Operations
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_D 0x0d
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Fill 0x14
#define Hit_Writeback_Inv_D 0x15
/* 0x16 is unused */
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/* 0x1a is unused */
#define Hit_Writeback_SD 0x1b
/* 0x1c is unused */
/* 0x1e is unused */
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
#endif

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/*
* File : cache_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
* 2015-07-08 chinesebear port to Loongson LS1C
*/
#include "../common/mipsregs.h"
#include "../common/mips.inc"
#include "../common/asm.h"
#include "cache.h"
.ent cache_init
.global cache_init
.set noreorder
cache_init:
move t1,ra
####part 2####
cache_detect_4way:
mfc0 t4, CP0_CONFIG
andi t5, t4, 0x0e00
srl t5, t5, 9 #ic
andi t6, t4, 0x01c0
srl t6, t6, 6 #dc
addiu t8, $0, 1
addiu t9, $0, 2
#set dcache way
beq t6, $0, cache_d1way
addiu t7, $0, 1 #1 way
beq t6, t8, cache_d2way
addiu t7, $0, 2 #2 way
beq $0, $0, cache_d4way
addiu t7, $0, 4 #4 way
cache_d1way:
beq $0, $0, 1f
addiu t6, t6, 12 #1 way
cache_d2way:
beq $0, $0, 1f
addiu t6, t6, 11 #2 way
cache_d4way:
addiu t6, t6, 10 #4 way (10), 2 way(11), 1 way(12)
1: #set icache way
beq t5, $0, cache_i1way
addiu t3, $0, 1 #1 way
beq t5, t8, cache_i2way
addiu t3, $0, 2 #2 way
beq $0, $0, cache_i4way
addiu t3, $0, 4 #4 way
cache_i1way:
beq $0, $0, 1f
addiu t5, t5, 12
cache_i2way:
beq $0, $0, 1f
addiu t5, t5, 11
cache_i4way:
addiu t5, t5, 10 #4 way (10), 2 way(11), 1 way(12)
1: addiu t4, $0, 1
sllv t6, t4, t6
sllv t5, t4, t5
#if 0
la t0, memvar
sw t7, 0x0(t0) #ways
sw t5, 0x4(t0) #icache size
sw t6, 0x8(t0) #dcache size
#endif
####part 3####
.set mips3
lui a0, 0x8000
addu a1, $0, t5
addu a2, $0, t6
cache_init_d2way:
#a0=0x80000000, a1=icache_size, a2=dcache_size
#a3, v0 and v1 used as local registers
mtc0 $0, CP0_TAGHI
addu v0, $0, a0
addu v1, a0, a2
1: slt a3, v0, v1
beq a3, $0, 1f
nop
mtc0 $0, CP0_TAGLO
beq t7, 1, 4f
cache Index_Store_Tag_D, 0x0(v0) # 1 way
beq t7, 2 ,4f
cache Index_Store_Tag_D, 0x1(v0) # 2 way
cache Index_Store_Tag_D, 0x2(v0) # 4 way
cache Index_Store_Tag_D, 0x3(v0)
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_flush_i2way:
addu v0, $0, a0
addu v1, a0, a1
1: slt a3, v0, v1
beq a3, $0, 1f
nop
beq t3, 1, 4f
cache Index_Invalidate_I, 0x0(v0) # 1 way
beq t3, 2, 4f
cache Index_Invalidate_I, 0x1(v0) # 2 way
cache Index_Invalidate_I, 0x2(v0)
cache Index_Invalidate_I, 0x3(v0) # 4 way
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_flush_d2way:
addu v0, $0, a0
addu v1, a0, a2
1: slt a3, v0, v1
beq a3, $0, 1f
nop
beq t7, 1, 4f
cache Index_Writeback_Inv_D, 0x0(v0) #1 way
beq t7, 2, 4f
cache Index_Writeback_Inv_D, 0x1(v0) # 2 way
cache Index_Writeback_Inv_D, 0x2(v0)
cache Index_Writeback_Inv_D, 0x3(v0) # 4 way
4: beq $0, $0, 1b
addiu v0, v0, 0x20
1:
cache_init_finish:
jr t1
nop
.set reorder
.end cache_init
###########################
# Enable CPU cache #
###########################
LEAF(enable_cpu_cache)
.set noreorder
mfc0 t0, CP0_CONFIG
nop
and t0, ~0x03
or t0, 0x03
mtc0 t0, CP0_CONFIG
nop
.set reorder
j ra
END (enable_cpu_cache)
###########################
# disable CPU cache #
###########################
LEAF(disable_cpu_cache)
.set noreorder
mfc0 t0, CP0_CONFIG
nop
and t0, ~0x03
or t0, 0x2
mtc0 t0, CP0_CONFIG
nop
.set reorder
j ra
END (disable_cpu_cache)
/**********************************/
/* Invalidate Instruction Cache */
/**********************************/
LEAF(Clear_TagLo)
.set noreorder
mtc0 zero, CP0_TAGLO
nop
.set reorder
j ra
END(Clear_TagLo)
.set mips3
/**********************************/
/* Invalidate Instruction Cache */
/**********************************/
LEAF(Invalidate_Icache_Ls1c)
.set noreorder
cache Index_Invalidate_I,0(a0)
cache Index_Invalidate_I,1(a0)
cache Index_Invalidate_I,2(a0)
cache Index_Invalidate_I,3(a0)
.set reorder
j ra
END(Invalidate_Icache_Ls1c)
/**********************************/
/* Invalidate Data Cache */
/**********************************/
LEAF(Invalidate_Dcache_ClearTag_Ls1c)
.set noreorder
cache Index_Store_Tag_D, 0(a0) # BDSLOT: clear tag
cache Index_Store_Tag_D, 1(a0) # BDSLOT: clear tag
.set reorder
j ra
END(Invalidate_Dcache_ClearTag_Ls1c)
LEAF(Invalidate_Dcache_Fill_Ls1c)
.set noreorder
cache Index_Writeback_Inv_D, 0(a0) # BDSLOT: clear tag
cache Index_Writeback_Inv_D, 1(a0) # BDSLOT: clear tag
.set reorder
j ra
END(Invalidate_Dcache_Fill_Ls1c)
LEAF(Writeback_Invalidate_Dcache)
.set noreorder
cache Hit_Writeback_Inv_D, (a0)
.set reorder
j ra
END(Writeback_Invalidate_Dcache)
.set mips0

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/*
* File : context_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-11 bernard port to Loongson SoC3210
* 2011-08-08 lgnq port to Loongson LS1B
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
.section ".text", "ax"
.set noreorder
/*
* rt_base_t rt_hw_interrupt_disable()
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
mfc0 v0, CP0_STATUS
and v1, v0, 0xfffffffe
mtc0 v1, CP0_STATUS
jr ra
nop
/*
* void rt_hw_interrupt_enable(rt_base_t level)
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
mtc0 a0, CP0_STATUS
jr ra
nop
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
mtc0 ra, CP0_EPC
SAVE_ALL
sw sp, 0(a0) /* store sp in preempted tasks TCB */
lw sp, 0(a1) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_to(rt_uint32 to)/*
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
lw sp, 0(a0) /* get new task stack pointer */
RESTORE_ALL_AND_RET
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
la t0, rt_thread_switch_interrupt_flag
lw t1, 0(t0)
nop
bnez t1, _reswitch
nop
li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
sw t1, 0(t0)
la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
sw a0, 0(t0)
_reswitch:
la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
sw a1, 0(t0)
jr ra
nop
/*
* void rt_hw_context_switch_interrupt_do(rt_base_t flag)
*/
.globl rt_interrupt_enter
.globl rt_interrupt_leave
.globl mips_irq_handle
mips_irq_handle:
SAVE_ALL
mfc0 t0, CP0_CAUSE
and t1, t0, 0xff
bnez t1, spurious_interrupt /* check exception */
nop
/* let k0 keep the current context sp */
move k0, sp
/* switch to kernel stack */
li sp, SYSTEM_STACK
jal rt_interrupt_enter
nop
jal rt_interrupt_dispatch
nop
jal rt_interrupt_leave
nop
/* switch sp back to thread's context */
move sp, k0
/*
* if rt_thread_switch_interrupt_flag set, jump to
* rt_hw_context_switch_interrupt_do and don't return
*/
la k0, rt_thread_switch_interrupt_flag
lw k1, 0(k0)
beqz k1, spurious_interrupt
nop
sw zero, 0(k0) /* clear flag */
nop
/*
* switch to the new thread
*/
la k0, rt_interrupt_from_thread
lw k1, 0(k0)
nop
sw sp, 0(k1) /* store sp in preempted tasks's TCB */
la k0, rt_interrupt_to_thread
lw k1, 0(k0)
nop
lw sp, 0(k1) /* get new task's stack pointer */
j spurious_interrupt
nop
spurious_interrupt:
RESTORE_ALL_AND_RET
.set reorder

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/*
* File : cpuport.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-07-09 Bernard first version
* 2010-09-11 Bernard add CPU reset implementation
* 2015-07-06 chinesebear modified for loongson 1c
*/
#include <rtthread.h>
#include "ls1c.h"
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
/**
* this function will reset CPU
*
*/
void rt_hw_cpu_reset(void)
{
/* open the watch-dog */
WDT_EN = 0x01; /* watch dog enable */
WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
WDT_SET = 0x01; /* watch dog start */
rt_kprintf("reboot system...\n");
while (1);
}
/**
* this function will shutdown CPU
*
*/
void rt_hw_cpu_shutdown(void)
{
rt_kprintf("shutdown...\n");
while (1);
}
extern rt_uint32_t cp0_get_cause(void);
extern rt_uint32_t cp0_get_status(void);
extern rt_uint32_t cp0_get_hi(void);
extern rt_uint32_t cp0_get_lo(void);
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
static rt_uint32_t g_sr = 0;
if (g_sr == 0)
{
g_sr = cp0_get_status();
g_sr &= 0xfffffffe;
g_sr |= 0x8401;
}
/** Start at stack top */
stk = (rt_uint32_t *)stack_addr;
*(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */
*(--stk) = (rt_uint32_t) 0xeeee; /* c0_cause */
*(--stk) = (rt_uint32_t) 0xffff; /* c0_badvaddr */
*(--stk) = (rt_uint32_t) cp0_get_lo(); /* lo */
*(--stk) = (rt_uint32_t) cp0_get_hi(); /* hi */
*(--stk) = (rt_uint32_t) g_sr; /* C0_SR: HW2 = En, IE = En */
*(--stk) = (rt_uint32_t) texit; /* ra */
*(--stk) = (rt_uint32_t) 0x0000001e; /* s8 */
*(--stk) = (rt_uint32_t) stack_addr; /* sp */
*(--stk) = (rt_uint32_t) 0x0000001c; /* gp */
*(--stk) = (rt_uint32_t) 0x0000001b; /* k1 */
*(--stk) = (rt_uint32_t) 0x0000001a; /* k0 */
*(--stk) = (rt_uint32_t) 0x00000019; /* t9 */
*(--stk) = (rt_uint32_t) 0x00000018; /* t8 */
*(--stk) = (rt_uint32_t) 0x00000017; /* s7 */
*(--stk) = (rt_uint32_t) 0x00000016; /* s6 */
*(--stk) = (rt_uint32_t) 0x00000015; /* s5 */
*(--stk) = (rt_uint32_t) 0x00000014; /* s4 */
*(--stk) = (rt_uint32_t) 0x00000013; /* s3 */
*(--stk) = (rt_uint32_t) 0x00000012; /* s2 */
*(--stk) = (rt_uint32_t) 0x00000011; /* s1 */
*(--stk) = (rt_uint32_t) 0x00000010; /* s0 */
*(--stk) = (rt_uint32_t) 0x0000000f; /* t7 */
*(--stk) = (rt_uint32_t) 0x0000000e; /* t6 */
*(--stk) = (rt_uint32_t) 0x0000000d; /* t5 */
*(--stk) = (rt_uint32_t) 0x0000000c; /* t4 */
*(--stk) = (rt_uint32_t) 0x0000000b; /* t3 */
*(--stk) = (rt_uint32_t) 0x0000000a; /* t2 */
*(--stk) = (rt_uint32_t) 0x00000009; /* t1 */
*(--stk) = (rt_uint32_t) 0x00000008; /* t0 */
*(--stk) = (rt_uint32_t) 0x00000007; /* a3 */
*(--stk) = (rt_uint32_t) 0x00000006; /* a2 */
*(--stk) = (rt_uint32_t) 0x00000005; /* a1 */
*(--stk) = (rt_uint32_t) parameter; /* a0 */
*(--stk) = (rt_uint32_t) 0x00000003; /* v1 */
*(--stk) = (rt_uint32_t) 0x00000002; /* v0 */
*(--stk) = (rt_uint32_t) 0x00000001; /* at */
*(--stk) = (rt_uint32_t) 0x00000000; /* zero */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
/*@}*/

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/*
* File : cpu.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "../common/exception.h"
#include "../common/mipsregs.h"
/**
* @addtogroup Loongson
*/
/*@{*/
/**
* exception handle table
*/
#define RT_EXCEPTION_MAX 8
exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
/**
* setup the exception handle
*/
exception_func_t rt_set_except_vector(int n, exception_func_t func)
{
exception_func_t old_handler = sys_exception_handlers[n];
if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
{
return 0;
}
sys_exception_handlers[n] = func;
return old_handler;
}
void tlb_refill_handler(void)
{
rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
void cache_error_handler(void)
{
rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
rt_hw_cpu_shutdown();
}
static void unhandled_exception_handle(pt_regs_t *regs)
{
rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
}
void install_default_execpt_handle(void)
{
rt_int32_t i;
for (i=0; i<RT_EXCEPTION_MAX; i++)
sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
}
void exception_handler(pt_regs_t *regs)
{
rt_uint32_t cause;
rt_uint32_t index;
cause = (read_c0_cause() & read_c0_config());
cause = (cause & 0xfc00) >> 8;
for (index = RT_EXCEPTION_MAX; index > 0; index --)
{
if (cause & (1 << index))
{
sys_exception_handlers[index](regs);
cause &= ~(1 << index);
}
}
}
/*@}*/

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/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-10-15 Bernard first version
* 2010-10-15 lgnq modified for LS1B
* 2013-03-29 aozima Modify the interrupt interface implementations.
* 2015-07-06 chinesebear modified for loongson 1c
*/
#include <rtthread.h>
#include <rthw.h>
#include "ls1c.h"
#define MAX_INTR 32
extern rt_uint32_t rt_interrupt_nest;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
static struct rt_irq_desc irq_handle_table[MAX_INTR];
void rt_interrupt_dispatch(void *ptreg);
void rt_hw_timer_handler();
static struct ls1c_intc_regs volatile *ls1c_hw0_icregs
= (struct ls1c_intc_regs volatile *)(LS1C_INTREG_BASE);
/**
* @addtogroup Loongson LS1B
*/
/*@{*/
static void rt_hw_interrupt_handler(int vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
rt_int32_t idx;
/* pci active low */
ls1c_hw0_icregs->int_pol = -1; //must be done here 20110802 lgnq
/* make all interrupts level triggered */
(ls1c_hw0_icregs+0)->int_edge = 0x0000e000;
/* mask all interrupts */
(ls1c_hw0_icregs+0)->int_clr = 0xffffffff;
rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
for (idx = 0; idx < MAX_INTR; idx ++)
{
irq_handle_table[idx].handler = rt_hw_interrupt_handler;
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int vector)
{
/* mask interrupt */
(ls1c_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int vector)
{
(ls1c_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector >= 0 && vector < MAX_INTR)
{
old_handler = irq_handle_table[vector].handler;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
#endif /* RT_USING_INTERRUPT_INFO */
irq_handle_table[vector].handler = handler;
irq_handle_table[vector].param = param;
}
return old_handler;
}
void rt_interrupt_dispatch(void *ptreg)
{
int irq;
void *param;
rt_isr_handler_t irq_func;
static rt_uint32_t status = 0;
rt_uint32_t c0_status;
rt_uint32_t c0_cause;
volatile rt_uint32_t cause_im;
volatile rt_uint32_t status_im;
rt_uint32_t pending_im;
/* check os timer */
c0_status = read_c0_status();
c0_cause = read_c0_cause();
cause_im = c0_cause & ST0_IM;
status_im = c0_status & ST0_IM;
pending_im = cause_im & status_im;
if (pending_im & CAUSEF_IP7)
{
rt_hw_timer_handler();
}
if (pending_im & CAUSEF_IP2)
{
/* the hardware interrupt */
status = ls1c_hw0_icregs->int_isr;
if (!status)
return;
for (irq = MAX_INTR; irq > 0; --irq)
{
if ((status & (1 << irq)))
{
status &= ~(1 << irq);
irq_func = irq_handle_table[irq].handler;
param = irq_handle_table[irq].param;
/* do interrupt */
irq_func(irq, param);
#ifdef RT_USING_INTERRUPT_INFO
irq_handle_table[irq].counter++;
#endif /* RT_USING_INTERRUPT_INFO */
/* ack interrupt */
ls1c_hw0_icregs->int_clr |= (1 << irq);
}
}
}
else if (pending_im & CAUSEF_IP3)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP4)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP5)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
else if (pending_im & CAUSEF_IP6)
{
rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
}
}
/*@}*/

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/*
* File : ls1c.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-08-08 lgnq first version
* 2015-07-06 chinesebear modified for loongson 1c
*/
#ifndef __LS1C_H__
#define __LS1C_H__
#include "../common/mipsregs.h"
#define LS1C_ACPI_IRQ 0
#define LS1C_HPET_IRQ 1
#define LS1C_UART0_IRQ 2
#define LS1C_UART1_IRQ 4
#define LS1C_UART2_IRQ 5
#define LS1C_CAN0_IRQ 6
#define LS1C_CAN1_IRQ 7
#define LS1C_SPI0_IRQ 8
#define LS1C_SPI1_IRQ 9
#define LS1C_AC97_IRQ 10
#define LS1C_MS_IRQ 11
#define LS1C_KB_IRQ 12
#define LS1C_DMA0_IRQ 13
#define LS1C_DMA1_IRQ 14
#define LS1C_NAND_IRQ 15
#define LS1C_I2C0_IRQ 16
#define LS1C_I2C1_IRQ 17
#define LS1C_PWM0_IRQ 18
#define LS1C_PWM1_IRQ 19
#define LS1C_PWM2_IRQ 20
#define LS1C_PWM3_IRQ 21
#define LS1C_LPC_IRQ 22
#define LS1C_EHCI_IRQ 32
#define LS1C_OHCI_IRQ 33
#define LS1C_GMAC1_IRQ 34
#define LS1C_GMAC2_IRQ 35
#define LS1C_SATA_IRQ 36
#define LS1C_GPU_IRQ 37
#define LS1C_PCI_INTA_IRQ 38
#define LS1C_PCI_INTB_IRQ 39
#define LS1C_PCI_INTC_IRQ 40
#define LS1C_PCI_INTD_IRQ 41
#define LS1C_GPIO_IRQ 64
#define LS1C_GPIO_FIRST_IRQ 64
#define LS1C_GPIO_IRQ_COUNT 96
#define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
#define INT_PCI_INTA (1<<6)
#define INT_PCI_INTB (1<<7)
#define INT_PCI_INTC (1<<8)
#define INT_PCI_INTD (1<<9)
#define LS1C_LAST_IRQ 159
#define MIPS_CPU_TIMER_IRQ 167
#define LS1C_INTREG_BASE 0xbfd01040
#define LS1C_DMA_IRQ_BASE 168
#define LS1C_DMA_IRQ_COUNT 16
struct ls1c_intc_regs
{
volatile unsigned int int_isr;
volatile unsigned int int_en;
volatile unsigned int int_set;
volatile unsigned int int_clr; /* offset 0x10*/
volatile unsigned int int_pol;
volatile unsigned int int_edge; /* offset 0 */
};
struct ls1c_cop_global_regs
{
volatile unsigned int control;
volatile unsigned int rd_inten;
volatile unsigned int wr_inten;
volatile unsigned int rd_intisr; /* offset 0x10*/
volatile unsigned int wr_intisr;
unsigned int unused[11];
} ;
struct ls1c_cop_channel_regs
{
volatile unsigned int rd_control;
volatile unsigned int rd_src;
volatile unsigned int rd_cnt;
volatile unsigned int rd_status; /* offset 0x10*/
volatile unsigned int wr_control;
volatile unsigned int wr_src;
volatile unsigned int wr_cnt;
volatile unsigned int wr_status; /* offset 0x10*/
} ;
struct ls1c_cop_regs
{
struct ls1c_cop_global_regs global;
struct ls1c_cop_channel_regs chan[8][2];
} ;
#define __REG8(addr) *((volatile unsigned char *)(addr))
#define __REG16(addr) *((volatile unsigned short *)(addr))
#define __REG32(addr) *((volatile unsigned int *)(addr))
#define GMAC0_BASE 0xBFE10000
#define GMAC0_DMA_BASE 0xBFE11000
#define GMAC1_BASE 0xBFE20000
#define GMAC1_DMA_BASE 0xBFE21000
#define I2C0_BASE 0xBFE58000
#define PWM0_BASE 0xBFE5C000
#define PWM1_BASE 0xBFE5C010
#define PWM2_BASE 0xBFE5C020
#define PWM3_BASE 0xBFE5C030
#define WDT_BASE 0xBFE5C060
#define RTC_BASE 0xBFE64000
#define I2C1_BASE 0xBFE68000
#define I2C2_BASE 0xBFE70000
#define AC97_BASE 0xBFE74000
#define NAND_BASE 0xBFE78000
#define SPI_BASE 0xBFE80000
#define CAN1_BASE 0xBF004300
#define CAN0_BASE 0xBF004400
/* Watch Dog registers */
#define WDT_EN __REG32(WDT_BASE + 0x00)
#define WDT_SET __REG32(WDT_BASE + 0x04)
#define WDT_TIMER __REG32(WDT_BASE + 0x08)
#define PLL_FREQ __REG32(0xbfe78030)
#define PLL_DIV_PARAM __REG32(0xbfe78034)
#endif

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/*
* File : mipscfg.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-27 swkyer first version
*/
#include <rtthread.h>
#include "../common/mipsregs.h"
#include "../common/mipscfg.h"
mips32_core_cfg_t g_mips_core =
{
16, /* icache_line_size */
256, /* icache_lines_per_way */
4, /* icache_ways */
16, /* dcache_line_size */
256, /* dcache_lines_per_way */
4, /* dcache_ways */
16, /* max_tlb_entries */
};
static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
{
rt_uint16_t rets = 1;
while (n--)
rets *= b;
return rets;
}
static rt_uint16_t m_log2(rt_uint16_t b)
{
rt_uint16_t rets = 0;
while (b != 1)
{
b /= 2;
rets++;
}
return rets;
}
/**
* read core attribute
*/
void mips32_cfg_init(void)
{
rt_uint16_t val;
rt_uint32_t cp0_config1;
cp0_config1 = read_c0_config();
if (cp0_config1 & 0x80000000)
{
cp0_config1 = read_c0_config1();
val = (cp0_config1 & (7<<22))>>22;
g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<19))>>19;
g_mips_core.icache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<16))>>16;
g_mips_core.icache_ways = val + 1;
val = (cp0_config1 & (7<<13))>>13;
g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
val = (cp0_config1 & (7<<10))>>10;
g_mips_core.dcache_line_size = 2 * m_pow(2, val);
val = (cp0_config1 & (7<<7))>>7;
g_mips_core.dcache_ways = val + 1;
val = (cp0_config1 & (0x3F<<25))>>25;
g_mips_core.max_tlb_entries = val + 1;
}
}

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/*
* File : start_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2010-05-17 swkyer first version
* 2010-09-04 bernard porting to Jz47xx
*/
#include "../common/mips.inc"
#include "../common/stackframe.h"
.section ".start", "ax"
.set noreorder
/* the program entry */
.globl _start
_start:
.set noreorder
la ra, _start
/* disable interrupt */
mfc0 t0, CP0_STATUS
and t0, 0xfffffffe # By default it will be disabled.
mtc0 t0, CP0_STATUS # Set CPU to disable interrupt.
nop
/* disable cache */
mfc0 t0, CP0_CONFIG
and t0, 0xfffffff8
or t0, 0x2 # disable,!default value is not it!
mtc0 t0, CP0_CONFIG # Set CPU to disable cache.
nop
/* setup stack pointer */
li sp, SYSTEM_STACK
la gp, _gp
/* clear bss */
la t0, __bss_start
la t1, __bss_end
_clr_bss_loop:
sw zero, 0(t0)
bne t0, t1, _clr_bss_loop
addiu t0, t0, 4
/* jump to RT-Thread RTOS */
jal rtthread_startup
nop
/* restart, never die */
j _start
nop
.set reorder
.globl cp0_get_cause
cp0_get_cause:
mfc0 v0, CP0_CAUSE
jr ra
nop
.globl cp0_get_status
cp0_get_status:
mfc0 v0, CP0_STATUS
jr ra
nop
.globl cp0_get_hi
cp0_get_hi:
mfhi v0
jr ra
nop
.globl cp0_get_lo
cp0_get_lo:
mflo v0
jr ra
nop
.extern tlb_refill_handler
.extern cache_error_handler
/* Exception Handler */
/* 0x0 - TLB refill handler */
.section .vectors.1, "ax", %progbits
.global tlb_refill_exception
.type tlb_refill_exception,@function
tlb_refill_exception:
j tlb_refill_handler
nop
/* 0x100 - Cache error handler */
.section .vectors.2, "ax", %progbits
j cache_error_handler
nop
/* 0x180 - Exception/Interrupt handler */
.section .vectors.3, "ax", %progbits
.global general_exception
.type general_exception,@function
general_exception:
j _general_exception_handler
nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.section .vectors.4, "ax", %progbits
.global irq_exception
.type irq_exception,@function
irq_exception:
j _irq_handler
nop
.section .vectors, "ax", %progbits
.extern mips_irq_handle
/* general exception handler */
_general_exception_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder
/* interrupt handler */
_irq_handler:
.set noreorder
la k0, mips_irq_handle
jr k0
nop
.set reorder