diff --git a/bsp/jz47xx/application.c b/bsp/jz47xx/application.c index 53881435a..2b6ce42b4 100644 --- a/bsp/jz47xx/application.c +++ b/bsp/jz47xx/application.c @@ -18,8 +18,33 @@ /*@{*/ #include +#include +#include + +static struct rt_thread thread1; +static rt_uint8_t thread1_stack[1024]; + +void thread_entry(void* parameter) +{ + while (1) + { + rt_kprintf("IPR: 0x%08x, SR : 0x%08x, CAUSE: 0x%08x\n", INTC_IPR, read_c0_status(), read_c0_cause()); + + rt_thread_delay(100); + } +} + int rt_application_init() { + rt_err_t result; + + result = rt_thread_init(&thread1, "t1", + thread_entry, RT_NULL, + &thread1_stack[0], sizeof(thread1_stack), + 200, 10); + if (result == RT_EOK) + rt_thread_startup(&thread1); + return 0; } diff --git a/bsp/jz47xx/board.c b/bsp/jz47xx/board.c index f0ebd3842..439534ec8 100644 --- a/bsp/jz47xx/board.c +++ b/bsp/jz47xx/board.c @@ -17,6 +17,7 @@ #include "board.h" #include "uart.h" +#include /** * @addtogroup JZ47xx @@ -28,13 +29,68 @@ */ void rt_hw_timer_handler() { - /* enter interrupt */ - rt_interrupt_enter(); - + /* increase a OS tick */ rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); + /* clear flag */ + TCU_TFCR = TCU_TFCR_OSTFLAG; +} + +/** + * This function will initial OS timer + */ +void rt_hw_timer_init() +{ + rt_uint32_t val; + + /* disable TCU clock */ + CPM_CLKGR &= ~CPM_CLKGR_TCU; + TCU_TECR = TCU_TECR_OSTCL; + + /* set */ + OST_DR = RT_TICK_PER_SECOND * 0xcffff; + /* clear counter */ + OST_CNT = 0; + +#if 0 + switch (RTC_DIV) + { + case 1: + val = OST_TCSR_PRESCALE1; + break; + case 4: + val = OST_TCSR_PRESCALE4; + break; + case 16: + val = OST_TCSR_PRESCALE16; + break; + case 64: + val = OST_TCSR_PRESCALE64; + break; + case 256: + val = OST_TCSR_PRESCALE256; + break; + case 1024: + val = OST_TCSR_PRESCALE1024; + break; + default: + val = OST_TCSR_PRESCALE4; + break; + } +#endif + +#ifdef RTC_SRC_EXTAL + OST_CSR = (val | OST_TCSR_EXT_EN); +#else + OST_CSR = (val | OST_TCSR_PCLK_EN); +#endif + + TCU_TFCR = TCU_TFCR_OSTFLAG; + TCU_TMCR = TCU_TMCR_OSTMCL; + TCU_TESR = TCU_TESR_OSTST; + + rt_hw_interrupt_install(IRQ_TCU0, rt_hw_timer_handler, RT_NULL); + rt_hw_interrupt_umask (IRQ_TCU0); } /** @@ -51,5 +107,8 @@ void rt_hw_board_init() /* set console device */ rt_console_set_device("uart"); #endif + + /* init operating system timer */ + rt_hw_timer_init(); } /*@}*/ diff --git a/bsp/jz47xx/rtconfig.py b/bsp/jz47xx/rtconfig.py index acfc53836..53d59e4f2 100644 --- a/bsp/jz47xx/rtconfig.py +++ b/bsp/jz47xx/rtconfig.py @@ -84,4 +84,4 @@ else: RT_USING_MINILIBC = True DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n' COPY_ACTION = 'copy rtthread.bin usbboot\n' -POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + DUMP_ACTION + COPY_ACTION +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + COPY_ACTION diff --git a/bsp/jz47xx/startup.c b/bsp/jz47xx/startup.c index e216e2ac8..67779e996 100644 --- a/bsp/jz47xx/startup.c +++ b/bsp/jz47xx/startup.c @@ -14,6 +14,7 @@ #include #include +#include #include "board.h" @@ -27,22 +28,13 @@ extern unsigned char __bss_end; extern int rt_application_init(void); -void dump_memory(rt_uint8_t* ptr, rt_size_t size) -{ - rt_size_t index; - - for (index = 0; index < size; index ++) - { - rt_kprintf("%02x ", ptr[index] & 0xff); - if ((index + 1) % 16 == 0) rt_kprintf("\n"); - } -} - /** * This function will startup RT-Thread RTOS. */ void rtthread_startup(void) { + /* init cache */ + rt_hw_cache_init(); /* init hardware interrupt */ rt_hw_interrupt_init(); @@ -50,8 +42,6 @@ void rtthread_startup(void) rt_hw_board_init(); rt_show_version(); - dump_memory((rt_uint8_t*)0x80000200, 32); - /* init tick */ rt_system_tick_init(); diff --git a/bsp/jz47xx/uart.c b/bsp/jz47xx/uart.c index 9ddbb02e1..d3aa84a15 100644 --- a/bsp/jz47xx/uart.c +++ b/bsp/jz47xx/uart.c @@ -1,6 +1,7 @@ #include #include -#include + +#include /** * @addtogroup Jz47xx diff --git a/libcpu/mips/jz47xx/cache.c b/libcpu/mips/jz47xx/cache.c new file mode 100644 index 000000000..e00292675 --- /dev/null +++ b/libcpu/mips/jz47xx/cache.c @@ -0,0 +1,93 @@ +#include "jz47xx.h" +#include "cache.h" + +#define CACHE_SIZE 16*1024 +#define CACHE_LINE_SIZE 32 +#define KSEG0 0x80000000 + + +#define K0_TO_K1() \ +do { \ + unsigned long __k0_addr; \ + \ + __asm__ __volatile__( \ + "la %0, 1f\n\t" \ + "or %0, %0, %1\n\t" \ + "jr %0\n\t" \ + "nop\n\t" \ + "1: nop\n" \ + : "=&r"(__k0_addr) \ + : "r" (0x20000000) ); \ +} while(0) + +#define K1_TO_K0() \ +do { \ + unsigned long __k0_addr; \ + __asm__ __volatile__( \ + "nop;nop;nop;nop;nop;nop;nop\n\t" \ + "la %0, 1f\n\t" \ + "jr %0\n\t" \ + "nop\n\t" \ + "1: nop\n" \ + : "=&r" (__k0_addr)); \ +} while (0) + +#define INVALIDATE_BTB() \ +do { \ + unsigned long tmp; \ + __asm__ __volatile__( \ + ".set mips32\n\t" \ + "mfc0 %0, $16, 7\n\t" \ + "nop\n\t" \ + "ori %0, 2\n\t" \ + "mtc0 %0, $16, 7\n\t" \ + "nop\n\t" \ + ".set mips2\n\t" \ + : "=&r" (tmp)); \ +} while (0) + +#define SYNC_WB() __asm__ __volatile__ ("sync") + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips32\n\t \n" \ + " cache %0, %1 \n" \ + " .set mips0 \n" \ + " .set reorder" \ + : \ + : "i" (op), "m" (*(unsigned char *)(addr))) + +void __icache_invalidate_all(void) +{ + unsigned int i; + + K0_TO_K1(); + + asm volatile (".set noreorder\n" + ".set mips32\n\t" + "mtc0\t$0,$28\n\t" + "mtc0\t$0,$29\n" + ".set mips0\n" + ".set reorder\n"); + for (i=KSEG0;i +#include +/* Watchdog definitions */ +#define WDT_CLK_PRESCALE_CLK1 ( 0x0 << 3) +#define WDT_CLK_PRESCALE_CLK4 ( 0x1 << 3) +#define WDT_CLK_PRESCALE_CLK16 ( 0x2 << 3) +#define WDT_CLK_PRESCALE_CLK64 ( 0x3 << 3) +#define WDT_CLK_PRESCALE_CLK256 ( 0x4 << 3) +#define WDT_CLK_PRESCALE_CLK1024 ( 0x5 << 3) +#define WDT_CLK_PRESCALE_MASK ( 0x3F << 3) + +#define WDT_CLK_EXTAL ( 0x1 << 2) +#define WDT_CLK_RTC ( 0x1 << 1) +#define WDT_CLK_PCLK ( 0x1 << 0) +#define WDT_CLK_MASK ( 7 ) + +#define WDT_ENABLE ( 1 << 0 ) /** * @addtogroup Jz47xx @@ -26,6 +43,14 @@ void rt_hw_cpu_reset() { /* open the watch-dog */ + WDT_TCSR = WDT_CLK_EXTAL; + WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024; + WDT_TDR = 0x03; + WDT_TCNT = 0x00; + WDT_TCER |= WDT_ENABLE; + + rt_kprintf("reboot system...\n"); + while (1); } /** diff --git a/libcpu/mips/jz47xx/interrupt.c b/libcpu/mips/jz47xx/interrupt.c index 8c44c63cc..8a9bd84e6 100644 --- a/libcpu/mips/jz47xx/interrupt.c +++ b/libcpu/mips/jz47xx/interrupt.c @@ -88,17 +88,17 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha } } -static rt_uint32_t pending ; void rt_interrupt_dispatch(void *ptreg) { int i; rt_isr_handler_t irq_func; + static rt_uint32_t pending = 0; /* the hardware interrupt */ pending |= INTC_IPR; if (!pending) return; - for (i = 0; i < JZ47XX_MAX_INTR; i++) + for (i = JZ47XX_MAX_INTR; i > 0; --i) { if ((pending & (1<