commit
376ac91b67
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@ -48,15 +48,29 @@ extern "C" {
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#define HWREG8(x) (*((volatile rt_uint8_t *)(x)))
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#define HWREG8(x) (*((volatile rt_uint8_t *)(x)))
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#endif
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#endif
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#ifndef RT_CPU_CACHE_LINE_SZ
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#define RT_CPU_CACHE_LINE_SZ 32
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#endif
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enum RT_HW_CACHE_OPS
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{
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RT_HW_CACHE_FLUSH = 0x01,
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RT_HW_CACHE_INVALIDATE = 0x02,
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};
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/*
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/*
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* CPU interfaces
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* CPU interfaces
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*/
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*/
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void rt_hw_cpu_icache_enable(void);
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void rt_hw_cpu_icache_enable(void);
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void rt_hw_cpu_icache_disable(void);
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void rt_hw_cpu_icache_disable(void);
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rt_base_t rt_hw_cpu_icache_status(void);
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rt_base_t rt_hw_cpu_icache_status(void);
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void rt_hw_cpu_icache_ops(int ops, void* addr, int size);
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void rt_hw_cpu_dcache_enable(void);
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void rt_hw_cpu_dcache_enable(void);
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void rt_hw_cpu_dcache_disable(void);
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void rt_hw_cpu_dcache_disable(void);
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rt_base_t rt_hw_cpu_dcache_status(void);
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rt_base_t rt_hw_cpu_dcache_status(void);
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void rt_hw_cpu_dcache_ops(int ops, void* addr, int size);
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void rt_hw_cpu_reset(void);
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void rt_hw_cpu_reset(void);
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void rt_hw_cpu_shutdown(void);
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void rt_hw_cpu_shutdown(void);
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