Merge pull request #1407 from aozima/pulls
update enc28j60 driver: ensure enable PHY link changed interrupt.
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commit
290b2fa98e
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@ -321,6 +321,8 @@ static rt_err_t enc28j60_init(rt_device_t dev)
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enc28j60_phy_write(spi_device, PHCON1, PHCON1_PDPXMD); // full duplex
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enc28j60_phy_write(spi_device, PHCON1, PHCON1_PDPXMD); // full duplex
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// no loopback of transmitted frames
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// no loopback of transmitted frames
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enc28j60_phy_write(spi_device, PHCON2, PHCON2_HDLDIS);
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enc28j60_phy_write(spi_device, PHCON2, PHCON2_HDLDIS);
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/* enable PHY link changed interrupt. */
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enc28j60_phy_write(spi_device, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
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enc28j60_set_bank(spi_device, ECON2);
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enc28j60_set_bank(spi_device, ECON2);
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spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON2, ECON2_AUTOINC);
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spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON2, ECON2_AUTOINC);
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@ -221,6 +221,12 @@
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#define PHCON2_TXDIS 0x2000
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#define PHCON2_TXDIS 0x2000
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#define PHCON2_JABBER 0x0400
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#define PHCON2_JABBER 0x0400
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#define PHCON2_HDLDIS 0x0100
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#define PHCON2_HDLDIS 0x0100
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/* ENC28J60 PHY PHIE Register Bit Definitions */
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#define PHIE_PLNKIE (1 << 4)
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#define PHIE_PGEIE (1 << 1)
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/* ENC28J60 PHY PHIR Register Bit Definitions */
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#define PHIR_PLNKIF (1 << 4)
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#define PHIR_PGEIF (1 << 1)
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// ENC28J60 Packet Control Byte Bit Definitions
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// ENC28J60 Packet Control Byte Bit Definitions
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#define PKTCTRL_PHUGEEN 0x08
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#define PKTCTRL_PHUGEEN 0x08
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