diff --git a/bsp/stm32f107/stm32_eth.c b/bsp/stm32f107/stm32_eth.c index 4cab904d1..95c4629f0 100644 --- a/bsp/stm32f107/stm32_eth.c +++ b/bsp/stm32f107/stm32_eth.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_eth.c * @author MCD Application Team - * @version V1.0.0 - * @date 06/19/2009 + * @version V1.1.0 + * @date 11/20/2009 * @brief This file provides all the ETH firmware functions. ****************************************************************************** * @copy @@ -22,6 +22,13 @@ #include "stm32_eth.h" #include "stm32f10x_rcc.h" +/* STM32F107 ETH dirver options */ +#define CHECKSUM_BY_HARDWARE +#define MII_MODE /* MII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */ +//#define RMII_MODE /* RMII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */ +#define PHY_ADDRESS 0x01 /* Relative to STM3210C-EVAL Board */ + + /** @addtogroup STM32_ETH_Driver * @brief ETH driver modules * @{ @@ -45,28 +52,39 @@ ETH_DMADESCTypeDef *DMAPTPTxDescToSet; ETH_DMADESCTypeDef *DMAPTPRxDescToGet; /* ETHERNET MAC address offsets */ -#define ETH_MAC_AddrHighBase (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ -#define ETH_MAC_AddrLowBase (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + /* ETHERNET MACMIIAR register Mask */ -#define MACMIIAR_CR_Mask ((uint32_t)0xFFFFFFE3) +#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) + /* ETHERNET MACCR register Mask */ -#define MACCR_CLEAR_Mask ((uint32_t)0xFF20810F) +#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) + /* ETHERNET MACFCR register Mask */ -#define MACFCR_CLEAR_Mask ((uint32_t)0x0000FF41) +#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) + /* ETHERNET DMAOMR register Mask */ -#define DMAOMR_CLEAR_Mask ((uint32_t)0xF8DE3F23) +#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) + /* ETHERNET Remote Wake-up frame register length */ -#define ETH_WakeupRegisterLength 8 +#define ETH_WAKEUP_REGISTER_LENGTH 8 + /* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RxOverflowMissedFramesCounterShift 17 +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 + /* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATxDesc_CollisionCountShift 3 +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 + /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATxDesc_BufferSize2Shift 16 +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 + /* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARxDesc_FrameLengthShift 16 +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 + /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARxDesc_Buffer2SizeShift 16 +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 + /* ETHERNET errors */ #define ETH_ERROR ((uint32_t)0) #define ETH_SUCCESS ((uint32_t)1) @@ -91,6 +109,7 @@ ETH_DMADESCTypeDef *DMAPTPRxDescToGet; /** @defgroup ETH_Private_FunctionPrototypes * @{ */ + /** * @} */ @@ -100,10 +119,9 @@ ETH_DMADESCTypeDef *DMAPTPRxDescToGet; */ /** - * @brief Deinitializes the ETHERNET peripheral registers to their - * default reset values. + * @brief Deinitializes the ETHERNET peripheral registers to their default reset values. * @param None - * @retval : None + * @retval None */ void ETH_DeInit(void) { @@ -114,12 +132,11 @@ void ETH_DeInit(void) /** * @brief Initializes the ETHERNET peripheral according to the specified * parameters in the ETH_InitStruct . - * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure - * that contains the configuration information for the - * specified ETHERNET peripheral. + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains + * the configuration information for the specified ETHERNET peripheral. * @param PHYAddress: external PHY address - * @retval : ETH_ERROR: Ethernet initialization failed - * ETH_SUCCESS: Ethernet successfully initialized + * @retval ETH_ERROR: Ethernet initialization failed + * ETH_SUCCESS: Ethernet successfully initialized */ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) { @@ -181,7 +198,7 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) /* Get the ETHERNET MACMIIAR value */ tmpreg = ETH->MACMIIAR; /* Clear CSR Clock Range CR[2:0] bits */ - tmpreg &= MACMIIAR_CR_Mask; + tmpreg &= MACMIIAR_CR_MASK; /* Get hclk frequency value */ RCC_GetClocksFreq(&rcc_clocks); hclk = rcc_clocks.HCLK_Frequency; @@ -295,7 +312,7 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) /* Get the ETHERNET MACCR value */ tmpreg = ETH->MACCR; /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg &= MACCR_CLEAR_Mask; + tmpreg &= MACCR_CLEAR_MASK; /* Set the WD bit according to ETH_Watchdog value */ /* Set the JD: bit according to ETH_Jabber value */ /* Set the IFG bit according to ETH_InterFrameGap value */ @@ -352,7 +369,7 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) /* Get the ETHERNET MACFCR value */ tmpreg = ETH->MACFCR; /* Clear xx bits */ - tmpreg &= MACFCR_CLEAR_Mask; + tmpreg &= MACFCR_CLEAR_MASK; /* Set the PT bit according to ETH_PauseTime value */ /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ @@ -379,7 +396,7 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) /* Get the ETHERNET DMAOMR value */ tmpreg = ETH->DMAOMR; /* Clear xx bits */ - tmpreg &= DMAOMR_CLEAR_Mask; + tmpreg &= DMAOMR_CLEAR_MASK; /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ /* Set the RSF bit according to ETH_ReceiveStoreForward value */ @@ -422,9 +439,8 @@ uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress) /** * @brief Fills each ETH_InitStruct member with its default value. - * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure - * which will be initialized. - * @retval : None + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized. + * @retval None */ void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) { @@ -483,7 +499,7 @@ void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) /** * @brief Enables ENET MAC and DMA reception/transmission * @param None - * @retval : None + * @retval None */ void ETH_Start(void) { @@ -502,10 +518,10 @@ void ETH_Start(void) /** * @brief Transmits a packet, from application buffer, pointed by ppkt. - * @param ppkt: pointer to application packet buffer to transmit. - * @param FrameLength: Tx Packet size. - * @retval : ETH_ERROR: in case of Tx desc owned by DMA - * ETH_SUCCESS: for correct transmission + * @param ppkt: pointer to the application's packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @retval ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission */ uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) { @@ -565,9 +581,9 @@ uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) /** * @brief Receives a packet and copies it to memory pointed by ppkt. - * @param ppkt: pointer to application packet receive buffer. - * @retval : ETH_ERROR: if there is error in reception - * framelength: received packet size if packet reception is correct + * @param ppkt: pointer to the application packet receive buffer. + * @retval ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct */ uint32_t ETH_HandleRxPkt(uint8_t *ppkt) { @@ -584,7 +600,7 @@ uint32_t ETH_HandleRxPkt(uint8_t *ppkt) ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) { /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ for(offset=0; offsetMACMIIAR; /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~MACMIIAR_CR_Mask; + tmpreg &= ~MACMIIAR_CR_MASK; /* Prepare the MII address register value */ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ @@ -738,17 +752,15 @@ __IO uint32_t timeout = 0; /** * @brief Write to a PHY register - * @param PHYAddress: PHY device address, is the index of one of supported - * 32 PHY devices. + * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. * This parameter can be one of the following values: 0,..,31 - * @param PHYReg: PHY register address, is the index of one of the 32 - * PHY register. + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. * This parameter can be one of the following values: - * @arg PHY_BCR : Tranceiver Control Register - * @arg More PHY register could be written depending on the used PHY - * @param PHYValue: the value to write - * @retval : ETH_ERROR: in case of timeout - * ETH_SUCCESS: for correct write + * @arg PHY_BCR : Tranceiver Control Register + * @arg More PHY register could be written depending on the used PHY + * @param PHYValue: the value to write + * @retval ETH_ERROR: in case of timeout + * ETH_SUCCESS: for correct write */ uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) { @@ -761,7 +773,7 @@ uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHY /* Get the ETHERNET MACMIIAR value */ tmpreg = ETH->MACMIIAR; /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg &= ~MACMIIAR_CR_Mask; + tmpreg &= ~MACMIIAR_CR_MASK; /* Prepare the MII register address value */ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ @@ -789,15 +801,14 @@ uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHY /** * @brief Enables or disables the PHY loopBack mode. - * @param PHYAddress: PHY device address, is the index of one of supported - * 32 PHY devices. + * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal + * loopback at MII level + * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. * This parameter can be one of the following values: - * @param NewState: new state of the PHY loopBack mode. + * @param NewState: new state of the PHY loopBack mode. * This parameter can be: ENABLE or DISABLE. - * Note: Don't be confused with ETH_MACLoopBackCmd function - * which enables internal loopback at MII level - * @retval : ETH_ERROR: in case of bad PHY configuration - * ETH_SUCCESS: for correct PHY configuration + * @retval ETH_ERROR: in case of bad PHY configuration + * ETH_SUCCESS: for correct PHY configuration */ uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) { @@ -834,9 +845,9 @@ uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) /*--------------------------------- MAC ------------------------------------*/ /** * @brief Enables or disables the MAC transmission. - * @param NewState: new state of the MAC transmission. + * @param NewState: new state of the MAC transmission. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_MACTransmissionCmd(FunctionalState NewState) { @@ -857,9 +868,9 @@ void ETH_MACTransmissionCmd(FunctionalState NewState) /** * @brief Enables or disables the MAC reception. - * @param NewState: new state of the MAC reception. + * @param NewState: new state of the MAC reception. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_MACReceptionCmd(FunctionalState NewState) { @@ -881,7 +892,7 @@ void ETH_MACReceptionCmd(FunctionalState NewState) /** * @brief Checks whether the ETHERNET flow control busy bit is set or not. * @param None - * @retval : The new state of flow control busy status bit (SET or RESET). + * @retval The new state of flow control busy status bit (SET or RESET). */ FlagStatus ETH_GetFlowControlBusyStatus(void) { @@ -901,7 +912,7 @@ FlagStatus ETH_GetFlowControlBusyStatus(void) /** * @brief Initiate a Pause Control Frame (Full-duplex only). * @param None - * @retval : None + * @retval None */ void ETH_InitiatePauseControlFrame(void) { @@ -911,9 +922,9 @@ void ETH_InitiatePauseControlFrame(void) /** * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). - * @param NewState: new state of the MAC BackPressure operation activation. + * @param NewState: new state of the MAC BackPressure operation activation. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_BackPressureActivationCmd(FunctionalState NewState) { @@ -936,14 +947,14 @@ void ETH_BackPressureActivationCmd(FunctionalState NewState) /** * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * @param ETH_MAC_FLAG: specifies the flag to check. + * @param ETH_MAC_FLAG: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval : The new state of ETHERNET MAC flag (SET or RESET). + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval The new state of ETHERNET MAC flag (SET or RESET). */ FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) { @@ -963,14 +974,14 @@ FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) /** * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. - * @param ETH_MAC_IT: specifies the interrupt source to check. + * @param ETH_MAC_IT: specifies the interrupt source to check. * This parameter can be one of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt - * @arg ETH_MAC_IT_MMCR : MMC receive interrupt - * @arg ETH_MAC_IT_MMC : MMC interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval : The new state of ETHERNET MAC interrupt (SET or RESET). + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt + * @arg ETH_MAC_IT_MMCR : MMC receive interrupt + * @arg ETH_MAC_IT_MMC : MMC interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval The new state of ETHERNET MAC interrupt (SET or RESET). */ ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) { @@ -990,14 +1001,14 @@ ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) /** * @brief Enables or disables the specified ETHERNET MAC interrupts. - * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be + * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @param NewState: new state of the specified ETHERNET MAC interrupts. + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @param NewState: new state of the specified ETHERNET MAC interrupts. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) { @@ -1019,14 +1030,14 @@ void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) /** * @brief Configures the selected MAC address. - * @param MacAddr: The MAC addres to configure. + * @param MacAddr: The MAC addres to configure. * This parameter can be one of the following values: - * @arg ETH_MAC_Address0 : MAC Address0 - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param Addr: Pointer on MAC address buffer data (6 bytes). - * @retval : None + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval None */ void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) { @@ -1037,24 +1048,24 @@ void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) /* Calculate the selectecd MAC address high register */ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; /* Load the selectecd MAC address high register */ - (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) = tmpreg; + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; /* Calculate the selectecd MAC address low register */ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; /* Load the selectecd MAC address low register */ - (*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)) = tmpreg; + (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; } /** * @brief Get the selected MAC address. - * @param MacAddr: The MAC addres to return. + * @param MacAddr: The MAC addres to return. * This parameter can be one of the following values: - * @arg ETH_MAC_Address0 : MAC Address0 - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param Addr: Pointer on MAC address buffer data (6 bytes). - * @retval : None + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval None */ void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) { @@ -1063,13 +1074,13 @@ void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); /* Get the selectecd MAC address high register */ - tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)); + tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); /* Calculate the selectecd MAC address buffer */ Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); Addr[4] = (tmpreg & (uint8_t)0xFF); /* Load the selectecd MAC address low register */ - tmpreg =(*(__IO uint32_t *) (ETH_MAC_AddrLowBase + MacAddr)); + tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)); /* Calculate the selectecd MAC address buffer */ Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); @@ -1080,14 +1091,14 @@ void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) /** * @brief Enables or disables the Address filter module uses the specified * ETHERNET MAC address for perfect filtering - * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering. + * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering. * This parameter can be one of the following values: - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param NewState: new state of the specified ETHERNET MAC address use. + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param NewState: new state of the specified ETHERNET MAC address use. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) { @@ -1098,29 +1109,29 @@ void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) if (NewState != DISABLE) { /* Enable the selected ETHERNET MAC address for perfect filtering */ - (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_AE; + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; } else { /* Disable the selected ETHERNET MAC address for perfect filtering */ - (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); } } /** * @brief Set the filter type for the specified ETHERNET MAC address - * @param MacAddr: specifies the ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address * This parameter can be one of the following values: - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param Filter: specifies the used frame received field for comparaison + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Filter: specifies the used frame received field for comparaison * This parameter can be one of the following values: - * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare - * with the SA fields of the received frame. - * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare - * with the DA fields of the received frame. - * @retval : None + * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the + * SA fields of the received frame. + * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the + * DA fields of the received frame. + * @retval None */ void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) { @@ -1132,32 +1143,32 @@ void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) { /* The selected ETHERNET MAC address is used to compare with the SA fields of the received frame. */ - (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= ETH_MACA1HR_SA; + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; } else { /* The selected ETHERNET MAC address is used to compare with the DA fields of the received frame. */ - (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); } } /** * @brief Set the filter type for the specified ETHERNET MAC address - * @param MacAddr: specifies the ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address * This parameter can be one of the following values: - * @arg ETH_MAC_Address1 : MAC Address1 - * @arg ETH_MAC_Address2 : MAC Address2 - * @arg ETH_MAC_Address3 : MAC Address3 - * @param MaskByte: specifies the used address bytes for comparaison + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param MaskByte: specifies the used address bytes for comparaison * This parameter can be any combination of the following values: - * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. - * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. - * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. - * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16]. - * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8]. - * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0]. - * @retval : None + * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. + * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. + * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16]. + * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0]. + * @retval None */ void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) { @@ -1166,18 +1177,18 @@ void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); /* Clear MBC bits in the selected MAC address high register */ - (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); /* Set the selected Filetr mask bytes */ - (*(__IO uint32_t *) (ETH_MAC_AddrHighBase + MacAddr)) |= MaskByte; + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; } /*------------------------ DMA Tx/Rx Desciptors -----------------------------*/ /** * @brief Initializes the DMA Tx descriptors in chain mode. - * @param DMATxDescTab: Pointer on the first Tx desc list - * @param TxBuff: Pointer on the first TxBuffer list - * @param TxBuffCount: Number of the used Tx desc in the list - * @retval : None + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval None */ void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) { @@ -1216,13 +1227,13 @@ void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, u /** * @brief Initializes the DMA Tx descriptors in ring mode. - * @param DMATxDescTab: Pointer on the first Tx desc list - * @param TxBuff1: Pointer on the first TxBuffer1 list - * @param TxBuff2: Pointer on the first TxBuffer2 list - * @param TxBuffCount: Number of the used Tx desc in the list + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff1: Pointer on the first TxBuffer1 list + * @param TxBuff2: Pointer on the first TxBuffer2 list + * @param TxBuffCount: Number of the used Tx desc in the list * Note: see decriptor skip length defined in ETH_DMA_InitStruct * for the number of Words to skip between two unchained descriptors. - * @retval : None + * @retval None */ void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) { @@ -1257,34 +1268,34 @@ void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, u /** * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param ETH_DMATxDescFlag: specifies the flag to check. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param ETH_DMATxDescFlag: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine - * @arg ETH_DMATxDesc_IC : Interrupt on completetion - * @arg ETH_DMATxDesc_LS : Last Segment - * @arg ETH_DMATxDesc_FS : First Segment - * @arg ETH_DMATxDesc_DC : Disable CRC - * @arg ETH_DMATxDesc_DP : Disable Pad - * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable - * @arg ETH_DMATxDesc_TER : Transmit End of Ring - * @arg ETH_DMATxDesc_TCH : Second Address Chained - * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status - * @arg ETH_DMATxDesc_IHE : IP Header Error - * @arg ETH_DMATxDesc_ES : Error summary - * @arg ETH_DMATxDesc_JT : Jabber Timeout - * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush - * @arg ETH_DMATxDesc_PCE : Payload Checksum Error - * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission - * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver - * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision - * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions - * @arg ETH_DMATxDesc_VF : VLAN Frame - * @arg ETH_DMATxDesc_CC : Collision Count - * @arg ETH_DMATxDesc_ED : Excessive Deferral - * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory - * @arg ETH_DMATxDesc_DB : Deferred Bit - * @retval : The new state of ETH_DMATxDescFlag (SET or RESET). + * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMATxDesc_IC : Interrupt on completetion + * @arg ETH_DMATxDesc_LS : Last Segment + * @arg ETH_DMATxDesc_FS : First Segment + * @arg ETH_DMATxDesc_DC : Disable CRC + * @arg ETH_DMATxDesc_DP : Disable Pad + * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable + * @arg ETH_DMATxDesc_TER : Transmit End of Ring + * @arg ETH_DMATxDesc_TCH : Second Address Chained + * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status + * @arg ETH_DMATxDesc_IHE : IP Header Error + * @arg ETH_DMATxDesc_ES : Error summary + * @arg ETH_DMATxDesc_JT : Jabber Timeout + * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush + * @arg ETH_DMATxDesc_PCE : Payload Checksum Error + * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission + * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver + * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision + * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions + * @arg ETH_DMATxDesc_VF : VLAN Frame + * @arg ETH_DMATxDesc_CC : Collision Count + * @arg ETH_DMATxDesc_ED : Excessive Deferral + * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory + * @arg ETH_DMATxDesc_DB : Deferred Bit + * @retval The new state of ETH_DMATxDescFlag (SET or RESET). */ FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) { @@ -1305,19 +1316,19 @@ FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ET /** * @brief Returns the specified ETHERNET DMA Tx Desc collision count. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @retval : The Transmit descriptor collision counter value. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @retval The Transmit descriptor collision counter value. */ uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) { /* Return the Receive descriptor frame length */ - return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATxDesc_CollisionCountShift); + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); } /** * @brief Set the specified DMA Tx Desc Own bit. - * @param DMATxDesc: Pointer on a Tx desc - * @retval : None + * @param DMATxDesc: Pointer on a Tx desc + * @retval None */ void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) { @@ -1327,10 +1338,10 @@ void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) /** * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. - * @param DMATxDesc: Pointer on a Tx desc - * @param NewState: new state of the DMA Tx Desc transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param NewState: new state of the DMA Tx Desc transmit interrupt. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { @@ -1351,12 +1362,12 @@ void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalStat /** * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. - * @param DMATxDesc: Pointer on a Tx desc - * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment. + * @param DMATxDesc: Pointer on a Tx desc + * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment. * This parameter can be one of the following values: - * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment - * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment - * @retval : None + * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment + * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment + * @retval None */ void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) { @@ -1369,14 +1380,14 @@ void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMA /** * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion. * This parameter can be one of the following values: - * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass - * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum - * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval : None + * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass + * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @retval None */ void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) { @@ -1389,10 +1400,10 @@ void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_ /** * @brief Enables or disables the DMA Tx Desc CRC. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param NewState: new state of the specified DMA Tx Desc CRC. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc CRC. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { @@ -1413,10 +1424,10 @@ void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState /** * @brief Enables or disables the DMA Tx Desc end of ring. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param NewState: new state of the specified DMA Tx Desc end of ring. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc end of ring. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { @@ -1437,10 +1448,10 @@ void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState Ne /** * @brief Enables or disables the DMA Tx Desc second address chained. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param NewState: new state of the specified DMA Tx Desc second address chained. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc second address chained. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { @@ -1461,11 +1472,10 @@ void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, Functio /** * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param NewState: new state of the specified DMA Tx Desc padding for - * frame shorter than 64 bytes. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { @@ -1486,10 +1496,10 @@ void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, Functional /** * @brief Enables or disables the DMA Tx Desc time stamp. - * @param DMATxDesc: pointer on a DMA Tx descriptor - * @param NewState: new state of the specified DMA Tx Desc time stamp. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc time stamp. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) { @@ -1510,10 +1520,10 @@ void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState Ne /** * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. - * @param DMATxDesc: Pointer on a Tx desc - * @param BufferSize1: specifies the Tx desc buffer1 size. - * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used). - * @retval : None + * @param DMATxDesc: Pointer on a Tx desc + * @param BufferSize1: specifies the Tx desc buffer1 size. + * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used). + * @retval None */ void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) { @@ -1522,15 +1532,15 @@ void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t Buffe assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ - DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATxDesc_BufferSize2Shift)); + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); } /** * @brief Initializes the DMA Rx descriptors in chain mode. - * @param DMARxDescTab: Pointer on the first Rx desc list - * @param RxBuff: Pointer on the first RxBuffer list - * @param RxBuffCount: Number of the used Rx desc in the list - * @retval : None + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval None */ void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) { @@ -1571,13 +1581,13 @@ void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, u /** * @brief Initializes the DMA Rx descriptors in ring mode. - * @param DMARxDescTab: Pointer on the first Rx desc list - * @param RxBuff1: Pointer on the first RxBuffer1 list - * @param RxBuff2: Pointer on the first RxBuffer2 list - * @param RxBuffCount: Number of the used Rx desc in the list + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff1: Pointer on the first RxBuffer1 list + * @param RxBuff2: Pointer on the first RxBuffer2 list + * @param RxBuffCount: Number of the used Rx desc in the list * Note: see decriptor skip length defined in ETH_DMA_InitStruct * for the number of Words to skip between two unchained descriptors. - * @retval : None + * @retval None */ void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) { @@ -1615,28 +1625,28 @@ void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, u /** * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. - * @param DMARxDesc: pointer on a DMA Rx descriptor - * @param ETH_DMARxDescFlag: specifies the flag to check. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param ETH_DMARxDescFlag: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine - * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame - * @arg ETH_DMARxDesc_ES: Error summary - * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame - * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame - * @arg ETH_DMARxDesc_LE: Frame size not matching with length field - * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow - * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame - * @arg ETH_DMARxDesc_FS: First descriptor of the frame - * @arg ETH_DMARxDesc_LS: Last descriptor of the frame - * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error - * @arg ETH_DMARxDesc_LC: Late collision occurred during reception - * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 - * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception - * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface - * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits - * @arg ETH_DMARxDesc_CE: CRC error - * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error - * @retval : The new state of ETH_DMARxDescFlag (SET or RESET). + * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame + * @arg ETH_DMARxDesc_ES: Error summary + * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame + * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame + * @arg ETH_DMARxDesc_LE: Frame size not matching with length field + * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow + * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame + * @arg ETH_DMARxDesc_FS: First descriptor of the frame + * @arg ETH_DMARxDesc_LS: Last descriptor of the frame + * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMARxDesc_LC: Late collision occurred during reception + * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 + * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception + * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface + * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits + * @arg ETH_DMARxDesc_CE: CRC error + * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * @retval The new state of ETH_DMARxDescFlag (SET or RESET). */ FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) { @@ -1656,8 +1666,8 @@ FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ET /** * @brief Set the specified DMA Rx Desc Own bit. - * @param DMARxDesc: Pointer on a Rx desc - * @retval : None + * @param DMARxDesc: Pointer on a Rx desc + * @retval None */ void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) { @@ -1667,21 +1677,21 @@ void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) /** * @brief Returns the specified DMA Rx Desc frame length. - * @param DMARxDesc: pointer on a DMA Rx descriptor - * @retval : The Rx descriptor received frame length. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @retval The Rx descriptor received frame length. */ uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) { /* Return the Receive descriptor frame length */ - return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift); + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); } /** * @brief Enables or disables the specified DMA Rx Desc receive interrupt. - * @param DMARxDesc: Pointer on a Rx desc - * @param NewState: new state of the specified DMA Rx Desc interrupt. + * @param DMARxDesc: Pointer on a Rx desc + * @param NewState: new state of the specified DMA Rx Desc interrupt. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) { @@ -1702,10 +1712,10 @@ void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState /** * @brief Enables or disables the DMA Rx Desc end of ring. - * @param DMARxDesc: pointer on a DMA Rx descriptor - * @param NewState: new state of the specified DMA Rx Desc end of ring. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc end of ring. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) { @@ -1726,10 +1736,10 @@ void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState Ne /** * @brief Enables or disables the DMA Rx Desc second address chained. - * @param DMARxDesc: pointer on a DMA Rx descriptor - * @param NewState: new state of the specified DMA Rx Desc second address chained. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc second address chained. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) { @@ -1750,12 +1760,12 @@ void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, Functio /** * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. - * @param DMARxDesc: pointer on a DMA Rx descriptor - * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. * This parameter can be any one of the following values: - * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 - * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 - * @retval : The Receive descriptor frame length. + * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 + * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 + * @retval The Receive descriptor frame length. */ uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) { @@ -1765,7 +1775,7 @@ uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMAR if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) { /* Return the DMA Rx Desc buffer2 size */ - return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARxDesc_Buffer2SizeShift); + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); } else { @@ -1778,7 +1788,7 @@ uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMAR /** * @brief Resets all MAC subsystem internal registers and logic. * @param None - * @retval : None + * @retval None */ void ETH_SoftwareReset(void) { @@ -1790,7 +1800,7 @@ void ETH_SoftwareReset(void) /** * @brief Checks whether the ETHERNET software reset bit is set or not. * @param None - * @retval : The new state of DMA Bus Mode register SR bit (SET or RESET). + * @retval The new state of DMA Bus Mode register SR bit (SET or RESET). */ FlagStatus ETH_GetSoftwareResetStatus(void) { @@ -1808,30 +1818,30 @@ FlagStatus ETH_GetSoftwareResetStatus(void) /** * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * @param ETH_DMA_FLAG: specifies the flag to check. + * @param ETH_DMA_FLAG: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag - * @arg ETH_DMA_FLAG_PMT : PMT flag - * @arg ETH_DMA_FLAG_MMC : MMC flag - * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access - * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr - * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA - * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag - * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag - * @arg ETH_DMA_FLAG_ER : Early receive flag - * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag - * @arg ETH_DMA_FLAG_ET : Early transmit flag - * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag - * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag - * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag - * @arg ETH_DMA_FLAG_R : Receive flag - * @arg ETH_DMA_FLAG_TU : Underflow flag - * @arg ETH_DMA_FLAG_RO : Overflow flag - * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag - * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag - * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag - * @arg ETH_DMA_FLAG_T : Transmit flag - * @retval : The new state of ETH_DMA_FLAG (SET or RESET). + * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag + * @arg ETH_DMA_FLAG_PMT : PMT flag + * @arg ETH_DMA_FLAG_MMC : MMC flag + * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access + * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr + * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Underflow flag + * @arg ETH_DMA_FLAG_RO : Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval The new state of ETH_DMA_FLAG (SET or RESET). */ FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) { @@ -1850,25 +1860,25 @@ FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) } /** - * @brief Clears the ETHERNET’s DMA pending flag. - * @param ETH_DMA_FLAG: specifies the flag to clear. + * @brief Clears the ETHERNET's DMA pending flag. + * @param ETH_DMA_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: - * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag - * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag - * @arg ETH_DMA_FLAG_ER : Early receive flag - * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag - * @arg ETH_DMA_FLAG_ETI : Early transmit flag - * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag - * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag - * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag - * @arg ETH_DMA_FLAG_R : Receive flag - * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag - * @arg ETH_DMA_FLAG_RO : Receive Overflow flag - * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag - * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag - * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag - * @arg ETH_DMA_FLAG_T : Transmit flag - * @retval : None + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ETI : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag + * @arg ETH_DMA_FLAG_RO : Receive Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval None */ void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) { @@ -1881,27 +1891,27 @@ void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) /** * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. - * @param ETH_DMA_IT: specifies the interrupt source to check. + * @param ETH_DMA_IT: specifies the interrupt source to check. * This parameter can be one of the following values: - * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt - * @arg ETH_DMA_IT_PMT : PMT interrupt - * @arg ETH_DMA_IT_MMC : MMC interrupt - * @arg ETH_DMA_IT_NIS : Normal interrupt summary - * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_IT_ER : Early receive interrupt - * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_IT_ET : Early transmit interrupt - * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_IT_R : Receive interrupt - * @arg ETH_DMA_IT_TU : Underflow interrupt - * @arg ETH_DMA_IT_RO : Overflow interrupt - * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_IT_T : Transmit interrupt - * @retval : The new state of ETH_DMA_IT (SET or RESET). + * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt + * @arg ETH_DMA_IT_PMT : PMT interrupt + * @arg ETH_DMA_IT_MMC : MMC interrupt + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval The new state of ETH_DMA_IT (SET or RESET). */ ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) { @@ -1920,25 +1930,25 @@ ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) } /** - * @brief Clears the ETHERNET’s DMA IT pending bit. - * @param ETH_DMA_IT: specifies the interrupt pending bit to clear. + * @brief Clears the ETHERNET's DMA IT pending bit. + * @param ETH_DMA_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: - * @arg ETH_DMA_IT_NIS : Normal interrupt summary - * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_IT_ER : Early receive interrupt - * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_IT_ETI : Early transmit interrupt - * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_IT_R : Receive interrupt - * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt - * @arg ETH_DMA_IT_RO : Receive Overflow interrupt - * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_IT_T : Transmit interrupt - * @retval : None + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ETI : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt + * @arg ETH_DMA_IT_RO : Receive Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval None */ void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) { @@ -1952,14 +1962,14 @@ void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) /** * @brief Returns the ETHERNET DMA Transmit Process State. * @param None - * @retval : The new ETHERNET DMA Transmit Process State: + * @retval The new ETHERNET DMA Transmit Process State: * This can be one of the following values: - * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued - * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor - * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status - * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory - * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe - * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor + * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor + * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status + * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory + * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe + * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor */ uint32_t ETH_GetTransmitProcessState(void) { @@ -1969,14 +1979,14 @@ uint32_t ETH_GetTransmitProcessState(void) /** * @brief Returns the ETHERNET DMA Receive Process State. * @param None - * @retval : The new ETHERNET DMA Receive Process State: + * @retval The new ETHERNET DMA Receive Process State: * This can be one of the following values: - * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued - * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor - * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet - * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable - * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor - * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory + * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor + * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet + * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable + * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor + * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory */ uint32_t ETH_GetReceiveProcessState(void) { @@ -1986,7 +1996,7 @@ uint32_t ETH_GetReceiveProcessState(void) /** * @brief Clears the ETHERNET transmit FIFO. * @param None - * @retval : None + * @retval None */ void ETH_FlushTransmitFIFO(void) { @@ -1997,7 +2007,7 @@ void ETH_FlushTransmitFIFO(void) /** * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. * @param None - * @retval : The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET). */ FlagStatus ETH_GetFlushTransmitFIFOStatus(void) { @@ -2015,9 +2025,9 @@ FlagStatus ETH_GetFlushTransmitFIFOStatus(void) /** * @brief Enables or disables the DMA transmission. - * @param NewState: new state of the DMA transmission. + * @param NewState: new state of the DMA transmission. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMATransmissionCmd(FunctionalState NewState) { @@ -2038,9 +2048,9 @@ void ETH_DMATransmissionCmd(FunctionalState NewState) /** * @brief Enables or disables the DMA reception. - * @param NewState: new state of the DMA reception. + * @param NewState: new state of the DMA reception. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMAReceptionCmd(FunctionalState NewState) { @@ -2061,27 +2071,27 @@ void ETH_DMAReceptionCmd(FunctionalState NewState) /** * @brief Enables or disables the specified ETHERNET DMA interrupts. - * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be + * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be * enabled or disabled. * This parameter can be any combination of the following values: - * @arg ETH_DMA_IT_NIS : Normal interrupt summary - * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary - * @arg ETH_DMA_IT_ER : Early receive interrupt - * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt - * @arg ETH_DMA_IT_ET : Early transmit interrupt - * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt - * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt - * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt - * @arg ETH_DMA_IT_R : Receive interrupt - * @arg ETH_DMA_IT_TU : Underflow interrupt - * @arg ETH_DMA_IT_RO : Overflow interrupt - * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt - * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt - * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt - * @arg ETH_DMA_IT_T : Transmit interrupt - * @param NewState: new state of the specified ETHERNET DMA interrupts. + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @param NewState: new state of the specified ETHERNET DMA interrupts. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) { @@ -2103,11 +2113,11 @@ void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) /** * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. - * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check. + * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check. * This parameter can be one of the following values: - * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter - * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter - * @retval : The new state of ETHERNET DMA overflow Flag (SET or RESET). + * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter + * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter + * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET). */ FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) { @@ -2129,17 +2139,17 @@ FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) /** * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. * @param None - * @retval : The value of Rx overflow Missed Frame Counter. + * @retval The value of Rx overflow Missed Frame Counter. */ uint32_t ETH_GetRxOverflowMissedFrameCounter(void) { - return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RxOverflowMissedFramesCounterShift)); + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); } /** * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. * @param None - * @retval : The value of Buffer unavailable Missed Frame Counter. + * @retval The value of Buffer unavailable Missed Frame Counter. */ uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) { @@ -2149,7 +2159,7 @@ uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) /** * @brief Get the ETHERNET DMA DMACHTDR register value. * @param None - * @retval : The value of the current Tx desc start address. + * @retval The value of the current Tx desc start address. */ uint32_t ETH_GetCurrentTxDescStartAddress(void) { @@ -2159,7 +2169,7 @@ uint32_t ETH_GetCurrentTxDescStartAddress(void) /** * @brief Get the ETHERNET DMA DMACHRDR register value. * @param None - * @retval : The value of the current Rx desc start address. + * @retval The value of the current Rx desc start address. */ uint32_t ETH_GetCurrentRxDescStartAddress(void) { @@ -2169,7 +2179,7 @@ uint32_t ETH_GetCurrentRxDescStartAddress(void) /** * @brief Get the ETHERNET DMA DMACHTBAR register value. * @param None - * @retval : The value of the current Tx desc buffer address. + * @retval The value of the current Tx buffer address. */ uint32_t ETH_GetCurrentTxBufferAddress(void) { @@ -2179,7 +2189,7 @@ uint32_t ETH_GetCurrentTxBufferAddress(void) /** * @brief Get the ETHERNET DMA DMACHRBAR register value. * @param None - * @retval : The value of the current Rx desc buffer address. + * @retval The value of the current Rx buffer address. */ uint32_t ETH_GetCurrentRxBufferAddress(void) { @@ -2187,11 +2197,10 @@ uint32_t ETH_GetCurrentRxBufferAddress(void) } /** - * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand - * register: (the data written could be anything). This forces - * the DMA to resume transmission. + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register + * (the data written could be anything). This forces the DMA to resume transmission. * @param None - * @retval : None. + * @retval None. */ void ETH_ResumeDMATransmission(void) { @@ -2199,11 +2208,10 @@ void ETH_ResumeDMATransmission(void) } /** - * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand - * register: (the data written could be anything). This forces - * the DMA to resume reception. + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register + * (the data written could be anything). This forces the DMA to resume reception. * @param None - * @retval : None. + * @retval None. */ void ETH_ResumeDMAReception(void) { @@ -2214,7 +2222,7 @@ void ETH_ResumeDMAReception(void) /** * @brief Reset Wakeup frame filter register pointer. * @param None - * @retval : None + * @retval None */ void ETH_ResetWakeUpFrameFilterRegisterPointer(void) { @@ -2224,16 +2232,15 @@ void ETH_ResetWakeUpFrameFilterRegisterPointer(void) /** * @brief Populates the remote wakeup frame registers. - * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer - * data (8 words). - * @retval : None + * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words). + * @retval None */ void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) { uint32_t i = 0; /* Fill Remote Wake-up Frame Filter register with Buffer data */ - for(i =0; iMACRWUFFR = Buffer[i]; @@ -2241,11 +2248,11 @@ void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) } /** - * @brief Enables or disables any unicast packet filtered by the MAC - * (DAF) address recognition to be a wake-up frame. - * @param NewState: new state of the MAC Global Unicast Wake-Up. + * @brief Enables or disables any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * @param NewState: new state of the MAC Global Unicast Wake-Up. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) { @@ -2266,12 +2273,12 @@ void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) /** * @brief Checks whether the specified ETHERNET PMT flag is set or not. - * @param ETH_PMT_FLAG: specifies the flag to check. + * @param ETH_PMT_FLAG: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval : The new state of ETHERNET PMT Flag (SET or RESET). + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * @retval The new state of ETHERNET PMT Flag (SET or RESET). */ FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) { @@ -2292,9 +2299,9 @@ FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) /** * @brief Enables or disables the MAC Wake-Up Frame Detection. - * @param NewState: new state of the MAC Wake-Up Frame Detection. + * @param NewState: new state of the MAC Wake-Up Frame Detection. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) { @@ -2315,9 +2322,9 @@ void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) /** * @brief Enables or disables the MAC Magic Packet Detection. - * @param NewState: new state of the MAC Magic Packet Detection. + * @param NewState: new state of the MAC Magic Packet Detection. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_MagicPacketDetectionCmd(FunctionalState NewState) { @@ -2338,9 +2345,9 @@ void ETH_MagicPacketDetectionCmd(FunctionalState NewState) /** * @brief Enables or disables the MAC Power Down. - * @param NewState: new state of the MAC Power Down. + * @param NewState: new state of the MAC Power Down. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_PowerDownCmd(FunctionalState NewState) { @@ -2363,9 +2370,9 @@ void ETH_PowerDownCmd(FunctionalState NewState) /*--------------------------------- MMC ------------------------------------*/ /** * @brief Enables or disables the MMC Counter Freeze. - * @param NewState: new state of the MMC Counter Freeze. + * @param NewState: new state of the MMC Counter Freeze. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_MMCCounterFreezeCmd(FunctionalState NewState) { @@ -2386,9 +2393,9 @@ void ETH_MMCCounterFreezeCmd(FunctionalState NewState) /** * @brief Enables or disables the MMC Reset On Read. - * @param NewState: new state of the MMC Reset On Read. + * @param NewState: new state of the MMC Reset On Read. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_MMCResetOnReadCmd(FunctionalState NewState) { @@ -2409,9 +2416,9 @@ void ETH_MMCResetOnReadCmd(FunctionalState NewState) /** * @brief Enables or disables the MMC Counter Stop Rollover. - * @param NewState: new state of the MMC Counter Stop Rollover. + * @param NewState: new state of the MMC Counter Stop Rollover. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_MMCCounterRolloverCmd(FunctionalState NewState) { @@ -2433,7 +2440,7 @@ void ETH_MMCCounterRolloverCmd(FunctionalState NewState) /** * @brief Resets the MMC Counters. * @param None - * @retval : None + * @retval None */ void ETH_MMCCountersReset(void) { @@ -2443,19 +2450,18 @@ void ETH_MMCCountersReset(void) /** * @brief Enables or disables the specified ETHERNET MMC interrupts. - * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt - * sources to be enabled or disabled. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. * This parameter can be any combination of Tx interrupt or * any combination of Rx interrupt (but not both)of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @param NewState: new state of the specified ETHERNET MMC interrupts. + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @param NewState: new state of the specified ETHERNET MMC interrupts. * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) { @@ -2498,15 +2504,15 @@ void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) /** * @brief Checks whether the specified ETHERNET MMC IT is set or not. - * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt. * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value - * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value - * @retval : The value of ETHERNET MMC IT (SET or RESET). + * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value + * @retval The value of ETHERNET MMC IT (SET or RESET). */ ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) { @@ -2546,20 +2552,20 @@ ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) /** * @brief Get the specified ETHERNET MMC register value. - * @param ETH_MMCReg: specifies the ETHERNET MMC register. + * @param ETH_MMCReg: specifies the ETHERNET MMC register. * This parameter can be one of the following values: - * @arg ETH_MMCCR : MMC CR register - * @arg ETH_MMCRIR : MMC RIR register - * @arg ETH_MMCTIR : MMC TIR register - * @arg ETH_MMCRIMR : MMC RIMR register - * @arg ETH_MMCTIMR : MMC TIMR register - * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register - * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register - * @arg ETH_MMCTGFCR : MMC TGFCR register - * @arg ETH_MMCRFCECR : MMC RFCECR register - * @arg ETH_MMCRFAECR : MMC RFAECR register - * @arg ETH_MMCRGUFCR : MMC RGUFCRregister - * @retval : The value of ETHERNET MMC Register value. + * @arg ETH_MMCCR : MMC CR register + * @arg ETH_MMCRIR : MMC RIR register + * @arg ETH_MMCTIR : MMC TIR register + * @arg ETH_MMCRIMR : MMC RIMR register + * @arg ETH_MMCTIMR : MMC TIMR register + * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register + * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register + * @arg ETH_MMCTGFCR : MMC TGFCR register + * @arg ETH_MMCRFCECR : MMC RFCECR register + * @arg ETH_MMCRFAECR : MMC RFAECR register + * @arg ETH_MMCRGUFCR : MMC RGUFCRregister + * @retval The value of ETHERNET MMC Register value. */ uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) { @@ -2572,10 +2578,9 @@ uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) /*--------------------------------- PTP ------------------------------------*/ /** - * @brief Updated the PTP block for fine correction with the Time Stamp - * Addend register value. + * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value. * @param None - * @retval : None + * @retval None */ void ETH_EnablePTPTimeStampAddend(void) { @@ -2586,7 +2591,7 @@ void ETH_EnablePTPTimeStampAddend(void) /** * @brief Enable the PTP Time Stamp interrupt trigger * @param None - * @retval : None + * @retval None */ void ETH_EnablePTPTimeStampInterruptTrigger(void) { @@ -2595,10 +2600,9 @@ void ETH_EnablePTPTimeStampInterruptTrigger(void) } /** - * @brief Updated the PTP system time with the Time Stamp Update register - * value. + * @brief Updated the PTP system time with the Time Stamp Update register value. * @param None - * @retval : None + * @retval None */ void ETH_EnablePTPTimeStampUpdate(void) { @@ -2609,7 +2613,7 @@ void ETH_EnablePTPTimeStampUpdate(void) /** * @brief Initialize the PTP Time Stamp * @param None - * @retval : None + * @retval None */ void ETH_InitializePTPTimeStamp(void) { @@ -2619,11 +2623,11 @@ void ETH_InitializePTPTimeStamp(void) /** * @brief Selects the PTP Update method - * @param UpdateMethod: the PTP Update method + * @param UpdateMethod: the PTP Update method * This parameter can be one of the following values: - * @arg ETH_PTP_FineUpdate : Fine Update method - * @arg ETH_PTP_CoarseUpdate : Coarse Update method - * @retval : None + * @arg ETH_PTP_FineUpdate : Fine Update method + * @arg ETH_PTP_CoarseUpdate : Coarse Update method + * @retval None */ void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) { @@ -2644,9 +2648,9 @@ void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) /** * @brief Enables or disables the PTP time stamp for transmit and receive frames. - * @param NewState: new state of the PTP time stamp for transmit and receive frames + * @param NewState: new state of the PTP time stamp for transmit and receive frames * This parameter can be: ENABLE or DISABLE. - * @retval : None + * @retval None */ void ETH_PTPTimeStampCmd(FunctionalState NewState) { @@ -2667,13 +2671,13 @@ void ETH_PTPTimeStampCmd(FunctionalState NewState) /** * @brief Checks whether the specified ETHERNET PTP flag is set or not. - * @param ETH_PTP_FLAG: specifies the flag to check. + * @param ETH_PTP_FLAG: specifies the flag to check. * This parameter can be one of the following values: - * @arg ETH_PTP_FLAG_TSARU : Addend Register Update - * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable - * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update - * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize - * @retval : The new state of ETHERNET PTP Flag (SET or RESET). + * @arg ETH_PTP_FLAG_TSARU : Addend Register Update + * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable + * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update + * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize + * @retval The new state of ETHERNET PTP Flag (SET or RESET). */ FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) { @@ -2694,8 +2698,8 @@ FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) /** * @brief Sets the system time Sub-Second Increment value. - * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value. - * @retval : None + * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value. + * @retval None */ void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) { @@ -2707,14 +2711,14 @@ void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) /** * @brief Sets the Time Stamp update sign and values. - * @param Sign: specifies the PTP Time update value sign. + * @param Sign: specifies the PTP Time update value sign. * This parameter can be one of the following values: - * @arg ETH_PTP_PositiveTime : positive time value. - * @arg ETH_PTP_NegativeTime : negative time value. - * @param SecondValue: specifies the PTP Time update second value. - * @param SubSecondValue: specifies the PTP Time update sub-second value. - * this is a 31 bit value. bit32 correspond to the sign. - * @retval : None + * @arg ETH_PTP_PositiveTime : positive time value. + * @arg ETH_PTP_NegativeTime : negative time value. + * @param SecondValue: specifies the PTP Time update second value. + * @param SubSecondValue: specifies the PTP Time update sub-second value. + * This parameter is a 31 bit value, bit32 correspond to the sign. + * @retval None */ void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) { @@ -2730,8 +2734,8 @@ void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t Sub /** * @brief Sets the Time Stamp Addend value. - * @param Value: specifies the PTP Time Stamp Addend Register value. - * @retval : None + * @param Value: specifies the PTP Time Stamp Addend Register value. + * @retval None */ void ETH_SetPTPTimeStampAddend(uint32_t Value) { @@ -2741,9 +2745,9 @@ void ETH_SetPTPTimeStampAddend(uint32_t Value) /** * @brief Sets the Target Time registers values. - * @param HighValue: specifies the PTP Target Time High Register value. - * @param LowValue: specifies the PTP Target Time Low Register value. - * @retval : None + * @param HighValue: specifies the PTP Target Time High Register value. + * @param LowValue: specifies the PTP Target Time Low Register value. + * @retval None */ void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) { @@ -2755,18 +2759,18 @@ void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) /** * @brief Get the specified ETHERNET PTP register value. - * @param ETH_PTPReg: specifies the ETHERNET PTP register. + * @param ETH_PTPReg: specifies the ETHERNET PTP register. * This parameter can be one of the following values: - * @arg ETH_PTPTSCR : Sub-Second Increment Register - * @arg ETH_PTPSSIR : Sub-Second Increment Register - * @arg ETH_PTPTSHR : Time Stamp High Register - * @arg ETH_PTPTSLR : Time Stamp Low Register - * @arg ETH_PTPTSHUR : Time Stamp High Update Register - * @arg ETH_PTPTSLUR : Time Stamp Low Update Register - * @arg ETH_PTPTSAR : Time Stamp Addend Register - * @arg ETH_PTPTTHR : Target Time High Register - * @arg ETH_PTPTTLR : Target Time Low Register - * @retval : The value of ETHERNET PTP Register value. + * @arg ETH_PTPTSCR : Sub-Second Increment Register + * @arg ETH_PTPSSIR : Sub-Second Increment Register + * @arg ETH_PTPTSHR : Time Stamp High Register + * @arg ETH_PTPTSLR : Time Stamp Low Register + * @arg ETH_PTPTSHUR : Time Stamp High Update Register + * @arg ETH_PTPTSLUR : Time Stamp Low Update Register + * @arg ETH_PTPTSAR : Time Stamp Addend Register + * @arg ETH_PTPTTHR : Target Time High Register + * @arg ETH_PTPTTLR : Target Time Low Register + * @retval The value of ETHERNET PTP Register value. */ uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) { @@ -2779,13 +2783,14 @@ uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) /** * @brief Initializes the DMA Tx descriptors in chain mode with PTP. - * @param DMATxDescTab: Pointer on the first Tx desc list - * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list - * @param TxBuff: Pointer on the first TxBuffer list - * @param TxBuffCount: Number of the used Tx desc in the list - * @retval : None + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval None */ -void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, + uint8_t* TxBuff, uint32_t TxBuffCount) { uint32_t i = 0; ETH_DMADESCTypeDef *DMATxDesc; @@ -2828,13 +2833,14 @@ void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCType /** * @brief Initializes the DMA Rx descriptors in chain mode. - * @param DMARxDescTab: Pointer on the first Rx desc list - * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list - * @param RxBuff: Pointer on the first RxBuffer list - * @param RxBuffCount: Number of the used Rx desc in the list - * @retval : None + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval None */ -void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, + uint8_t *RxBuff, uint32_t RxBuffCount) { uint32_t i = 0; ETH_DMADESCTypeDef *DMARxDesc; @@ -2878,13 +2884,12 @@ void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCType } /** - * @brief Transmits a packet, from application buffer, pointed by ppkt with - * Time Stamp values. - * @param ppkt: pointer to application packet buffer to transmit. - * @param FrameLength: Tx Packet size. - * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values. - * @retval : ETH_ERROR: in case of Tx desc owned by DMA - * ETH_SUCCESS: for correct transmission + * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values. + * @retval ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission */ uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) { @@ -2964,12 +2969,11 @@ uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTx } /** - * @brief Receives a packet and copies it to memory pointed by ppkt with - * Time Stamp values. + * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. * @param ppkt: pointer to application packet receive buffer. - * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values. - * @retval : ETH_ERROR: if there is error in reception - * framelength: received packet size if packet reception is correct + * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values. + * @retval ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct */ uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) { @@ -2985,7 +2989,7 @@ uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) { /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ for(offset=0; offset #include "lwipopts.h" -#define STM32_ETH_DEBUG 0 +#define STM32_ETH_DEBUG +//#define STM32_ETH_PHY_DUMP +//#define STM32_ETH_RX_DUMP +//#define STM32_ETH_TX_DUMP -#define MII_MODE /* MII mode for STM3210C-EVAL Board (MB784) (check jumpers setting) */ -#define CHECKSUM_BY_HARDWARE -#define DP83848_PHY /* Ethernet pins mapped on STM3210C-EVAL Board */ -#define PHY_ADDRESS 0x01 /* Relative to STM3210C-EVAL Board */ +#ifdef STM32_ETH_DEBUG +#define STM32_ETH_TRACE rt_kprintf +#else +#define STM32_ETH_TRACE(...) +#endif #define ETH_RXBUFNB 4 #define ETH_TXBUFNB 2 @@ -3077,11 +3082,11 @@ static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB #define MAX_ADDR_LEN 6 struct rt_stm32_eth { - /* inherit from ethernet device */ - struct eth_device parent; + /* inherit from ethernet device */ + struct eth_device parent; - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ }; static struct rt_stm32_eth stm32_eth_device; static struct rt_semaphore tx_buf_free; @@ -3089,7 +3094,7 @@ static struct rt_semaphore tx_buf_free; /* interrupt service routine for ETH */ void ETH_IRQHandler(void) { - rt_uint32_t status; + rt_uint32_t status; /* enter interrupt */ rt_interrupt_enter(); @@ -3097,36 +3102,39 @@ void ETH_IRQHandler(void) /* get DMA IT status */ status = ETH->DMASR; - if ( (status & ETH_DMA_IT_R) != (u32)RESET ) /* packet receiption */ - { - /* a frame has been received */ - eth_device_ready(&(stm32_eth_device.parent)); - ETH_DMAClearITPendingBit(ETH_DMA_IT_R); - } + if ( (status & ETH_DMA_IT_R) != (u32)RESET ) /* packet receiption */ + { + /* a frame has been received */ + eth_device_ready(&(stm32_eth_device.parent)); - if ( (status & ETH_DMA_IT_T) != (u32)RESET ) /* packet transmission */ - { + ETH_DMAClearITPendingBit(ETH_DMA_IT_R); + } + + if ( (status & ETH_DMA_IT_T) != (u32)RESET ) /* packet transmission */ + { rt_sem_release(&tx_buf_free); - ETH_DMAClearITPendingBit(ETH_DMA_IT_T); - } + ETH_DMAClearITPendingBit(ETH_DMA_IT_T); + } - /* Clear received IT */ - if ((status & ETH_DMA_IT_NIS) != (u32)RESET) - ETH->DMASR = (u32)ETH_DMA_IT_NIS; - if ((status & ETH_DMA_IT_AIS) != (u32)RESET) - ETH->DMASR = (u32)ETH_DMA_IT_AIS; - if ((status & ETH_DMA_IT_RO) != (u32)RESET) - ETH->DMASR = (u32)ETH_DMA_IT_RO; - if ((status & ETH_DMA_IT_RBU) != (u32)RESET) - { - ETH_ResumeDMAReception(); - ETH->DMASR = (u32)ETH_DMA_IT_RBU; - } - if ((status & ETH_DMA_IT_TBU) != (u32)RESET) - { - ETH_ResumeDMATransmission(); - ETH->DMASR = (u32)ETH_DMA_IT_TBU; - } + /* Clear received IT */ + if ((status & ETH_DMA_IT_NIS) != (u32)RESET) + ETH->DMASR = (u32)ETH_DMA_IT_NIS; + if ((status & ETH_DMA_IT_AIS) != (u32)RESET) + ETH->DMASR = (u32)ETH_DMA_IT_AIS; + if ((status & ETH_DMA_IT_RO) != (u32)RESET) + ETH->DMASR = (u32)ETH_DMA_IT_RO; + + if ((status & ETH_DMA_IT_RBU) != (u32)RESET) + { + ETH_ResumeDMAReception(); + ETH->DMASR = (u32)ETH_DMA_IT_RBU; + } + + if ((status & ETH_DMA_IT_TBU) != (u32)RESET) + { + ETH_ResumeDMATransmission(); + ETH->DMASR = (u32)ETH_DMA_IT_TBU; + } /* leave interrupt */ rt_interrupt_leave(); @@ -3137,44 +3145,44 @@ void ETH_IRQHandler(void) void EXTI9_5_IRQHandler(void) { - volatile rt_uint16_t status; + volatile rt_uint16_t status; - /* enter interrupt */ - rt_interrupt_enter(); + /* enter interrupt */ + rt_interrupt_enter(); - status = ETH_ReadPHYRegister(PHY_ADDRESS, MISR); - if (status & (1 << 13)) - { - /* change of link */ - status = ETH_ReadPHYRegister(PHY_ADDRESS, PHY_SR); - if (status & 0x01) /* link established */ - { - netif_set_link_up(stm32_eth_device.parent.netif); - } - else - { - netif_set_link_down(stm32_eth_device.parent.netif); - } - } + status = ETH_ReadPHYRegister(PHY_ADDRESS, MISR); + if (status & (1 << 13)) + { + /* change of link */ + status = ETH_ReadPHYRegister(PHY_ADDRESS, PHY_SR); + if (status & 0x01) /* link established */ + { + netif_set_link_up(stm32_eth_device.parent.netif); + } + else + { + netif_set_link_down(stm32_eth_device.parent.netif); + } + } - /* Clear the Key Button EXTI line pending bit */ - EXTI_ClearITPendingBit(EXTI_Line5); + /* Clear the Key Button EXTI line pending bit */ + EXTI_ClearITPendingBit(EXTI_Line5); - /* leave interrupt */ - rt_interrupt_leave(); + /* leave interrupt */ + rt_interrupt_leave(); } void rt_eth_phy_init(void) { - GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitTypeDef GPIO_InitStructure; EXTI_InitTypeDef EXTI_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; - /* Configure PC5 as input for PHY interrupt */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - GPIO_Init(GPIOC, &GPIO_InitStructure); + /* Configure PC5 as input for PHY interrupt */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); /* Connect PHY Interrupt Line to GPIOC Pin 5 */ GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, GPIO_PinSource5); @@ -3186,9 +3194,9 @@ void rt_eth_phy_init(void) EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); - /* set PHY interrupt */ - ETH_WritePHYRegister(PHY_ADDRESS, MICR, 0x0003); - ETH_WritePHYRegister(PHY_ADDRESS, MISR, 0x0060); + /* set PHY interrupt */ + ETH_WritePHYRegister(PHY_ADDRESS, MICR, 0x0003); + ETH_WritePHYRegister(PHY_ADDRESS, MISR, 0x0060); /* Clear PHY Interrupt Line pending bit */ EXTI_ClearITPendingBit(EXTI_Line5); @@ -3204,49 +3212,52 @@ void rt_eth_phy_init(void) } /* RT-Thread Device Interface */ + /* initialize the interface */ static rt_err_t rt_stm32_eth_init(rt_device_t dev) { - vu32 Value = 0; + vu32 Value = 0; - /* Reset ETHERNET on AHB Bus */ - ETH_DeInit(); + /* Reset ETHERNET on AHB Bus */ + ETH_DeInit(); - /* Software reset */ - ETH_SoftwareReset(); + /* Software reset */ + ETH_SoftwareReset(); - /* Wait for software reset */ - while(ETH_GetSoftwareResetStatus()==SET); + /* Wait for software reset */ + while(ETH_GetSoftwareResetStatus()==SET); - /* ETHERNET Configuration ------------------------------------------------------*/ - /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ - ETH_StructInit(Ð_InitStructure); + /* ETHERNET Configuration ------------------------------------------------------*/ + /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ + ETH_StructInit(Ð_InitStructure); - /* Fill ETH_InitStructure parametrs */ - /*------------------------ MAC -----------------------------------*/ - ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable ; - ETH_InitStructure.ETH_Speed = ETH_Speed_100M; - ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; + /* Fill ETH_InitStructure parametrs */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable ; + ETH_InitStructure.ETH_Speed = ETH_Speed_100M; + ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; - ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; - ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; - ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; - ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; - ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; - ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; - ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; + ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; + ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; #ifdef CHECKSUM_BY_HARDWARE ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; #endif /*------------------------ DMA -----------------------------------*/ + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; @@ -3278,52 +3289,49 @@ static rt_err_t rt_stm32_eth_init(rt_device_t dev) static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_stm32_eth_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_set_errno(-RT_ENOSYS); - return 0; + rt_set_errno(-RT_ENOSYS); + return 0; } static rt_err_t rt_stm32_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args) { - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6); - else return -RT_ERROR; - break; + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6); + else return -RT_ERROR; + break; - default : - break; - } + default : + break; + } - return RT_EOK; + return RT_EOK; } /* ethernet device interface */ /* transmit packet. */ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) { -#if STM32_ETH_DEBUG - int cnt = 0; -#endif - struct pbuf* q; - rt_uint32_t offset; + struct pbuf* q; + rt_uint32_t offset; /* get free tx buffer */ { @@ -3332,33 +3340,47 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) if (result != RT_EOK) return -RT_ERROR; } -#if STM32_ETH_DEBUG - rt_kprintf("tx dump:\n"); -#endif - offset = 0; - for (q = p; q != NULL; q = q->next) - { - rt_uint8_t* ptr; - rt_uint32_t len; + offset = 0; + for (q = p; q != NULL; q = q->next) + { + rt_uint8_t* ptr; + rt_uint32_t len; - len = q->len; - ptr = q->payload; + len = q->len; + ptr = q->payload; - /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ - while (len) - { - (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = *ptr; + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + while (len) + { + (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = *ptr; -#if STM32_ETH_DEBUG - rt_kprintf("%02x ", *ptr); - if (++cnt % 16 == 0) rt_kprintf("\n"); -#endif - offset ++; ptr ++; len --; - } - } + offset ++; + ptr ++; + len --; + } + } -#if STM32_ETH_DEBUG - rt_kprintf("\n"); +#ifdef STM32_ETH_TX_DUMP + { + rt_uint32_t i; + rt_uint8_t *ptr = (rt_uint8_t*)(DMATxDescToSet->Buffer1Addr); + + STM32_ETH_TRACE("tx_dump:"); + for(i=0; itot_len; i++) + { + if( (i%8) == 0 ) + { + STM32_ETH_TRACE(" "); + } + if( (i%16) == 0 ) + { + STM32_ETH_TRACE("\r\n"); + } + STM32_ETH_TRACE("%02x ",*ptr); + ptr++; + } + STM32_ETH_TRACE("\r\ndump done!\r\n"); + } #endif /* Setting the Frame Length: bits[12:0] */ @@ -3385,144 +3407,114 @@ rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) } } #endif - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMASR_TBUS; - /* Transmit Poll Demand to resume DMA transmission*/ - ETH->DMATPDR = 0; -#if STM32_ETH_DEBUG - rt_kprintf("transmit poll demand\n"); -#endif - } + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Transmit Poll Demand to resume DMA transmission*/ + ETH->DMATPDR = 0; + STM32_ETH_TRACE("transmit poll demand\n"); + } - /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ - /* Chained Mode */ - if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) - { - /* Selects the next DMA Tx descriptor list for next buffer to send */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); - } - else /* Ring Mode */ - { - if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) - { - /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); - } - else - { - /* Selects the next DMA Tx descriptor list for next buffer to send */ - DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - } - } + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); - /* Return SUCCESS */ - return RT_EOK; + /* Return SUCCESS */ + return RT_EOK; } /* reception packet. */ struct pbuf *rt_stm32_eth_rx(rt_device_t dev) { - struct pbuf* p; - rt_uint32_t offset = 0, framelength = 0; + struct pbuf* p; + rt_uint32_t offset = 0, framelength = 0; - /* init p pointer */ - p = RT_NULL; + /* init p pointer */ + p = RT_NULL; - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)) - return p; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)) + return p; - if (((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && - ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) - { -#if STM32_ETH_DEBUG - int cnt = 0; + if (((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; - rt_kprintf("rx dump:\n"); -#endif + /* allocate buffer */ + p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM); + if (p != RT_NULL) + { + rt_uint8_t* ptr; + struct pbuf* q; + rt_size_t len; - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4; + for (q = p; q != RT_NULL; q= q->next) + { + ptr = q->payload; + len = q->len; - /* allocate buffer */ - p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM); - if (p != RT_NULL) - { - rt_uint8_t* ptr; - struct pbuf* q; - rt_size_t len; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + while (len) + { + *ptr = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset)); - for (q = p; q != RT_NULL; q= q->next) - { - ptr = q->payload; - len = q->len; + offset ++; + ptr ++; + len --; + } + } + } + } - /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ - while (len) - { - *ptr = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset)); -#if STM32_ETH_DEBUG - rt_kprintf("%02x ", *ptr); - if (++cnt % 16 == 0) rt_kprintf("\n"); -#endif + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; - offset ++; ptr ++; len --; - } - } + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } -#if STM32_ETH_DEBUG - rt_kprintf("\n"); -#endif - } - } + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } - /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ - DMARxDescToGet->Status = ETH_DMARxDesc_OWN; - - /* When Rx Buffer unavailable flag is set: clear it and resume reception */ - if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) - { - /* Clear RBUS ETHERNET DMA flag */ - ETH->DMASR = ETH_DMASR_RBUS; - /* Resume DMA reception */ - ETH->DMARPDR = 0; - } - - /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ - /* Chained Mode */ - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) - { - /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); - } - else /* Ring Mode */ - { - if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) - { - /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); - } - else - { - /* Selects the next DMA Rx descriptor list for next buffer to read */ - DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); - } - } - - return p; + return p; } static void RCC_Configuration(void) { - /* Enable ETHERNET clock */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | RCC_AHBPeriph_ETH_MAC_Tx | - RCC_AHBPeriph_ETH_MAC_Rx, ENABLE); + /* Enable ETHERNET clock */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | RCC_AHBPeriph_ETH_MAC_Tx | + RCC_AHBPeriph_ETH_MAC_Rx, ENABLE); /* Enable GPIOs clocks */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | @@ -3653,9 +3645,9 @@ static void GPIO_Configuration(void) void rt_hw_stm32_eth_init() { - RCC_Configuration(); - GPIO_Configuration(); - NVIC_Configuration(); + RCC_Configuration(); + GPIO_Configuration(); + NVIC_Configuration(); // OUI 00-80-E1 STMICROELECTRONICS stm32_eth_device.dev_addr[0] = 0x00; @@ -3666,22 +3658,22 @@ void rt_hw_stm32_eth_init() stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFFF7E8+8); stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFFF7E8+9); - stm32_eth_device.parent.parent.init = rt_stm32_eth_init; - stm32_eth_device.parent.parent.open = rt_stm32_eth_open; - stm32_eth_device.parent.parent.close = rt_stm32_eth_close; - stm32_eth_device.parent.parent.read = rt_stm32_eth_read; - stm32_eth_device.parent.parent.write = rt_stm32_eth_write; - stm32_eth_device.parent.parent.control = rt_stm32_eth_control; - stm32_eth_device.parent.parent.user_data = RT_NULL; + stm32_eth_device.parent.parent.init = rt_stm32_eth_init; + stm32_eth_device.parent.parent.open = rt_stm32_eth_open; + stm32_eth_device.parent.parent.close = rt_stm32_eth_close; + stm32_eth_device.parent.parent.read = rt_stm32_eth_read; + stm32_eth_device.parent.parent.write = rt_stm32_eth_write; + stm32_eth_device.parent.parent.control = rt_stm32_eth_control; + stm32_eth_device.parent.parent.user_data = RT_NULL; - stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; - stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; + stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; + stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; - /* init tx buffer free semaphore */ - rt_sem_init(&tx_buf_free, "tx_buf", ETH_TXBUFNB, RT_IPC_FLAG_FIFO); + /* init tx buffer free semaphore */ + rt_sem_init(&tx_buf_free, "tx_buf", ETH_TXBUFNB, RT_IPC_FLAG_FIFO); - /* register eth device */ - eth_device_init(&(stm32_eth_device.parent), "e0"); + /* register eth device */ + eth_device_init(&(stm32_eth_device.parent), "e0"); } #include diff --git a/bsp/stm32f107/stm32_eth.h b/bsp/stm32f107/stm32_eth.h index 349d01f01..e99ef49bd 100644 --- a/bsp/stm32f107/stm32_eth.h +++ b/bsp/stm32f107/stm32_eth.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32_eth.h * @author MCD Application Team - * @version V1.0.0 - * @date 06/19/2009 + * @version V1.1.0 + * @date 11/20/2009 * @brief This file contains all the functions prototypes for the Ethernet * firmware library. ****************************************************************************** @@ -17,7 +17,7 @@ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2009 STMicroelectronics

- */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32_ETH_H @@ -38,75 +38,183 @@ * @{ */ -/** +/** * @brief ETH MAC Init structure definition - */ + * @note The user should not configure all the ETH_InitTypeDef structure's fields. + * By calling the ETH_StructInit function the structure¡¯s fields are set to their default values. + * Only the parameters that will be set to a non-default value should be configured. + */ typedef struct { -/** - * @brief / * MAC - */ - uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation with the external PHY */ - uint32_t ETH_Watchdog; /*!< Enable/disable Watchdog timer */ - uint32_t ETH_Jabber; /*!< Enable/disable Jabber timer */ - uint32_t ETH_InterFrameGap; /*!< Selects minimum IFG between frames during transmission */ - uint32_t ETH_CarrierSense; /*!< Enable/disable Carrier Sense */ - uint32_t ETH_Speed; /*!< Indicates the Ethernet speed: 10/100 Mbps */ - uint32_t ETH_ReceiveOwn; /*!< Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */ - uint32_t ETH_LoopbackMode; /*!< Enable/disable internal MAC MII Loopback mode */ - uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ - uint32_t ETH_ChecksumOffload; /*!< Enable/disable the calculation of complement sum of all received Ethernet frame payloads */ - uint32_t ETH_RetryTransmission; /*!< Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */ - uint32_t ETH_AutomaticPadCRCStrip; /*!< Enable/disable Automatic MAC Pad/CRC Stripping */ - uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value */ - uint32_t ETH_DeferralCheck; /*!< Enable/disable deferral check function (Half-Duplex mode) */ - uint32_t ETH_ReceiveAll; /*!< Enable/disable all frames reception by the MAC (No fitering)*/ - uint32_t ETH_SourceAddrFilter; /*!< Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */ - uint32_t ETH_PassControlFrames; /*!< Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */ - uint32_t ETH_BroadcastFramesReception; /*!< Enable/disable reception of Broadcast Frames */ - uint32_t ETH_DestinationAddrFilter; /*!< Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */ - uint32_t ETH_PromiscuousMode; /*!< Enable/disable Promiscuous Mode */ - uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */ - uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */ - uint32_t ETH_HashTableHigh; /*!< This field contains the higher 32 bits of Hash table. */ - uint32_t ETH_HashTableLow; /*!< This field contains the lower 32 bits of Hash table. */ - uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame */ - uint32_t ETH_ZeroQuantaPause; /*!< Enable/disable the automatic generation of Zero-Quanta Pause Control frames */ - uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */ - uint32_t ETH_UnicastPauseFrameDetect; /*!< Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */ - uint32_t ETH_ReceiveFlowControl; /*!< Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */ - uint32_t ETH_TransmitFlowControl; /*!< Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */ - uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */ - uint32_t ETH_VLANTagIdentifier; /*!< VLAN tag identifier for receive frames */ +/** + * @brief / * MAC + */ + uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_watchdog */ + + uint32_t ETH_Jabber; /*!< Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref ETH_Speed */ + + uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ + + uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ + + uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the + transmit control frame */ + + uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ + +/** + * @brief / * DMA + */ + + uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t ETH_TxDMABurstLength; /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ -/** - * @brief / * DMA - */ - uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Enable/disable Dropping of TCP/IP Checksum Error Frames */ - uint32_t ETH_ReceiveStoreForward; /*!< Enable/disable Receive store and forward */ - uint32_t ETH_FlushReceivedFrame; /*!< Enable/disable flushing of received frames */ - uint32_t ETH_TransmitStoreForward; /*!< Enable/disable Transmit store and forward */ - uint32_t ETH_TransmitThresholdControl; /*!< Selects the Transmit Threshold Control */ - uint32_t ETH_ForwardErrorFrames; /*!< Enable/disable forward to DMA of all frames except runt error frames */ - uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */ - uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO */ - uint32_t ETH_SecondFrameOperate; /*!< Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */ - uint32_t ETH_AddressAlignedBeats; /*!< Enable/disable Address Aligned Beats */ - uint32_t ETH_FixedBurst; /*!< Enable/disable the AHB Master interface fixed burst transfers */ - uint32_t ETH_RxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Rx DMA transaction */ - uint32_t ETH_TxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Tx DMA transaction */ uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ - uint32_t ETH_DMAArbitration; /*!< Selects DMA Tx/Rx arbitration */ + + uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref ETH_DMA_Arbitration */ }ETH_InitTypeDef; /**--------------------------------------------------------------------------**/ -/** +/** * @brief DMA descriptors types - */ + */ /**--------------------------------------------------------------------------**/ -/** +/** * @brief ETH DMA Desciptors data structure definition - */ + */ typedef struct { uint32_t Status; /*!< Status */ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ @@ -120,33 +228,35 @@ typedef struct { /** @defgroup ETH_Exported_Constants * @{ - */ + */ /**--------------------------------------------------------------------------**/ -/** +/** * @brief ETH Frames defines - */ + */ /**--------------------------------------------------------------------------**/ -/** @defgroup ENET_Buffers_setting +/** @defgroup ENET_Buffers_setting * @{ - */ + */ #define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ #define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ #define ETH_CRC 4 /*!< Ethernet CRC */ -#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ +#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ #define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ #define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ #define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ -#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ /**--------------------------------------------------------------------------**/ -/** +/** * @brief Ethernet DMA descriptors registers bits definition - */ + */ /**--------------------------------------------------------------------------**/ -/* DMA Tx Desciptor -----------------------------------------------------------*/ -/**---------------------------------------------------------------------------------------------- +/** +@code + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | ----------------------------------------------------------------------------------------------- TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | @@ -154,11 +264,13 @@ typedef struct { TDES2 | Buffer1 Address [31:0] | ----------------------------------------------------------------------------------------------- TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | - ---------------------------------------------------------------------------------------------**/ + ----------------------------------------------------------------------------------------------- +@endcode +*/ -/** +/** * @brief Bit definition of TDES0 register: DMA Tx descriptor status register - */ + */ #define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ #define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ #define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */ @@ -167,10 +279,10 @@ typedef struct { #define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */ #define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ #define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ -#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ #define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ #define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ #define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ @@ -189,32 +301,35 @@ typedef struct { #define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ #define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ -/** +/** * @brief Bit definition of TDES1 register - */ + */ #define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ #define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ -/** +/** * @brief Bit definition of TDES2 register - */ + */ #define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ -/** +/** * @brief Bit definition of TDES3 register - */ + */ #define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ /** * @} - */ + */ -/** @defgroup DMA_Rx_descriptor +/** @defgroup DMA_Rx_descriptor * @{ */ -/**-------------------------------------------------------------------------------------------------------------------- +/** +@code + DMA Rx Desciptor + -------------------------------------------------------------------------------------------------------------------- RDES0 | OWN(31) | Status [30:0] | --------------------------------------------------------------------------------------------------------------------- RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | @@ -222,11 +337,13 @@ typedef struct { RDES2 | Buffer1 Address [31:0] | --------------------------------------------------------------------------------------------------------------------- RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | - -------------------------------------------------------------------------------------------------------------------**/ + --------------------------------------------------------------------------------------------------------------------- +@endcode +*/ -/** +/** * @brief Bit definition of RDES0 register: DMA Rx descriptor status register - */ + */ #define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ #define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ #define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ @@ -237,8 +354,8 @@ typedef struct { #define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ #define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ #define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ -#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ -#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ #define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ #define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ #define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ @@ -247,38 +364,38 @@ typedef struct { #define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */ #define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ -/** +/** * @brief Bit definition of RDES1 register - */ + */ #define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ #define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ #define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ #define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ #define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ -/** - * @brief Bit definition of RDES2 register - */ +/** + * @brief Bit definition of RDES2 register + */ #define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ -/** - * @brief Bit definition of RDES3 register - */ +/** + * @brief Bit definition of RDES3 register + */ #define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ /**--------------------------------------------------------------------------**/ -/** +/** * @brief Desciption of common PHY registers - */ + */ /**--------------------------------------------------------------------------**/ /** * @} */ -/** @defgroup PHY_Read_write_Timeouts +/** @defgroup PHY_Read_write_Timeouts * @{ - */ + */ #define PHY_READ_TO ((uint32_t)0x0004FFFF) #define PHY_WRITE_TO ((uint32_t)0x0004FFFF) @@ -286,27 +403,27 @@ typedef struct { * @} */ -/** @defgroup PHY_Reset_Delay +/** @defgroup PHY_Reset_Delay * @{ - */ -#define PHY_ResetDelay ((uint32_t)0x000FFFFF) + */ +#define PHY_ResetDelay ((uint32_t)0x000FFFFF) /** * @} */ -/** @defgroup PHY_Config_Delay +/** @defgroup PHY_Config_Delay * @{ - */ + */ #define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) /** * @} */ -/** @defgroup PHY_Register_address +/** @defgroup PHY_Register_address * @{ - */ + */ #define PHY_BCR 0 /*!< Tranceiver Basic Control Register */ #define PHY_BSR 1 /*!< Tranceiver Basic Status Register */ @@ -314,9 +431,9 @@ typedef struct { * @} */ -/** @defgroup PHY_basic_Control_register +/** @defgroup PHY_basic_Control_register * @{ - */ + */ #define PHY_Reset ((u16)0x8000) /*!< PHY Reset */ #define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */ #define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ @@ -332,9 +449,9 @@ typedef struct { * @} */ -/** @defgroup PHY_basic_status_register +/** @defgroup PHY_basic_status_register * @{ - */ + */ #define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */ #define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */ #define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */ @@ -343,51 +460,49 @@ typedef struct { * @} */ -/** @defgroup PHY_status_register +/** @defgroup PHY_status_register * @{ - */ -/* The PHY status register value change from a PHY to another so the user have + */ +/* The PHY status register value change from a PHY to another so the user have to update this value depending on the used external PHY */ -/** - * @brief For LAN8700 - */ +/** + * @brief For LAN8700 + */ //#define PHY_SR 31 /*!< Tranceiver Status Register */ -/** - * @brief For DP83848 - */ +/** + * @brief For DP83848 + */ #define PHY_SR 16 /*!< Tranceiver Status Register */ /* The Speed and Duplex mask values change from a PHY to another so the user have to update this value depending on the used external PHY */ -/** - * @brief For LAN8700 - */ +/** + * @brief For LAN8700 + */ //#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */ //#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */ -/** - * @brief For DP83848 - */ +/** + * @brief For DP83848 + */ #define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */ #define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */ #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) -#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \ - ((REG) == PHY_BSR) || \ - ((REG) == PHY_SR)) +#define IS_ETH_PHY_REG(REG) (REG <= 0x1F) /**--------------------------------------------------------------------------**/ -/** +/** * @brief MAC defines - */ + */ /**--------------------------------------------------------------------------**/ /** * @} - */ + */ -/** @defgroup ETH_AutoNegotiation +/** @defgroup ETH_AutoNegotiation * @{ - */ + */ #define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) #define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ @@ -397,9 +512,9 @@ typedef struct { * @} */ -/** @defgroup ETH_watchdog +/** @defgroup ETH_watchdog * @{ - */ + */ #define ETH_Watchdog_Enable ((uint32_t)0x00000000) #define ETH_Watchdog_Disable ((uint32_t)0x00800000) #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ @@ -409,9 +524,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Jabber +/** @defgroup ETH_Jabber * @{ - */ + */ #define ETH_Jabber_Enable ((uint32_t)0x00000000) #define ETH_Jabber_Disable ((uint32_t)0x00400000) #define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ @@ -421,9 +536,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Inter_Frame_Gap +/** @defgroup ETH_Inter_Frame_Gap * @{ - */ + */ #define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ #define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ #define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ @@ -445,9 +560,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Carrier_Sense +/** @defgroup ETH_Carrier_Sense * @{ - */ + */ #define ETH_CarrierSense_Enable ((uint32_t)0x00000000) #define ETH_CarrierSense_Disable ((uint32_t)0x00010000) #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ @@ -457,9 +572,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Speed +/** @defgroup ETH_Speed * @{ - */ + */ #define ETH_Speed_10M ((uint32_t)0x00000000) #define ETH_Speed_100M ((uint32_t)0x00004000) #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ @@ -469,9 +584,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Receive_Own +/** @defgroup ETH_Receive_Own * @{ - */ + */ #define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) #define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ @@ -481,9 +596,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Loop_back_Mode +/** @defgroup ETH_Loop_Back_Mode * @{ - */ + */ #define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) #define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ @@ -493,9 +608,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Duplex_mode +/** @defgroup ETH_Duplex_Mode * @{ - */ + */ #define ETH_Mode_FullDuplex ((uint32_t)0x00000800) #define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ @@ -505,9 +620,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Checksum_Offload +/** @defgroup ETH_Checksum_Offload * @{ - */ + */ #define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) #define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ @@ -517,9 +632,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Retry_Transmission +/** @defgroup ETH_Retry_Transmission * @{ - */ + */ #define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) #define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ @@ -529,9 +644,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Automatic_Pad_CRC_Strip +/** @defgroup ETH_Automatic_Pad_CRC_Strip * @{ - */ + */ #define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) #define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ @@ -541,9 +656,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Back-Off_limit +/** @defgroup ETH_Back_Off_Limit * @{ - */ + */ #define ETH_BackOffLimit_10 ((uint32_t)0x00000000) #define ETH_BackOffLimit_8 ((uint32_t)0x00000020) #define ETH_BackOffLimit_4 ((uint32_t)0x00000040) @@ -557,7 +672,7 @@ typedef struct { * @} */ -/** @defgroup ETH_Deferral_Check +/** @defgroup ETH_Deferral_Check * @{ */ #define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) @@ -569,9 +684,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Receive_All +/** @defgroup ETH_Receive_All * @{ - */ + */ #define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) #define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ @@ -581,9 +696,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Source_Addr_Filter +/** @defgroup ETH_Source_Addr_Filter * @{ - */ + */ #define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) #define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) #define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) @@ -595,12 +710,12 @@ typedef struct { * @} */ -/** @defgroup ETH_Pass_Control_Frames +/** @defgroup ETH_Pass_Control_Frames * @{ - */ + */ #define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ #define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ -#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ ((PASS) == ETH_PassControlFrames_ForwardAll) || \ ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) @@ -609,9 +724,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Broadcast_Frames_Reception +/** @defgroup ETH_Broadcast_Frames_Reception * @{ - */ + */ #define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) #define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ @@ -621,9 +736,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Destination_Addr_Filter +/** @defgroup ETH_Destination_Addr_Filter * @{ - */ + */ #define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) #define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ @@ -633,9 +748,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Promiscuous_Mode +/** @defgroup ETH_Promiscuous_Mode * @{ - */ + */ #define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) #define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ @@ -645,9 +760,9 @@ typedef struct { * @} */ -/** @defgroup ETH_multicast_frames_filter +/** @defgroup ETH_Multicast_Frames_Filter * @{ - */ + */ #define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) #define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) #define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) @@ -656,15 +771,15 @@ typedef struct { ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ ((FILTER) == ETH_MulticastFramesFilter_None)) - + /** * @} */ -/** @defgroup ETH_unicast_frames_filter +/** @defgroup ETH_Unicast_Frames_Filter * @{ - */ + */ #define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) #define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) #define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) @@ -676,18 +791,18 @@ typedef struct { * @} */ -/** @defgroup ETH_Pause_Time +/** @defgroup ETH_Pause_Time * @{ - */ + */ #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) /** * @} */ -/** @defgroup ETH_Zero_Quanta_Pause +/** @defgroup ETH_Zero_Quanta_Pause * @{ - */ + */ #define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) #define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ @@ -696,9 +811,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Pause_Low_Threshold +/** @defgroup ETH_Pause_Low_Threshold * @{ - */ + */ #define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ #define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ #define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ @@ -712,9 +827,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Unicast_Pause_Frame_Detect +/** @defgroup ETH_Unicast_Pause_Frame_Detect * @{ - */ + */ #define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) #define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ @@ -724,9 +839,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Receive_Flow_Control +/** @defgroup ETH_Receive_Flow_Control * @{ - */ + */ #define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) #define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ @@ -736,9 +851,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Transmit_Flow_Control +/** @defgroup ETH_Transmit_Flow_Control * @{ - */ + */ #define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) #define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ @@ -748,9 +863,9 @@ typedef struct { * @} */ -/** @defgroup ETH_VLAN_Tag_Comparison +/** @defgroup ETH_VLAN_Tag_Comparison * @{ - */ + */ #define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) #define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ @@ -761,9 +876,9 @@ typedef struct { * @} */ -/** @defgroup ETH_MAC_Flags +/** @defgroup ETH_MAC_Flags * @{ - */ + */ #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ @@ -776,9 +891,9 @@ typedef struct { * @} */ -/** @defgroup ETH_MAC_Interrupts +/** @defgroup ETH_MAC_Interrupts * @{ - */ + */ #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ @@ -792,9 +907,9 @@ typedef struct { * @} */ -/** @defgroup ETH_MAC_addresses +/** @defgroup ETH_MAC_addresses * @{ - */ + */ #define ETH_MAC_Address0 ((uint32_t)0x00000000) #define ETH_MAC_Address1 ((uint32_t)0x00000008) #define ETH_MAC_Address2 ((uint32_t)0x00000010) @@ -810,9 +925,9 @@ typedef struct { * @} */ -/** @defgroup ETH_MAC_addresses_filter:_SA_DA_filed_of_received_frames +/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames * @{ - */ + */ #define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) #define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ @@ -821,9 +936,9 @@ typedef struct { * @} */ -/** @defgroup ETH_MAC_addresses_filter:_Mask_bytes +/** @defgroup ETH_MAC_addresses_filter_Mask_bytes * @{ - */ + */ #define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ #define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ #define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ @@ -838,9 +953,9 @@ typedef struct { ((MASK) == ETH_MAC_AddressMask_Byte1)) /**--------------------------------------------------------------------------**/ -/** +/** * @brief Ethernet DMA Desciptors defines - */ + */ /**--------------------------------------------------------------------------**/ /** * @} @@ -848,7 +963,7 @@ typedef struct { /** @defgroup ETH_DMA_Tx_descriptor_flags * @{ - */ + */ #define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ ((FLAG) == ETH_DMATxDesc_IC) || \ ((FLAG) == ETH_DMATxDesc_LS) || \ @@ -878,9 +993,9 @@ typedef struct { * @} */ -/** @defgroup ETH_DMA_Tx_descriptor_segment +/** @defgroup ETH_DMA_Tx_descriptor_segment * @{ - */ + */ #define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */ #define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */ #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ @@ -892,7 +1007,7 @@ typedef struct { /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control * @{ - */ + */ #define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */ #define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ #define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ @@ -901,9 +1016,9 @@ typedef struct { ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) -/** +/** * @brief ETH DMA Tx Desciptor buffer size - */ + */ #define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) /** @@ -912,7 +1027,7 @@ typedef struct { /** @defgroup ETH_DMA_Rx_descriptor_flags * @{ - */ + */ #define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ ((FLAG) == ETH_DMARxDesc_AFM) || \ ((FLAG) == ETH_DMARxDesc_ES) || \ @@ -936,26 +1051,26 @@ typedef struct { * @} */ -/** @defgroup ETH_DMA_Rx_descriptor_buffers_ +/** @defgroup ETH_DMA_Rx_descriptor_buffers_ * @{ - */ + */ #define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ #define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ ((BUFFER) == ETH_DMARxDesc_Buffer2)) /**--------------------------------------------------------------------------**/ -/** +/** * @brief Ethernet DMA defines - */ + */ /**--------------------------------------------------------------------------**/ /** * @} */ -/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame * @{ - */ + */ #define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) #define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ @@ -964,9 +1079,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Receive_Store_Forward +/** @defgroup ETH_Receive_Store_Forward * @{ - */ + */ #define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) #define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ @@ -975,9 +1090,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Flush_Received_Frame +/** @defgroup ETH_Flush_Received_Frame * @{ - */ + */ #define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) #define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ @@ -986,9 +1101,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Transmit_Store_Forward +/** @defgroup ETH_Transmit_Store_Forward * @{ - */ + */ #define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) #define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ @@ -997,9 +1112,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Transmit_Threshold_Control +/** @defgroup ETH_Transmit_Threshold_Control * @{ - */ + */ #define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ #define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ #define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ @@ -1020,9 +1135,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Forward_Error_Frames +/** @defgroup ETH_Forward_Error_Frames * @{ - */ + */ #define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) #define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ @@ -1031,11 +1146,11 @@ typedef struct { * @} */ -/** @defgroup ETH_Forward_Undersized_Good_Frames +/** @defgroup ETH_Forward_Undersized_Good_Frames * @{ - */ + */ #define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) -#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) @@ -1043,9 +1158,9 @@ typedef struct { * @} */ -/** @defgroup ETH_Receive_Threshold_Control +/** @defgroup ETH_Receive_Threshold_Control * @{ - */ + */ #define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ #define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ #define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ @@ -1058,11 +1173,11 @@ typedef struct { * @} */ -/** @defgroup ETH_Second_Frame_Operate +/** @defgroup ETH_Second_Frame_Operate * @{ - */ + */ #define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) -#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ ((CMD) == ETH_SecondFrameOperate_Disable)) @@ -1070,11 +1185,11 @@ typedef struct { * @} */ -/** @defgroup ETH_Address_Aligned_Beats +/** @defgroup ETH_Address_Aligned_Beats * @{ - */ + */ #define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) -#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ ((CMD) == ETH_AddressAlignedBeats_Disable)) @@ -1082,11 +1197,11 @@ typedef struct { * @} */ -/** @defgroup ETH_Fixed_Burst +/** @defgroup ETH_Fixed_Burst * @{ - */ + */ #define ETH_FixedBurst_Enable ((uint32_t)0x00010000) -#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ ((CMD) == ETH_FixedBurst_Disable)) @@ -1094,15 +1209,15 @@ typedef struct { * @} */ -/** @defgroup ETH_Rx_DMA_Burst_Length +/** @defgroup ETH_Rx_DMA_Burst_Length * @{ - */ + */ #define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ #define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ #define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ #define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ #define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ #define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ #define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ #define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ @@ -1121,20 +1236,20 @@ typedef struct { ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) - + /** * @} */ -/** @defgroup ETH_Tx_DMA_Burst_Length +/** @defgroup ETH_Tx_DMA_Burst_Length * @{ - */ + */ #define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ #define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ #define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ #define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ #define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ #define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ #define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ #define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ @@ -1153,18 +1268,18 @@ typedef struct { ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) -/** - * @brief ETH DMA Desciptor SkipLength - */ +/** + * @brief ETH DMA Desciptor SkipLength + */ #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) /** * @} */ -/** @defgroup ETH_DMA_Arbitration +/** @defgroup ETH_DMA_Arbitration * @{ - */ + */ #define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) #define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) #define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) @@ -1179,9 +1294,9 @@ typedef struct { * @} */ -/** @defgroup ETH_DMA_Flags +/** @defgroup ETH_DMA_Flags * @{ - */ + */ #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ @@ -1204,7 +1319,7 @@ typedef struct { #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ -#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ @@ -1220,9 +1335,9 @@ typedef struct { * @} */ -/** @defgroup ETH_DMA_Interrupts +/** @defgroup ETH_DMA_Interrupts * @{ - */ + */ #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ @@ -1257,9 +1372,9 @@ typedef struct { * @} */ -/** @defgroup ETH_DMA_transmit_process_state_ +/** @defgroup ETH_DMA_transmit_process_state_ * @{ - */ + */ #define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ #define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ #define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */ @@ -1269,12 +1384,12 @@ typedef struct { /** * @} - */ + */ -/** @defgroup ETH_DMA_receive_process_state_ +/** @defgroup ETH_DMA_receive_process_state_ * @{ - */ + */ #define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ #define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ #define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */ @@ -1286,26 +1401,26 @@ typedef struct { * @} */ -/** @defgroup ETH_DMA_overflow_ +/** @defgroup ETH_DMA_overflow_ * @{ - */ + */ #define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ #define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) /**--------------------------------------------------------------------------**/ -/** +/** * @brief Ethernet PMT defines - */ + */ /**--------------------------------------------------------------------------**/ /** * @} */ -/** @defgroup ETH_PMT_Flags +/** @defgroup ETH_PMT_Flags * @{ - */ + */ #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */ #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ @@ -1313,17 +1428,17 @@ typedef struct { ((FLAG) == ETH_PMT_FLAG_MPR)) /**--------------------------------------------------------------------------**/ -/** +/** * @brief Ethernet MMC defines - */ + */ /**--------------------------------------------------------------------------**/ /** * @} */ -/** @defgroup ETH_MMC_Tx_Interrupts +/** @defgroup ETH_MMC_Tx_Interrupts * @{ - */ + */ #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ @@ -1332,7 +1447,7 @@ typedef struct { * @} */ -/** @defgroup ETH_MMC_Rx_Interrupts +/** @defgroup ETH_MMC_Rx_Interrupts * @{ */ #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ @@ -1347,43 +1462,43 @@ typedef struct { * @} */ -/** @defgroup ETH_MMC_Registers +/** @defgroup ETH_MMC_Registers * @{ - */ + */ #define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */ #define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */ #define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */ #define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */ -#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ -#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ #define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */ #define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */ #define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */ #define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ -/** - * @brief ETH MMC registers - */ +/** + * @brief ETH MMC registers + */ #define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ - ((REG) == ETH_MMCRGUFCR)) + ((REG) == ETH_MMCRGUFCR)) /**--------------------------------------------------------------------------**/ -/** +/** * @brief Ethernet PTP defines - */ + */ /**--------------------------------------------------------------------------**/ /** * @} */ -/** @defgroup ETH_PTP_time_update_method +/** @defgroup ETH_PTP_time_update_method * @{ - */ + */ #define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */ #define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */ #define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ @@ -1391,12 +1506,12 @@ typedef struct { /** * @} - */ + */ -/** @defgroup ETH_PTP_Flags +/** @defgroup ETH_PTP_Flags * @{ - */ + */ #define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ #define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ #define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ @@ -1405,32 +1520,32 @@ typedef struct { ((FLAG) == ETH_PTP_FLAG_TSITE) || \ ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ ((FLAG) == ETH_PTP_FLAG_TSSTI)) -/** - * @brief ETH PTP subsecond increment - */ +/** + * @brief ETH PTP subsecond increment + */ #define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) /** * @} - */ + */ -/** @defgroup ETH_PTP_time_sign +/** @defgroup ETH_PTP_time_sign * @{ - */ + */ #define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */ #define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */ #define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ ((SIGN) == ETH_PTP_NegativeTime)) -/** - * @brief ETH PTP time stamp low update - */ +/** + * @brief ETH PTP time stamp low update + */ #define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) -/** - * @brief ETH PTP registers - */ +/** + * @brief ETH PTP registers + */ #define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */ #define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */ #define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */ @@ -1444,11 +1559,11 @@ typedef struct { ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ - ((REG) == ETH_PTPTTLR)) + ((REG) == ETH_PTPTTLR)) /** * @} - */ + */ /** @@ -1457,14 +1572,14 @@ typedef struct { /** @defgroup ETH_Exported_Macros * @{ - */ + */ /** * @} */ /** @defgroup ETH_Exported_Functions * @{ - */ + */ void ETH_DeInit(void); uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress); void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); @@ -1476,22 +1591,22 @@ uint32_t ETH_HandleRxPkt(u8 *ppkt); uint32_t ETH_GetRxPktSize(void); void ETH_DropRxPkt(void); -/** - * @brief PHY - */ +/** + * @brief PHY + */ u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg); uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue); uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState); -/** - * @brief MAC - */ +/** + * @brief MAC + */ void ETH_MACTransmissionCmd(FunctionalState NewState); void ETH_MACReceptionCmd(FunctionalState NewState); FlagStatus ETH_GetFlowControlBusyStatus(void); -void ETH_InitiatePauseControlFrame(void); -void ETH_BackPressureActivationCmd(FunctionalState NewState); -FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr); @@ -1500,9 +1615,9 @@ void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); -/** - * @brief DMA Tx/Rx descriptors - */ +/** + * @brief DMA Tx/Rx descriptors + */ void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount); void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount); FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); @@ -1527,9 +1642,9 @@ void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState Ne void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); -/** +/** * @brief DMA - */ + */ FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); @@ -1551,9 +1666,9 @@ uint32_t ETH_GetCurrentRxBufferAddress(void); void ETH_ResumeDMATransmission(void); void ETH_ResumeDMAReception(void); -/** - * @brief PMT - */ +/** + * @brief PMT + */ void ETH_ResetWakeUpFrameFilterRegisterPointer(void); void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); @@ -1562,9 +1677,9 @@ void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); void ETH_MagicPacketDetectionCmd(FunctionalState NewState); void ETH_PowerDownCmd(FunctionalState NewState); -/** - * @brief MMC - */ +/** + * @brief MMC + */ void ETH_MMCCounterFreezeCmd(FunctionalState NewState); void ETH_MMCResetOnReadCmd(FunctionalState NewState); void ETH_MMCCounterRolloverCmd(FunctionalState NewState); @@ -1573,9 +1688,9 @@ void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); -/** - * @brief PTP - */ +/** + * @brief PTP + */ uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab); uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab); void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount); @@ -1602,11 +1717,11 @@ void rt_hw_stm32_eth_init(void); #endif /* __STM32_ETH_H */ /** * @} - */ + */ /** * @} - */ + */ /******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/