320 lines
9.9 KiB
C
320 lines
9.9 KiB
C
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/*
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_FLEXRAM_H_
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#define _FSL_FLEXRAM_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup flexram
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* @{
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*/
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/******************************************************************************
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* Definitions.
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*****************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief Driver version 2.0.1. */
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#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
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/*@}*/
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/*! @brief flexram write read sel */
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enum _flexram_wr_rd_sel
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{
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kFLEXRAM_Read = 0U, /*!< read */
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kFLEXRAM_Write = 1U, /*!< write */
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};
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/*! @brief Interrupt status flag mask */
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enum _flexram_interrupt_status
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{
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kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */
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kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */
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kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */
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kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< ocram maigc address match */
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kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, /*!< dtcm maigc address match */
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kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, /*!< itcm maigc address match */
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kFLEXRAM_InterruptStatusAll = 0x3FU, /*!< all the interrupt status mask */
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};
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/*! @brief FLEXRAM TCM access mode
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* Fast access mode expected to be finished in 1-cycle
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* Wait access mode expected to be finished in 2-cycle
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* Wait access mode is a feature of the flexram and it should be used when
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* the cpu clock too fast to finish tcm access in 1-cycle.
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* Normally, fast mode is the default mode, the efficiency of the tcm access will better.
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*/
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typedef enum _flexram_tcm_access_mode
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{
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kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */
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kFLEXRAM_TCMAccessWaitMode = 1U, /*!< wait access mode */
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} flexram_tcm_access_mode_t;
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/*! @brief FLEXRAM bank type */
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enum _flexram_bank_type
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{
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kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */
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kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */
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kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */
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kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */
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};
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/*! @brief FLEXRAM tcm support size */
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enum _flexram_tcm_size
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{
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kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size 32KB */
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kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size 64KB */
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kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size 128KB */
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kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size 256KB */
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kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size 512KB */
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};
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/*! @brief FLEXRAM bank allocate source */
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typedef enum _flexram_bank_allocate_src
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{
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kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */
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kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */
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} flexram_bank_allocate_src_t;
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/*! @brief FLEXRAM allocate ocram, itcm, dtcm size */
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typedef struct _flexram_allocate_ram
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{
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const uint8_t ocramBankNum; /*!< ocram banknumber which the SOC support */
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const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */
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const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */
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} flexram_allocate_ram_t;
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/*!
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* @name Initialization and deinitialization
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* @{
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*/
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/*!
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* @brief FLEXRAM module initialization function.
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*
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* @param base FLEXRAM base address.
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*/
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void FLEXRAM_Init(FLEXRAM_Type *base);
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/*!
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* @brief Deinitializes the FLEXRAM.
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*
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*/
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void FLEXRAN_Deinit(FLEXRAM_Type *base);
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/* @} */
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/*!
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* @name Status
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* @{
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*/
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/*!
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* @brief FLEXRAM module get interrupt status.
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*
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* @param base FLEXRAM base address.
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*/
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static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base)
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{
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return base->INT_STATUS & kFLEXRAM_InterruptStatusAll;
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}
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/*!
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* @brief FLEXRAM module clear interrupt status.
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*
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* @param base FLEXRAM base address.
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* @param status status to clear.
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*/
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static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status)
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{
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base->INT_STATUS |= status;
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}
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/*!
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* @brief FLEXRAM module enable interrupt status.
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*
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* @param base FLEXRAM base address.
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* @param status status to enable.
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*/
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static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
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{
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base->INT_STAT_EN |= status;
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}
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/*!
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* @brief FLEXRAM module disable interrupt status.
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*
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* @param base FLEXRAM base address.
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* @param status status to disable.
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*/
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static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
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{
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base->INT_STAT_EN &= ~status;
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}
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/* @} */
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/*!
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* @name Interrupts
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* @{
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*/
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/*!
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* @brief FLEXRAM module enable interrupt.
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*
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* @param base FLEXRAM base address.
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* @param status status interrupt to enable.
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*/
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static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
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{
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base->INT_SIG_EN |= status;
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}
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/*!
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* @brief FLEXRAM module disable interrupt.
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*
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* @param base FLEXRAM base address.
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* @param status status interrupt to disable.
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*/
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static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
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{
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base->INT_SIG_EN &= ~status;
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}
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/* @} */
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/*!
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* @name functional
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* @{
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*/
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/*!
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* @brief FLEXRAM module set TCM read access mode
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*
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* @param base FLEXRAM base address.
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* @param mode access mode.
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*/
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static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
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{
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base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK;
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base->TCM_CTRL |= mode;
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}
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/*!
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* @brief FLEXRAM module set TCM write access mode
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*
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* @param base FLEXRAM base address.
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* @param mode access mode.
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*/
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static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
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{
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base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK;
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base->TCM_CTRL |= mode;
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}
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/*!
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* @brief FLEXRAM module force ram clock on
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*
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* @param base FLEXRAM base address.
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* @param enable enable or disable clock force on.
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*/
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static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable)
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{
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if (enable)
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{
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base->TCM_CTRL |= FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
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}
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else
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{
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base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
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}
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}
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/*!
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* @brief FLEXRAM OCRAM magic addr configuration
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* When read/write access hit magic address, it will generate interrupt
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* @param magicAddr magic address.
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* @param rwsel read write select, 0 read access , 1 write access
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*/
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static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
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{
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base->OCRAM_MAGIC_ADDR =
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FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) | FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(magicAddr >> 3U);
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}
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/*!
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* @brief FLEXRAM DTCM magic addr configuration
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* When read/write access hit magic address, it will generate interrupt
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* @param magicAddr magic address.
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* @param rwsel read write select, 0 read access , 1 write access
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*/
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static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
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{
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base->DTCM_MAGIC_ADDR =
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FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) | FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(magicAddr >> 3U);
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}
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/*!
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* @brief FLEXRAM ITCM magic addr configuration
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* When read/write access hit magic address, it will generate interrupt
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* @param magicAddr magic address.
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* @param rwsel read write select, 0 read access , 1 write access
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*/
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static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
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{
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base->ITCM_MAGIC_ADDR =
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FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) | FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(magicAddr >> 3U);
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}
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/*!
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* @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM
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* This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate
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* is needed.
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* @param config allocate configuration.
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* @retval kStatus_InvalidArgument the argument is invalid
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* kStatus_Success allocate success
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*/
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status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config);
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/*!
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* @brief FLEXRAM set allocate on-chip ram source
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* @param src bank config source select value.
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*/
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static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src)
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{
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IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK;
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IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src);
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}
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/*! @}*/
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#endif
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