rtt-f030/components/net/freemodbus-v1.6.0/port/user_mb_app.h

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#ifndef USER_APP
#define USER_APP
/* ----------------------- Modbus includes ----------------------------------*/
#include "mb.h"
#include "mb_m.h"
#include "mbconfig.h"
#include "mbframe.h"
#include "mbutils.h"
/* -----------------------Slave Defines -------------------------------------*/
#define S_DISCRETE_INPUT_START 1
#define S_DISCRETE_INPUT_NDISCRETES 16
#define S_COIL_START 1
#define S_COIL_NCOILS 64
#define S_REG_INPUT_START 1
#define S_REG_INPUT_NREGS 100
#define S_REG_HOLDING_START 1
#define S_REG_HOLDING_NREGS 100
//<2F>ӻ<EFBFBD>ģʽ<C4A3><CABD><EFBFBD>ڱ<EFBFBD><DAB1>ּĴ<D6BC><C4B4><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Ӧ<EFBFBD>Ĺ<EFBFBD><C4B9>ܶ<EFBFBD><DCB6><EFBFBD>
#define S_HD_RESERVE 0 //<2F><><EFBFBD><EFBFBD>
#define S_HD_CPU_USAGE_MAJOR 1 //<2F><>ǰCPU<50><55><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5><EFBFBD><EFBFBD><EFBFBD>λ
#define S_HD_CPU_USAGE_MINOR 2 //<2F><>ǰCPU<50><55><EFBFBD><EFBFBD><EFBFBD>ʵ<EFBFBD>С<EFBFBD><D0A1>λ
//<2F>ӻ<EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Ӧ<EFBFBD>Ĺ<EFBFBD><C4B9>ܶ<EFBFBD><DCB6><EFBFBD>
#define S_IN_RESERVE 0 //<2F><><EFBFBD><EFBFBD>
//<2F>ӻ<EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȧ<EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Ӧ<EFBFBD>Ĺ<EFBFBD><C4B9>ܶ<EFBFBD><DCB6><EFBFBD>
#define S_CO_RESERVE 2 //<2F><><EFBFBD><EFBFBD>
//<2F>ӻ<EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɢ<EFBFBD><C9A2><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Ӧ<EFBFBD>Ĺ<EFBFBD><C4B9>ܶ<EFBFBD><DCB6><EFBFBD>
#define S_DI_RESERVE 1 //<2F><><EFBFBD><EFBFBD>
/* -----------------------Master Defines -------------------------------------*/
#define M_DISCRETE_INPUT_START 1
#define M_DISCRETE_INPUT_NDISCRETES 16
#define M_COIL_START 1
#define M_COIL_NCOILS 64
#define M_REG_INPUT_START 1
#define M_REG_INPUT_NREGS 100
#define M_REG_HOLDING_START 1
#define M_REG_HOLDING_NREGS 100
//<2F><><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD>ڱ<EFBFBD><DAB1>ּĴ<D6BC><C4B4><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Ӧ<EFBFBD>Ĺ<EFBFBD><C4B9>ܶ<EFBFBD><DCB6><EFBFBD>
#define M_HD_RESERVE 0 //<2F><><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Ӧ<EFBFBD>Ĺ<EFBFBD><C4B9>ܶ<EFBFBD><DCB6><EFBFBD>
#define M_IN_RESERVE 0 //<2F><><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȧ<EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Ӧ<EFBFBD>Ĺ<EFBFBD><C4B9>ܶ<EFBFBD><DCB6><EFBFBD>
#define M_CO_RESERVE 2 //<2F><><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ɢ<EFBFBD><C9A2><EFBFBD><EFBFBD><EFBFBD>У<EFBFBD><D0A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7>Ӧ<EFBFBD>Ĺ<EFBFBD><C4B9>ܶ<EFBFBD><DCB6><EFBFBD>
#define M_DI_RESERVE 1 //<2F><><EFBFBD><EFBFBD>
#endif