305 lines
8.5 KiB
C
305 lines
8.5 KiB
C
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/*
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* serial.c UART driver
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*
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* COPYRIGHT (C) 2013, Shanghai Real-Thread Technology Co., Ltd
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*
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2013-03-30 Bernard the first verion
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*/
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#include <rthw.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "gic.h"
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#include "cp15.h"
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#include "uart_hw.h"
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#define Zynq7000_UART_INT_DISABLE(UART) \
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(UART->IER &= ~(UART_IXR_RXOVR | UART_IXR_RXFULL))
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#define Zynq7000_UART_INT_ENABLE(UART) \
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(UART->IER |= (UART_IXR_RXOVR | UART_IXR_RXFULL))
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#define Zynq7000_UART_SENDCHAR(UART, ch) \
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do { \
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while ((UART->SR) & UART_SR_TXFULL); \
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UART->FIFO = ch; \
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} while(0)
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#define Zynq7000_UART_GETCHAR(UART, ch) \
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do { \
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if (UART->ISR & UART_SR_RXOVR) \
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{ \
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ch = UART->FIFO & 0xff; \
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UART->ISR = (UART_IXR_RXOVR | UART_IXR_RXFULL); \
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} \
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} while(0)
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static void UartEnable(UART_Registers* uart)
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{
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uint32_t tmp = uart->CR;
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tmp &= ~UART_CR_EN_DIS_MASK;
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tmp |= (UART_CR_TX_EN | UART_CR_RX_EN);
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uart->CR = tmp;
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}
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static void UartDisable(UART_Registers* uart)
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{
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uint32_t tmp = uart->CR;
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tmp &= ~UART_CR_EN_DIS_MASK;
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tmp |= (UART_CR_TX_DIS | UART_CR_RX_DIS);
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uart->CR = tmp;
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}
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static void UartResetTXRXLogic(UART_Registers* uart)
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{
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uart->CR |= 0x03;
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while (uart->CR & 0x03)
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;
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}
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/* PULLUP | LVCMOS18 | Fast CMOS | UART */
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#define RX_MIO_PIN_MODE ((0x1UL << 12) | (0x1UL << 9) | (0x01UL << 8) | (0x7UL << 5))
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#define TX_MIO_PIN_MODE ( (0x1UL << 9) | (0x01UL << 8) | (0x7UL << 5))
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struct hw_uart_device
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{
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UART_Registers * uart;
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rt_uint32_t irqno;
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/* MIO pin mode address */
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rt_uint32_t *rxmio;
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rt_uint32_t *txmio;
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};
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/* RT-Thread UART interface */
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static void rt_hw_uart_isr(int irqno, void *param)
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{
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struct rt_serial_device *serial = (struct rt_serial_device *)param;
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rt_hw_serial_isr(serial);
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}
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static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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uint32_t mr;
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struct hw_uart_device *pdev = serial->parent.user_data;
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UART_Registers *uart = pdev->uart;
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/* unlock SLCR */
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__REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UNLOCK) = 0xDF0D;
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/* no loopback */
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__REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_MIO_LOOPBACK) &= ~(1 << 1);
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if (uart == (void*)Zynq7000_UART0_BASE)
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{
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/* enable the coresponding AMBA Peripheral Clock */
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__REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_APER_CLK_CTRL) |= 1 << 20;
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/* enable uart clock. Divider 0x14 gives 50MHZ ref clock on IO PLL input. */
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__REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_CLK_CTRL) |= (0x14 << 8) | 0x01;
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/* deassert the AMBA clock and software reset */
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__REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_RST_CTRL) &= ~((0x01 << 2)|(0x01 << 0));
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}
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else if (uart == (void*)Zynq7000_UART1_BASE)
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{
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__REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_APER_CLK_CTRL) |= 1 << 21;
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__REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_CLK_CTRL) |= (0x14 << 8) | 0x02;
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__REG32(Zynq7000_SLCR_BASE+Zynq7000_SLCR_UART_RST_CTRL) &= ~((0x01 << 3)|(0x01 << 1));
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}
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else
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return -RT_ERROR;
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UartDisable(uart);
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UartResetTXRXLogic(uart);
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UartEnable(uart);
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mr = uart->MR & ~(UART_MR_CHARLEN_MASK |
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UART_MR_STOPMODE_MASK |
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UART_MR_PARITY_MASK);
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if (cfg->stop_bits == STOP_BITS_2)
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mr |= UART_MR_STOPMODE_2_BIT;
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else if (cfg->stop_bits == STOP_BITS_1)
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mr |= UART_MR_STOPMODE_1_BIT;
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else
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return -RT_ERROR;
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if (cfg->parity == PARITY_EVEN)
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mr |= UART_MR_PARITY_EVEN;
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else if (cfg->parity == PARITY_ODD)
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mr |= UART_MR_PARITY_ODD;
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else if (cfg->parity == PARITY_NONE)
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mr |= UART_MR_PARITY_NONE;
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else
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return -1;
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if (cfg->data_bits == DATA_BITS_8)
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mr |= UART_MR_CHARLEN_8_BIT;
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else if (cfg->data_bits == DATA_BITS_7)
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mr |= UART_MR_CHARLEN_7_BIT;
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else if (cfg->data_bits == DATA_BITS_6)
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mr |= UART_MR_CHARLEN_6_BIT;
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else
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return -RT_ERROR;
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uart->MR = mr;
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uart->TXWM = 8;
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uart->RXWM = 1;
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if (cfg->baud_rate == BAUD_RATE_115200)
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{
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uart->BAUDGEN = UART_BAUDGEN_115200;
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uart->BAUDDIV = UART_BAUDDIV_115200;
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}
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else
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{
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rt_kprintf("baudrate %d not implemented yet\n", cfg->baud_rate);
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}
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/* disable all interrupts */
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uart->IDR = UART_IXR_MASK;
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/* configure the pin */
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*(pdev->txmio) = TX_MIO_PIN_MODE;
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*(pdev->rxmio) = RX_MIO_PIN_MODE;
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return RT_EOK;
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}
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static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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struct hw_uart_device *pdev;
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RT_ASSERT(serial != RT_NULL);
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pdev = serial->parent.user_data;
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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/* disable rx irq */
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Zynq7000_UART_INT_DISABLE(pdev->uart);
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break;
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case RT_DEVICE_CTRL_SET_INT:
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/* enable rx irq */
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Zynq7000_UART_INT_ENABLE(pdev->uart);
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rt_hw_interrupt_install(pdev->irqno, rt_hw_uart_isr, serial, "uart");
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/* set the interrupt to this cpu */
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arm_gic_set_cpu(0, pdev->irqno, 1 << rt_cpu_get_smp_id());
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rt_hw_interrupt_umask(pdev->irqno);
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break;
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}
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return RT_EOK;
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}
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static int uart_putc(struct rt_serial_device *serial, char c)
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{
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struct hw_uart_device *dev;
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RT_ASSERT(serial != RT_NULL);
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dev = (struct hw_uart_device *)serial->parent.user_data;
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Zynq7000_UART_SENDCHAR(dev->uart, c);
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return 1;
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}
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static int uart_getc(struct rt_serial_device *serial)
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{
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int ch;
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struct hw_uart_device *dev;
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RT_ASSERT(serial != RT_NULL);
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dev = (struct hw_uart_device *)serial->parent.user_data;
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ch = -1;
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Zynq7000_UART_GETCHAR(dev->uart, ch);
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return ch;
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}
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static const struct rt_uart_ops _uart_ops =
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{
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uart_configure,
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uart_control,
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uart_putc,
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uart_getc,
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};
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/* UART device driver structure */
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static struct hw_uart_device _uart_device0 =
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{
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.uart = (UART_Registers*)Zynq7000_UART0_BASE,
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.irqno = IRQ_Zynq7000_UART0,
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.rxmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x0728), /* MIO10 */
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.txmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x072C), /* MIO11 */
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};
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static struct hw_uart_device _uart_device1 =
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{
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.uart = (UART_Registers*)Zynq7000_UART1_BASE,
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.irqno = IRQ_Zynq7000_UART1,
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.rxmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x07C4), /* MIO49 */
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.txmio = (rt_uint32_t*)(Zynq7000_SLCR_BASE+0x07C0), /* MIO48 */
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};
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static struct serial_ringbuffer _uart_int_rx0;
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static struct rt_serial_device _serial0;
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static struct serial_ringbuffer _uart_int_rx1;
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static struct rt_serial_device _serial1;
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int rt_hw_uart_init(void)
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{
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struct serial_configure config;
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config.baud_rate = BAUD_RATE_115200;
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config.bit_order = BIT_ORDER_LSB;
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config.data_bits = DATA_BITS_8;
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config.parity = PARITY_NONE;
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config.stop_bits = STOP_BITS_1;
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config.invert = NRZ_NORMAL;
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_serial0.ops = &_uart_ops;
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_serial0.int_rx = &_uart_int_rx0;
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_serial0.config = config;
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_serial1.ops = &_uart_ops;
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_serial1.int_rx = &_uart_int_rx1;
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_serial1.config = config;
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/* register uart device */
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rt_hw_serial_register(&_serial0, "uart0",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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&_uart_device0);
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rt_hw_serial_register(&_serial1, "uart1",
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RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
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&_uart_device1);
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return 0;
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}
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INIT_BOARD_EXPORT(rt_hw_uart_init);
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