2017-07-18 11:15:10 +08:00
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// <20><>о1c<31><63><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>
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#ifndef __OPENLOONGSON_LS1C_REGS_H
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#define __OPENLOONGSON_LS1C_REGS_H
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// ʱ<><CAB1><EFBFBD><EFBFBD><EFBFBD>ؼĴ<D8BC><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
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#define LS1C_START_FREQ (0xbfe78030)
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#define LS1C_CLK_DIV_PARAM (0xbfe78034)
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// gpio<69><6F><EFBFBD>ؼĴ<D8BC><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ
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#define LS1C_GPIO_CFG0 (0xbfd010c0)
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#define LS1C_GPIO_EN0 (0xbfd010d0)
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#define LS1C_GPIO_IN0 (0xbfd010e0)
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#define LS1C_GPIO_OUT0 (0xbfd010f0)
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#define LS1C_GPIO_CFG1 (0xbfd010c4)
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#define LS1C_GPIO_EN1 (0xbfd010d4)
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#define LS1C_GPIO_IN1 (0xbfd010e4)
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#define LS1C_GPIO_OUT1 (0xbfd010f4)
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#define LS1C_GPIO_CFG2 (0xbfd010c8)
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#define LS1C_GPIO_EN2 (0xbfd010d8)
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#define LS1C_GPIO_IN2 (0xbfd010e8)
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#define LS1C_GPIO_OUT2 (0xbfd010f8)
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#define LS1C_GPIO_CFG3 (0xbfd010cc)
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#define LS1C_GPIO_EN3 (0xbfd010dc)
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#define LS1C_GPIO_IN3 (0xbfd010ec)
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#define LS1C_GPIO_OUT3 (0xbfd010fc)
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ؼĴ<D8BC><C4B4><EFBFBD>
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#define LS1C_CBUS_FIRST0 (0xbfd011c0)
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#define LS1C_CBUS_SECOND0 (0xbfd011d0)
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#define LS1C_CBUS_THIRD0 (0xbfd011e0)
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#define LS1C_CBUS_FOURTH0 (0xbfd011f0)
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#define LS1C_CBUS_FIFTH0 (0xbfd01200)
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#define LS1C_CBUS_FIRST1 (0xbfd011c4)
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#define LS1C_CBUS_SECOND1 (0xbfd011d4)
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#define LS1C_CBUS_THIRD1 (0xbfd011e4)
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#define LS1C_CBUS_FOURTH1 (0xbfd011f4)
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#define LS1C_CBUS_FIFTH1 (0xbfd01204)
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#define LS1C_CBUS_FIRST2 (0xbfd011c8)
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#define LS1C_CBUS_SECOND2 (0xbfd011d8)
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#define LS1C_CBUS_THIRD2 (0xbfd011e8)
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#define LS1C_CBUS_FOURTH2 (0xbfd011f8)
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#define LS1C_CBUS_FIFTH2 (0xbfd01208)
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#define LS1C_CBUS_FIRST3 (0xbfd011cc)
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#define LS1C_CBUS_SECOND3 (0xbfd011dc)
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#define LS1C_CBUS_THIRD3 (0xbfd011ec)
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#define LS1C_CBUS_FOURTH3 (0xbfd011fc)
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#define LS1C_CBUS_FIFTH3 (0xbfd0120c)
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// PWM<57>Ĵ<EFBFBD><C4B4><EFBFBD>ƫ<EFBFBD><C6AB>
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#define LS1C_PWM_CNTR (0x0)
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#define LS1C_PWM_HRC (0x4)
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#define LS1C_PWM_LRC (0x8)
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#define LS1C_PWM_CTRL (0xC)
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// PWM<57><4D><EFBFBD><EFBFBD>ַ
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#define LS1C_REG_BASE_PWM0 (0xbfe5c000)
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#define LS1C_REG_BASE_PWM1 (0xbfe5c010)
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#define LS1C_REG_BASE_PWM2 (0xbfe5c020)
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#define LS1C_REG_BASE_PWM3 (0xbfe5c030)
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2017-07-20 17:35:03 +08:00
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// <20>ж<EFBFBD><D0B6><EFBFBD><EFBFBD>üĴ<C3BC><C4B4><EFBFBD>
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#define LS1C_INT0_SR (0xbfd01040)
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#define LS1C_INT0_EN (0xbfd01044)
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#define LS1C_INT0_SET (0xbfd01048)
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#define LS1C_INT0_CLR (0xbfd0104c)
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#define LS1C_INT0_POL (0xbfd01050)
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#define LS1C_INT0_EDGE (0xbfd01054)
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#define LS1c_INT1_SR (0xbfd01058)
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#define LS1C_INT1_EN (0xbfd0105c)
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#define LS1C_INT1_SET (0xbfd01060)
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#define LS1C_INT1_CLR (0xbfd01064)
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#define LS1C_INT1_POL (0xbfd01068)
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#define LS1C_INT1_EDGE (0xbfd0106c)
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#define LS1C_INT2_SR (0xbfd01070)
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#define LS1C_INT2_EN (0xbfd01074)
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#define LS1C_INT2_SET (0xbfd01078)
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#define LS1C_INT2_CLR (0xbfd0107c)
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#define LS1C_INT2_POL (0xbfd01080)
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#define LS1C_INT2_EDGE (0xbfd01084)
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#define LS1C_INT3_SR (0xbfd01088)
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#define LS1C_INT3_EN (0xbfd0108c)
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#define LS1C_INT3_SET (0xbfd01090)
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#define LS1C_INT3_CLR (0xbfd01094)
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#define LS1C_INT3_POL (0xbfd01098)
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#define LS1C_INT3_EDGE (0xbfd0109c)
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#define LS1C_INT4_SR (0xbfd010a0)
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#define LS1C_INT4_EN (0xbfd010a4)
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#define LS1C_INT4_SET (0xbfd010a8)
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#define LS1C_INT4_CLR (0xbfd010ac)
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#define LS1C_INT4_POL (0xbfd010b0)
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#define LS1C_INT4_EDGE (0xbfd010b4)
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2017-07-18 11:15:10 +08:00
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2017-09-06 12:11:46 +08:00
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// I2C<32>Ĵ<EFBFBD><C4B4><EFBFBD>
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#define LS1C_I2C0_BASE (0xbfe58000)
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#define LS1C_I2C1_BASE (0xbfe68000)
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#define LS1C_I2C2_BASE (0xbfe70000)
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2017-07-18 11:15:10 +08:00
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#endif
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