99 lines
3.4 KiB
C
99 lines
3.4 KiB
C
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/*
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* @brief LPC5410X CPU multi-core support driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CPUCTRL_5410X_H_
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#define __CPUCTRL_5410X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CPUCTRL_5410X CHIP: LPC5410X CPU multi-core support driver
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* @ingroup CHIP_5410X_DRIVERS
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* This driver helps with determine which MCU core the software is running,
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* whether the MCU core is in master or slave mode, and provides functions
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* for master and slave core control.<br>
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*
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* The functions for the driver are provided as part of the
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* @ref POWER_LIBRARY_5410X library. For more information on using the
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* LPC5410x LPCopen package with multi-core, see @ref CHIP_5410X_MULTICORE<br>.
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* @{
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*/
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/**
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* @brief Determine which MCU this code is running on
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* @return true if executing on the CM4, or false if executing on the CM0+
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*/
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STATIC INLINE bool Chip_CPU_IsM4Core(void) {
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/* M4 core is designated by values 0xC24 on bits 15..4 */
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if (((SCB->CPUID >> 4) & 0xFFF) == 0xC24) {
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return true;
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}
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return false;
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}
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/**
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* @brief Determine if this core is a slave or master
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* @return true if this MCU is operating as the master, or false if operating as a slave
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*/
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bool Chip_CPU_IsMasterCore(void);
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/**
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* @brief Setup M0+ boot and reset M0+ core
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* @param coentry : Pointer to boot entry point for M0+ core
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* @param costackptr : Pointer to where stack should be located for M0+ core
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* @return Nothing
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* @note Will setup boot stack and entry point, enable M0+ clock and then
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* reset M0+ core.
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*/
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void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr);
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/**
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* @brief Setup M4 boot and reset M4 core
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* @param coentry : Pointer to boot entry point for M4 core
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* @param costackptr : Pointer to where stack should be located for M4 core
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* @return Nothing
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* @note Will setup boot stack and entry point, enable M4 clock and then
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* reset M0+ core.
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*/
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void Chip_CPU_CM4Boot(uint32_t *coentry, uint32_t *costackptr);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CPUCTRL_5410X_H_ */
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