380 lines
15 KiB
C
380 lines
15 KiB
C
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/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief High-level library abstracting features such as oscillators/pll/dfll
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* configuration, clock configuration, System-sensible parameters
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* configuration, buses clocks configuration, sleep mode, reset.
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*
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*
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* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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* - Supported devices: All AVR32 devices.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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*****************************************************************************/
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/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an Atmel
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* AVR product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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*
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*/
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#ifndef _POWER_CLOCKS_LIB_H_
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#define _POWER_CLOCKS_LIB_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <avr32/io.h>
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#include "compiler.h"
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#ifndef AVR32_PM_VERSION_RESETVALUE
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// Support for UC3A, UC3A3, UC3B parts.
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#include "pm.h"
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#else
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//! Device-specific data
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#if UC3L
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#include "pm_uc3l.h"
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#include "scif_uc3l.h"
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#include "flashcdw.h"
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#elif UC3C
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#include "pm_uc3c.h"
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#include "scif_uc3c.h"
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#include "flashc.h"
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#endif
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#endif
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/*! \name Clocks Management
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*/
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//! @{
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//! The different oscillators
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typedef enum
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{
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PCL_OSC0 = 0,
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PCL_OSC1 = 1
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} pcl_osc_t;
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//! The different DFLLs
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typedef enum
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{
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PCL_DFLL0 = 0,
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PCL_DFLL1 = 1
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} pcl_dfll_t;
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//! Possible Main Clock Sources
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typedef enum
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{
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PCL_MC_RCSYS, // Default main clock source, supported by all (aka Slow Clock)
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PCL_MC_OSC0, // Supported by all
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PCL_MC_OSC1, // Supported by UC3C only
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PCL_MC_OSC0_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC0 as reference)
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PCL_MC_OSC1_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC1 as reference)
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PCL_MC_OSC0_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC0 as reference)
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PCL_MC_OSC1_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC1 as reference)
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PCL_MC_DFLL0, // Supported by UC3L
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PCL_MC_DFLL1, // Not supported yet
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PCL_MC_RC120M, // Supported by UC3L, UC3C
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PCL_MC_RC8M, // Supported by UC3C
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PCL_MC_CRIPOSC // Supported by UC3C
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} pcl_mainclk_t;
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//! Input and output parameters to configure clocks with pcl_configure_clocks().
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// NOTE: regarding the frequency settings, always abide by the datasheet rules and min & max supported frequencies.
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#ifndef AVR32_PM_VERSION_RESETVALUE
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// Support for UC3A, UC3A3, UC3B parts.
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#define pcl_freq_param_t pm_freq_param_t // See pm.h
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#else
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// Support for UC3C, UC3L parts.
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typedef struct
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{
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//! Main clock source selection (input argument).
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pcl_mainclk_t main_clk_src;
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//! Target CPU frequency (input/output argument).
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unsigned long cpu_f;
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//! Target PBA frequency (input/output argument).
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unsigned long pba_f;
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//! Target PBB frequency (input/output argument).
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unsigned long pbb_f;
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//! Target PBC frequency (input/output argument).
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unsigned long pbc_f;
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//! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).
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unsigned long osc0_f;
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//! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
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unsigned long osc0_startup;
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//! DFLL target frequency (input/output argument) (NOTE: the bigger, the most stable the frequency)
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unsigned long dfll_f;
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//! Other parameters that might be necessary depending on the device (implementation-dependent).
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// For the UC3L DFLL setup, this parameter should be pointing to a structure of
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// type (scif_gclk_opt_t *).
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void *pextra_params;
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} pcl_freq_param_t;
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#endif
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//! Define "not supported" for the lib.
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#define PCL_NOT_SUPPORTED (-10000)
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/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
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*
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* This function needs some parameters stored in a pcl_freq_param_t structure:
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* - main_clk_src is the id of the main clock source to use,
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* - cpu_f and pba_f and pbb_f are the wanted frequencies,
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* - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
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* - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).
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* - dfll_f is the target DFLL frequency to set-up if main_clk_src is the dfll.
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*
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* The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
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*
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* \note: since it is dynamically computing the appropriate field values of the
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* configuration registers from the parameters structure, this function is not
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* optimal in terms of code size. For a code size optimal solution, it is better
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* to create a new function from pcl_configure_clocks() and modify it to use
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* preprocessor computation from pre-defined target frequencies.
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*
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* \param param pointer on the configuration structure.
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*
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* \retval 0 Success.
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* \retval <0 The configuration cannot be performed.
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*/
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extern long int pcl_configure_clocks(pcl_freq_param_t *param);
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/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.
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*
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* This function needs some parameters stored in a pcl_freq_param_t structure:
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* - cpu_f and pba_f and pbb_f are the wanted frequencies
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*
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* Supported main clock sources: PCL_MC_RCSYS
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*
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* Supported synchronous clocks frequencies:
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* 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
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*
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* \note: by default, this implementation doesn't perform thorough checks on the
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* input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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*
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* \note: since it is dynamically computing the appropriate field values of the
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* configuration registers from the parameters structure, this function is not
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* optimal in terms of code size. For a code size optimal solution, it is better
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* to create a new function from pcl_configure_clocks_rcsys() and modify it to use
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* preprocessor computation from pre-defined target frequencies.
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*
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* \param param pointer on the configuration structure.
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*
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* \retval 0 Success.
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* \retval <0 The configuration cannot be performed.
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*/
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extern long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param);
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/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.
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*
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* This function needs some parameters stored in a pcl_freq_param_t structure:
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* - cpu_f and pba_f and pbb_f are the wanted frequencies
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*
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* Supported main clock sources: PCL_MC_RC120M
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*
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* Supported synchronous clocks frequencies:
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* 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
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*
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* \note: by default, this implementation doesn't perform thorough checks on the
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* input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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*
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* \note: since it is dynamically computing the appropriate field values of the
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* configuration registers from the parameters structure, this function is not
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* optimal in terms of code size. For a code size optimal solution, it is better
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* to create a new function from pcl_configure_clocks_rc120m() and modify it to
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* use preprocessor computation from pre-defined target frequencies.
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*
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* \param param pointer on the configuration structure.
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*
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* \retval 0 Success.
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* \retval <0 The configuration cannot be performed.
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*/
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extern long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param);
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/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock
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*
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* This function needs some parameters stored in a pcl_freq_param_t structure:
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* - cpu_f and pba_f and pbb_f are the wanted frequencies,
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* - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
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* - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).
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*
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* Supported main clock sources: PCL_MC_OSC0
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*
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* Supported synchronous clocks frequencies:
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* (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
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* 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
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*
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* \note: by default, this implementation doesn't perform thorough checks on the
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* input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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*
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* \note: since it is dynamically computing the appropriate field values of the
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* configuration registers from the parameters structure, this function is not
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* optimal in terms of code size. For a code size optimal solution, it is better
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* to create a new function from pcl_configure_clocks_osc0() and modify it to use
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* preprocessor computation from pre-defined target frequencies.
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*
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* \param param pointer on the configuration structure.
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*
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* \retval 0 Success.
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* \retval <0 The configuration cannot be performed.
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*/
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extern long int pcl_configure_clocks_osc0(pcl_freq_param_t *param);
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/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock
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*
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* This function needs some parameters stored in a pcl_freq_param_t structure:
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* - cpu_f and pba_f and pbb_f are the wanted frequencies,
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* - dfll_f is the target DFLL frequency to set-up
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*
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* \note: when the DFLL0 is to be used as main source clock for the synchronous clocks,
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* the target frequency of the DFLL should be chosen to be as high as possible
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* within the specification range (for stability reasons); the target cpu and pbx
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* frequencies will then be reached by appropriate division ratio.
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*
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* Supported main clock sources: PCL_MC_DFLL0
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*
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* Supported synchronous clocks frequencies:
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* (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
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* 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
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*
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* \note: by default, this implementation doesn't perform thorough checks on the
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* input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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*
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* \note: since it is dynamically computing the appropriate field values of the
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* configuration registers from the parameters structure, this function is not
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* optimal in terms of code size. For a code size optimal solution, it is better
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* to create a new function from pcl_configure_clocks_dfll0() and modify it to
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* use preprocessor computation from pre-defined target frequencies.
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*
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* \param param pointer on the configuration structure.
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*
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* \retval 0 Success.
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* \retval <0 The configuration cannot be performed.
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*/
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extern long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param);
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/*! \brief Switch the main clock source to Osc0 configured in crystal mode
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*
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* \param osc The oscillator to enable and switch to.
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* \param fcrystal Oscillator external crystal frequency (Hz)
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* \param startup Oscillator startup time.
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*
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* \return Status.
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* \retval 0 Success.
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* \retval <0 An error occured.
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*/
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extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup);
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/*! \brief Enable the clock of a module.
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*
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* \param module The module to clock (use one of the defines in the part-specific
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* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
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* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks"
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* or look in the module section).
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*
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* \return Status.
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* \retval 0 Success.
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* \retval <0 An error occured.
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*/
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#ifndef AVR32_PM_VERSION_RESETVALUE
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// Implementation for UC3A, UC3A3, UC3B parts.
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#define pcl_enable_module(module) pm_enable_module(&AVR32_PM, module)
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#else
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// Implementation for UC3C, UC3L parts.
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#define pcl_enable_module(module) pm_enable_module(module)
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#endif
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/*! \brief Disable the clock of a module.
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*
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* \param module The module to shut down (use one of the defines in the part-specific
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* header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
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* clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks"
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* or look in the module section).
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*
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* \return Status.
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||
|
|
* \retval 0 Success.
|
||
|
|
* \retval <0 An error occured.
|
||
|
|
*/
|
||
|
|
#ifndef AVR32_PM_VERSION_RESETVALUE
|
||
|
|
// Implementation for UC3A, UC3A3, UC3B parts.
|
||
|
|
#define pcl_disable_module(module) pm_disable_module(&AVR32_PM, module)
|
||
|
|
#else
|
||
|
|
// Implementation for UC3C, UC3L parts.
|
||
|
|
#define pcl_disable_module(module) pm_disable_module(module)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/*! \brief Configure the USB Clock
|
||
|
|
*
|
||
|
|
*
|
||
|
|
* \return Status.
|
||
|
|
* \retval 0 Success.
|
||
|
|
* \retval <0 An error occured.
|
||
|
|
*/
|
||
|
|
extern long int pcl_configure_usb_clock(void);
|
||
|
|
|
||
|
|
//! @}
|
||
|
|
|
||
|
|
/*! \name Power Management
|
||
|
|
*/
|
||
|
|
//! @{
|
||
|
|
/*!
|
||
|
|
* \brief Read the content of the GPLP registers
|
||
|
|
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
|
||
|
|
*
|
||
|
|
* \return The content of the chosen GPLP register.
|
||
|
|
*/
|
||
|
|
extern unsigned long pcl_read_gplp(unsigned long gplp);
|
||
|
|
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* \brief Write into the GPLP registers
|
||
|
|
* \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
|
||
|
|
* \param value Value to write
|
||
|
|
*/
|
||
|
|
extern void pcl_write_gplp(unsigned long gplp, unsigned long value);
|
||
|
|
|
||
|
|
//! @}
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif // _POWER_CLOCKS_LIB_H_
|