170 lines
4.1 KiB
ArmAsm
170 lines
4.1 KiB
ArmAsm
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;/*
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; * File : context.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-17 Bernard first version
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; */
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;/**
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; * @addtogroup STM32
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; */
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;/*@{*/
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NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
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NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
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NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
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SECTION .text:CODE(2)
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THUMB
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REQUIRE8
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PRESERVE8
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IMPORT rt_thread_switch_interrput_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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EXPORT rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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MRS r0, PRIMASK
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CPSID I
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BX LR
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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EXPORT rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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MSR PRIMASK, r0
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BX LR
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;/*
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; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; * r0 --> from
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; * r1 --> to
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; */
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EXPORT rt_hw_context_switch
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rt_hw_context_switch:
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LDR r2, =rt_interrupt_from_thread
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STR r0, [r2]
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LDR r2, =rt_interrupt_to_thread
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STR r1, [r2]
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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CPSIE I ; enable interrupts at processor level
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BX LR
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; r0 --> swith from thread stack
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; r1 --> swith to thread stack
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; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
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EXPORT rt_hw_pend_sv
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rt_hw_pend_sv:
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LDR r0, =rt_interrupt_from_thread
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LDR r1, [r0]
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CBZ r1, swtich_to_thread ; skip register save at the first time
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MRS r1, psp ; get from thread stack pointer
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STMFD r1!, {r4 - r11} ; push r4 - r11 register
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LDR r0, [r0]
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STR r1, [r0] ; update from thread stack pointer
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swtich_to_thread
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LDR r1, =rt_interrupt_to_thread
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LDR r1, [r1]
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LDR r1, [r1] ; load thread stack pointer
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LDMFD r1!, {r4 - r11} ; pop r4 - r11 register
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MSR psp, r1 ; update stack pointer
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ORR lr, lr, #0x04
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BX lr
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;/*
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * r0 --> to
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; */
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EXPORT rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LDR r1, =rt_interrupt_to_thread
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STR r0, [r1]
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; set from thread to 0
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LDR r1, =rt_interrupt_from_thread
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MOV r0, #0x0
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STR r0, [r1]
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; set the PendSV exception priority
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LDR r0, =NVIC_SYSPRI2
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LDR r1, =NVIC_PENDSV_PRI
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STR r1, [r0]
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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CPSIE I ; enable interrupts at processor level
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; never reach here!
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;/*
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; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)
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; * {
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; * if (rt_thread_switch_interrput_flag == 1)
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; * {
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; * rt_interrupt_to_thread = to;
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; * }
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; * else
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; * {
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; * rt_thread_switch_interrput_flag = 1;
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; * rt_interrupt_from_thread = from;
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; * rt_interrupt_to_thread = to;
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; * }
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; * }
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; */
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EXPORT rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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LDR r2, =rt_thread_switch_interrput_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 ; set rt_thread_switch_interrput_flag to 1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch:
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LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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EXPORT rt_hw_interrupt_thread_switch
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rt_hw_interrupt_thread_switch:
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LDR r0, =rt_thread_switch_interrput_flag
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LDR r1, [r0]
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CBZ r1, _no_switch
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; clear rt_thread_switch_interrput_flag to 0
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MOV r1, #0x00
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STR r1, [r0]
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; trigger context switch
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LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch)
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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_no_switch:
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BX lr
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END
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