466 lines
12 KiB
C
466 lines
12 KiB
C
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/** @file system.h
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* @brief System Driver Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* .
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* which are relevant for the System driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __SYS_SYSTEM_H__
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#define __SYS_SYSTEM_H__
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#include "reg_system.h"
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#include "reg_flash.h"
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#include "reg_tcram.h"
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#include "gio.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* System General Definitions */
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/** @enum systemInterrupt
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* @brief Alias names for clock sources
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*
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* This enumeration is used to provide alias names for the clock sources:
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* - IRQ
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* - FIQ
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*/
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enum systemInterrupt
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{
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SYS_IRQ, /**< Alias for IRQ interrupt */
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SYS_FIQ /**< Alias for FIQ interrupt */
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};
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/** @enum systemClockSource
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* @brief Alias names for clock sources
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*
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* This enumeration is used to provide alias names for the clock sources:
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* - Oscillator
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* - Pll1
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* - External1
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* - Low Power Oscillator Low
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* - Low Power Oscillator High
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* - PLL2
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* - External2
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* - Synchronous VCLK1
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*/
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enum systemClockSource
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{
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SYS_OSC = 0U, /**< Alias for oscillator clock Source */
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SYS_PLL1 = 1U, /**< Alias for Pll1 clock Source */
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SYS_EXTERNAL1 = 3U, /**< Alias for external clock Source */
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SYS_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */
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SYS_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */
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SYS_PLL2 = 6U, /**< Alias for Pll2 clock Source */
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SYS_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */
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SYS_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */
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};
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#define SYS_DOZE_MODE 0x000F3F02U
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#define SYS_SNOOZE_MODE 0x000F3F03U
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#define SYS_SLEEP_MODE 0x000FFFFFU
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#define LPO_TRIM_VALUE (((*(volatile uint32 *)0xF00801B4U) & 0xFFFF0000U)>>16U)
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#define SYS_EXCEPTION (*(volatile uint32 *)0xFFFFFFE4U)
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#define POWERON_RESET 0x8000U
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#define OSC_FAILURE_RESET 0x4000U
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#define WATCHDOG_RESET 0x2000U
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#define ICEPICK_RESET 0x2000U
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#define CPU_RESET 0x0020U
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#define SW_RESET 0x0010U
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#define WATCHDOG_STATUS (*(volatile uint32 *)0xFFFFFC98U)
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#define DEVICE_ID_REV (*(volatile uint32 *)0xFFFFFFF0U)
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/** @def OSC_FREQ
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* @brief Oscillator clock source exported from HALCoGen GUI
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*
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* Oscillator clock source exported from HALCoGen GUI
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*/
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#define OSC_FREQ 16.0F
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/** @def PLL1_FREQ
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* @brief PLL 1 clock source exported from HALCoGen GUI
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*
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* PLL 1 clock source exported from HALCoGen GUI
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*/
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#define PLL1_FREQ 200.00F
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/** @def LPO_LF_FREQ
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* @brief LPO Low Freq Oscillator source exported from HALCoGen GUI
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*
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* LPO Low Freq Oscillator source exported from HALCoGen GUI
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*/
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#define LPO_LF_FREQ 0.080F
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/** @def LPO_HF_FREQ
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* @brief LPO High Freq Oscillator source exported from HALCoGen GUI
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*
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* LPO High Freq Oscillator source exported from HALCoGen GUI
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*/
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#define LPO_HF_FREQ 10.000F
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/** @def PLL1_FREQ
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* @brief PLL 2 clock source exported from HALCoGen GUI
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*
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* PLL 2 clock source exported from HALCoGen GUI
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*/
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#define PLL2_FREQ 200.00F
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/** @def GCLK_FREQ
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* @brief GCLK domain frequency exported from HALCoGen GUI
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*
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* GCLK domain frequency exported from HALCoGen GUI
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*/
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#define GCLK_FREQ 200.000F
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/** @def HCLK_FREQ
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* @brief HCLK domain frequency exported from HALCoGen GUI
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*
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* HCLK domain frequency exported from HALCoGen GUI
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*/
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#define HCLK_FREQ 200.000F
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/** @def RTI_FREQ
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* @brief RTI Clock frequency exported from HALCoGen GUI
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*
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* RTI Clock frequency exported from HALCoGen GUI
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*/
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#define RTI_FREQ 100.000F
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/** @def AVCLK1_FREQ
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* @brief AVCLK1 Domain frequency exported from HALCoGen GUI
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*
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* AVCLK Domain frequency exported from HALCoGen GUI
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*/
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#define AVCLK1_FREQ 100.000F
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/** @def AVCLK2_FREQ
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* @brief AVCLK2 Domain frequency exported from HALCoGen GUI
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*
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* AVCLK2 Domain frequency exported from HALCoGen GUI
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*/
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#define AVCLK2_FREQ 100.0F
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/** @def AVCLK3_FREQ
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* @brief AVCLK3 Domain frequency exported from HALCoGen GUI
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*
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* AVCLK3 Domain frequency exported from HALCoGen GUI
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*/
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#define AVCLK3_FREQ 100.000F
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/** @def VCLK1_FREQ
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* @brief VCLK1 Domain frequency exported from HALCoGen GUI
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*
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* VCLK1 Domain frequency exported from HALCoGen GUI
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*/
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#define VCLK1_FREQ 100.000F
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/** @def VCLK2_FREQ
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* @brief VCLK2 Domain frequency exported from HALCoGen GUI
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*
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* VCLK2 Domain frequency exported from HALCoGen GUI
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*/
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#define VCLK2_FREQ 100.000F
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/** @def SYS_PRE1
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* @brief Alias name for RTI1CLK PRE clock source
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*
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* This is an alias name for the RTI1CLK pre clock source.
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* This can be either:
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* - Oscillator
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* - Pll
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* - 32 kHz Oscillator
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* - External
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* - Low Power Oscillator Low
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* - Low Power Oscillator High
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* - Flexray Pll
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*/
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/*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
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#define SYS_PRE1 SYS_PLL1
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/** @def SYS_PRE2
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* @brief Alias name for RTI2CLK pre clock source
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*
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* This is an alias name for the RTI2CLK pre clock source.
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* This can be either:
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* - Oscillator
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* - Pll
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* - 32 kHz Oscillator
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* - External
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* - Low Power Oscillator Low
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* - Low Power Oscillator High
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* - Flexray Pll
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*/
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/*SAFETYMCUSW 79 S MR:19.4 <REVIEWED> "Macro filled using GUI parameter cannot be avoided" */
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#define SYS_PRE2 SYS_PLL1
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/* Configuration registers */
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typedef struct system_config_reg
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{
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uint32 CONFIG_SYSPC1;
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uint32 CONFIG_SYSPC2;
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uint32 CONFIG_SYSPC7;
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uint32 CONFIG_SYSPC8;
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uint32 CONFIG_SYSPC9;
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uint32 CONFIG_CSDIS;
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uint32 CONFIG_CDDIS;
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uint32 CONFIG_GHVSRC;
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uint32 CONFIG_VCLKASRC;
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uint32 CONFIG_RCLKSRC;
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uint32 CONFIG_MSTGCR;
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uint32 CONFIG_MINITGCR;
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uint32 CONFIG_MSINENA;
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uint32 CONFIG_PLLCTL1;
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uint32 CONFIG_PLLCTL2;
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uint32 CONFIG_UERFLAG;
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uint32 CONFIG_LPOMONCTL;
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uint32 CONFIG_CLKTEST;
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uint32 CONFIG_DFTCTRLREG1;
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uint32 CONFIG_DFTCTRLREG2;
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uint32 CONFIG_GPREG1;
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uint32 CONFIG_RAMGCR;
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uint32 CONFIG_BMMCR1;
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uint32 CONFIG_MMUGCR;
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uint32 CONFIG_CLKCNTL;
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uint32 CONFIG_ECPCNTL;
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uint32 CONFIG_DEVCR1;
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uint32 CONFIG_SYSECR;
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uint32 CONFIG_PLLCTL3;
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uint32 CONFIG_STCCLKDIV;
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uint32 CONFIG_CLK2CNTL;
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uint32 CONFIG_VCLKACON1;
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uint32 CONFIG_CLKSLIP;
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uint32 CONFIG_EFC_CTLEN;
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} system_config_reg_t;
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/* Configuration registers initial value */
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#define SYS_SYSPC1_CONFIGVALUE 0U
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#define SYS_SYSPC2_CONFIGVALUE 1U
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#define SYS_SYSPC7_CONFIGVALUE 0U
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#define SYS_SYSPC8_CONFIGVALUE 0U
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#define SYS_SYSPC9_CONFIGVALUE 1U
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#define SYS_CSDIS_CONFIGVALUE 0x00000000U\
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| 0x00000000U \
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| 0x00000008U \
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| 0x00000080U \
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| 0x00000000U \
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| 0x00000000U \
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| 0x00000000U\
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| (1U << 2U)
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#define SYS_CDDIS_CONFIGVALUE (FALSE << 4U )\
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|(TRUE << 5U )\
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|(FALSE << 8U )\
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|(FALSE << 10U)\
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|(FALSE << 11U)
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#define SYS_GHVSRC_CONFIGVALUE (SYS_PLL1 << 24U) \
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| (SYS_PLL1 << 16U) \
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| SYS_PLL1
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#define SYS_VCLKASRC_CONFIGVALUE (SYS_VCLK << 8U)\
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| SYS_VCLK
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#define SYS_RCLKSRC_CONFIGVALUE (1U << 24U)\
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| (SYS_VCLK << 16U)\
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| (1U << 8U)\
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| SYS_VCLK
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#define SYS_MSTGCR_CONFIGVALUE 0x00000105U
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#define SYS_MINITGCR_CONFIGVALUE 0x5U
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#define SYS_MSINENA_CONFIGVALUE 0U
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#define SYS_PLLCTL1_CONFIGVALUE_1 0x00000000U \
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| 0x20000000U \
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| ((0x1FU)<< 24U) \
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| 0x00000000U \
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| ((6U - 1U)<< 16U)\
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| ((150U - 1U)<< 8U)
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#define SYS_PLLCTL1_CONFIGVALUE_2 ( (SYS_PLLCTL1_CONFIGVALUE_1) & 0xE0FFFFFFU)|((1U - 1U)<< 24U)
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#define SYS_PLLCTL2_CONFIGVALUE 0x00000000U\
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| (255U << 22U)\
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| (7U << 12U)\
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| ((2U - 1U)<< 9U)\
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| 61U
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#define SYS_UERFLAG_CONFIGVALUE 0U
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#define SYS_LPOMONCTL_CONFIGVALUE_1 (1U << 24U) | LPO_TRIM_VALUE
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#define SYS_LPOMONCTL_CONFIGVALUE_2 (1U << 24U) | (16U << 8U) | 8U
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#define SYS_CLKTEST_CONFIGVALUE 0x000A0000U
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#define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U
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#define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U
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#define SYS_GPREG1_CONFIGVALUE 0x0005FFFFU
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#define SYS_RAMGCR_CONFIGVALUE 0x00050000U
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#define SYS_BMMCR1_CONFIGVALUE 0xAU
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#define SYS_MMUGCR_CONFIGVALUE 0U
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#define SYS_CLKCNTL_CONFIGVALUE (1U << 8U) \
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| (1U << 16U) \
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| (1U << 24U)
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#define SYS_ECPCNTL_CONFIGVALUE (0U << 24U)\
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| (0U << 23U)\
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| ((8U - 1U) & 0xFFFFU)
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#define SYS_DEVCR1_CONFIGVALUE 0xAU
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#define SYS_SYSECR_CONFIGVALUE 0x00004000U
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#define SYS2_PLLCTL3_CONFIGVALUE_1 ((2U - 1U) << 29U)\
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| ((0x1FU)<< 24U) \
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| ((6U - 1U)<< 16U) \
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| ((150U - 1U) << 8U)
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#define SYS2_PLLCTL3_CONFIGVALUE_2 ((SYS2_PLLCTL3_CONFIGVALUE_1) & 0xE0FFFFFFU)|((1U - 1U)<< 24U)
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#define SYS2_STCCLKDIV_CONFIGVALUE 0U
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#define SYS2_CLK2CNTL_CONFIGVALUE (1U) \
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| (1U << 8U)
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#define SYS2_VCLKACON1_CONFIGVALUE (1U << 24U) \
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| (1U << 20U) \
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| (SYS_VCLK << 16U)\
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| (1U << 8U)\
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| (1U << 4U) \
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| SYS_VCLK
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#define SYS2_CLKSLIP_CONFIGVALUE 0x5U
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#define SYS2_EFC_CTLEN_CONFIGVALUE 0x5U
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void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t type);
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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/* FlashW General Definitions */
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/** @enum flashWPowerModes
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* @brief Alias names for flash bank power modes
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*
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* This enumeration is used to provide alias names for the flash bank power modes:
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* - sleep
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* - standby
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* - active
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*/
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enum flashWPowerModes
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{
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SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */
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SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */
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SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */
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|
|
};
|
||
|
|
|
||
|
|
/* USER CODE BEGIN (2) */
|
||
|
|
/* USER CODE END */
|
||
|
|
|
||
|
|
|
||
|
|
#define FSM_WR_ENA_HL (*(volatile uint32 *)0xFFF87288U)
|
||
|
|
#define EEPROM_CONFIG_HL (*(volatile uint32 *)0xFFF872B8U)
|
||
|
|
|
||
|
|
/* Configuration registers */
|
||
|
|
typedef struct tcmflash_config_reg
|
||
|
|
{
|
||
|
|
uint32 CONFIG_FRDCNTL;
|
||
|
|
uint32 CONFIG_FEDACCTRL1;
|
||
|
|
uint32 CONFIG_FEDACCTRL2;
|
||
|
|
uint32 CONFIG_FEDACSDIS;
|
||
|
|
uint32 CONFIG_FBPROT;
|
||
|
|
uint32 CONFIG_FBSE;
|
||
|
|
uint32 CONFIG_FBAC;
|
||
|
|
uint32 CONFIG_FBFALLBACK;
|
||
|
|
uint32 CONFIG_FPAC1;
|
||
|
|
uint32 CONFIG_FPAC2;
|
||
|
|
uint32 CONFIG_FMAC;
|
||
|
|
uint32 CONFIG_FLOCK;
|
||
|
|
uint32 CONFIG_FDIAGCTRL;
|
||
|
|
uint32 CONFIG_FEDACSDIS2;
|
||
|
|
} tcmflash_config_reg_t;
|
||
|
|
|
||
|
|
/* Configuration registers initial value */
|
||
|
|
#define TCMFLASH_FRDCNTL_CONFIGVALUE 0x00000000U | (3U << 8U) | (1U << 4U) | 1U
|
||
|
|
#define TCMFLASH_FEDACCTRL1_CONFIGVALUE 0x000A0005U
|
||
|
|
#define TCMFLASH_FEDACCTRL2_CONFIGVALUE 0U
|
||
|
|
#define TCMFLASH_FEDACSDIS_CONFIGVALUE 0U
|
||
|
|
#define TCMFLASH_FBPROT_CONFIGVALUE 0U
|
||
|
|
#define TCMFLASH_FBSE_CONFIGVALUE 0U
|
||
|
|
#define TCMFLASH_FBAC_CONFIGVALUE 0xFU
|
||
|
|
#define TCMFLASH_FBFALLBACK_CONFIGVALUE 0x00000000U\
|
||
|
|
| (SYS_ACTIVE << 14U) \
|
||
|
|
| (SYS_SLEEP << 12U) \
|
||
|
|
| (SYS_SLEEP << 10U) \
|
||
|
|
| (SYS_SLEEP << 8U) \
|
||
|
|
| (SYS_SLEEP << 6U) \
|
||
|
|
| (SYS_SLEEP << 4U) \
|
||
|
|
| (SYS_ACTIVE << 2U) \
|
||
|
|
| SYS_ACTIVE \
|
||
|
|
|
||
|
|
#define TCMFLASH_FPAC1_CONFIGVALUE 0x00C80001U
|
||
|
|
#define TCMFLASH_FPAC2_CONFIGVALUE 0U
|
||
|
|
#define TCMFLASH_FMAC_CONFIGVALUE 0U
|
||
|
|
#define TCMFLASH_FLOCK_CONFIGVALUE 0x55AAU
|
||
|
|
#define TCMFLASH_FDIAGCTRL_CONFIGVALUE 0x000A0000U
|
||
|
|
#define TCMFLASH_FEDACSDIS2_CONFIGVALUE 0U
|
||
|
|
|
||
|
|
void tcmflashGetConfigValue(tcmflash_config_reg_t *config_reg, config_value_type_t type);
|
||
|
|
|
||
|
|
/* USER CODE BEGIN (3) */
|
||
|
|
/* USER CODE END */
|
||
|
|
|
||
|
|
|
||
|
|
/* System Interface Functions */
|
||
|
|
void setupPLL(void);
|
||
|
|
void trimLPO(void);
|
||
|
|
void setupFlash(void);
|
||
|
|
void periphInit(void);
|
||
|
|
void mapClocks(void);
|
||
|
|
void systemInit(void);
|
||
|
|
void systemPowerDown(uint32 mode);
|
||
|
|
|
||
|
|
|
||
|
|
/*Configuration registers
|
||
|
|
* index 0: Even RAM
|
||
|
|
* index 1: Odd RAM
|
||
|
|
*/
|
||
|
|
typedef struct sram_config_reg
|
||
|
|
{
|
||
|
|
uint32 CONFIG_RAMCTRL[2U];
|
||
|
|
uint32 CONFIG_RAMTHRESHOLD[2U];
|
||
|
|
uint32 CONFIG_RAMINTCTRL[2U];
|
||
|
|
uint32 CONFIG_RAMTEST[2U];
|
||
|
|
uint32 CONFIG_RAMADDRDECVECT[2U];
|
||
|
|
} sram_config_reg_t;
|
||
|
|
|
||
|
|
/* Configuration registers initial value */
|
||
|
|
#define SRAM_RAMCTRL_CONFIGVALUE 0x0005000AU
|
||
|
|
#define SRAM_RAMTHRESHOLD_CONFIGVALUE 1U
|
||
|
|
#define SRAM_RAMINTCTRL_CONFIGVALUE 1U
|
||
|
|
#define SRAM_RAMTEST_CONFIGVALUE 0x5U
|
||
|
|
#define SRAM_RAMADDRDECVECT_CONFIGVALUE 0U
|
||
|
|
|
||
|
|
void sramGetConfigValue(sram_config_reg_t *config_reg, config_value_type_t type);
|
||
|
|
#endif
|