163 lines
8.6 KiB
C
163 lines
8.6 KiB
C
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/** @file reg_adc.h
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* @brief ADC Register Layer Header File
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* @date 23.May.2013
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* @version 03.05.01
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*
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* This file contains:
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* - Definitions
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* - Types
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* - Interface Prototypes
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* .
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* which are relevant for the ADC driver.
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*/
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/* (c) Texas Instruments 2009-2013, All rights reserved. */
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#ifndef __REG_ADC_H__
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#define __REG_ADC_H__
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#include "sys_common.h"
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/* USER CODE BEGIN (0) */
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/* USER CODE END */
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/* Adc Register Frame Definition */
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/** @struct adcBase
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* @brief ADC Register Frame Definition
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*
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* This type is used to access the ADC Registers.
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*/
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/** @typedef adcBASE_t
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* @brief ADC Register Frame Type Definition
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*
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* This type is used to access the ADC Registers.
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*/
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typedef volatile struct adcBase
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{
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uint32 RSTCR; /**< 0x0000: Reset control register */
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uint32 OPMODECR; /**< 0x0004: Operating mode control register */
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uint32 CLOCKCR; /**< 0x0008: Clock control register */
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uint32 CALCR; /**< 0x000C: Calibration control register */
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uint32 GxMODECR[3U]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */
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uint32 G0SRC; /**< 0x001C: Group 0 trigger source control register */
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uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */
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uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */
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uint32 GxINTENA[3U]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register */
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uint32 GxINTFLG[3U]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */
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uint32 GxINTCR[3U]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */
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uint32 G0DMACR; /**< 0x004C: Group 0 DMA control register */
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uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */
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uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */
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uint32 BNDCR; /**< 0x0058: Buffer boundary control register */
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uint32 BNDEND; /**< 0x005C: Buffer boundary end register */
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uint32 G0SAMP; /**< 0x0060: Group 0 sample window register */
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uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */
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uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */
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uint32 G0SR; /**< 0x006C: Group 0 status register */
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uint32 G1SR; /**< 0x0070: Group 1 status register */
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uint32 G2SR; /**< 0x0074: Group 2 status register */
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uint32 GxSEL[3U]; /**< 0x0078-0x007C: Group 0-2 channel select register */
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uint32 CALR; /**< 0x0084: Calibration register */
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uint32 SMSTATE; /**< 0x0088: State machine state register */
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uint32 LASTCONV; /**< 0x008C: Last conversion register */
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struct
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{
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uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */
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uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */
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uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */
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uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */
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uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */
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uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */
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uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */
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uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */
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} GxBUF[3U];
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uint32 G0EMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */
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uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */
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uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */
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uint32 EVTDIR; /**< 0x00FC: Event pin direction register */
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uint32 EVTOUT; /**< 0x0100: Event pin digital output register */
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uint32 EVTIN; /**< 0x0104: Event pin digital input register */
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uint32 EVTSET; /**< 0x0108: Event pin set register */
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uint32 EVTCLR; /**< 0x010C: Event pin clear register */
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uint32 EVTPDR; /**< 0x0110: Event pin open drain register */
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uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */
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uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */
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uint32 G0SAMPDISEN; /**< 0x011C: Group 0 sample discharge register */
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uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */
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uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */
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uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */
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uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */
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uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */
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uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */
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uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */
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uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */
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uint32 MAGINTCR4; /**< 0x0140: Magnitude interrupt control register 4 */
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uint32 MAGINT4MASK; /**< 0x0144: Magnitude interrupt mask register 4 */
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uint32 MAGINTCR5; /**< 0x0148: Magnitude interrupt control register 5 */
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uint32 MAGINT5MASK; /**< 0x014C: Magnitude interrupt mask register 5 */
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uint32 MAGINTCR6; /**< 0x0150: Magnitude interrupt control register 6 */
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uint32 MAGINT6MASK; /**< 0x0154: Magnitude interrupt mask register 6 */
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uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */
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uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */
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uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */
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uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */
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uint32 GxFIFORESETCR[3U]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register */
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uint32 G0RAMADDR; /**< 0x0174: Group 0 RAM pointer register */
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uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */
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uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */
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uint32 PARCR; /**< 0x0180: Parity control register */
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uint32 PARADDR; /**< 0x0184: Parity error address register */
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uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */
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} adcBASE_t;
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/** @def adcREG1
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* @brief ADC1 Register Frame Pointer
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*
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* This pointer is used by the ADC driver to access the ADC1 registers.
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*/
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#define adcREG1 ((adcBASE_t *)0xFFF7C000U)
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/** @def adcREG2
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* @brief ADC2 Register Frame Pointer
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*
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* This pointer is used by the ADC driver to access the ADC2 registers.
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*/
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#define adcREG2 ((adcBASE_t *)0xFFF7C200U)
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/** @def adcRAM1
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* @brief ADC1 RAM Pointer
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*
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* This pointer is used by the ADC driver to access the ADC1 RAM.
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*/
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#define adcRAM1 (*(volatile uint32 *)0xFF3E0000U)
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/** @def adcRAM2
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* @brief ADC2 RAM Pointer
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*
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* This pointer is used by the ADC driver to access the ADC2 RAM.
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*/
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#define adcRAM2 (*(volatile uint32 *)0xFF3A0000U)
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/** @def adcPARRAM1
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* @brief ADC1 Parity RAM Pointer
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*
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* This pointer is used by the ADC driver to access the ADC1 Parity RAM.
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*/
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#define adcPARRAM1 (*(volatile uint32 *)(0xFF3E0000U + 0x1000U))
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/** @def adcPARRAM2
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* @brief ADC2 Parity RAM Pointer
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*
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* This pointer is used by the ADC driver to access the ADC2 Parity RAM.
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*/
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#define adcPARRAM2 (*(volatile uint32 *)(0xFF3A0000U + 0x1000U))
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/* USER CODE BEGIN (1) */
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/* USER CODE END */
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#endif
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