64 lines
2.6 KiB
C
64 lines
2.6 KiB
C
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006-2011, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-05-23 aozima first implementation for PIC32.
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*/
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// Adds support for PIC32 Peripheral library functions and macros
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#include <plib.h>
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// Configuration Bits
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#pragma config FNOSC = PRIPLL // Oscillator Selection
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#pragma config FPLLIDIV = DIV_2 // PLL Input Divider (PIC32 Starter Kit: use divide by 2 only)
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#pragma config FPLLMUL = MUL_20 // PLL Multiplier
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#pragma config FPLLODIV = DIV_1 // PLL Output Divider
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#pragma config FPBDIV = DIV_1 // Peripheral Clock divisor
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#pragma config FWDTEN = OFF // Watchdog Timer
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#pragma config WDTPS = PS1 // Watchdog Timer Postscale
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#pragma config FCKSM = CSDCMD // Clock Switching & Fail Safe Clock Monitor
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#pragma config OSCIOFNC = OFF // CLKO Enable
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#pragma config POSCMOD = XT // Primary Oscillator
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#pragma config IESO = OFF // Internal/External Switch-over
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#pragma config FSOSCEN = OFF // Secondary Oscillator Enable
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#pragma config CP = OFF // Code Protect
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#pragma config BWP = OFF // Boot Flash Write Protect
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#pragma config PWP = OFF // Program Flash Write Protect
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#pragma config ICESEL = ICS_PGx2 // ICE/ICD Comm Channel Select
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#pragma config DEBUG = OFF // Debugger Disabled for Starter Kit
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// The following is used by the main application
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#define SYS_FREQ (80000000)
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static void rt_hw_show_info(void)
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{
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rt_kprintf("\r\n\r\n---------- board info ----------\r\n");
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rt_kprintf("DEVICE_FAMILY: PIC32\r\n");
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rt_kprintf("CPU_ARCHITECTURE: MIPS\r\n");
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rt_kprintf("CPU_FREQ: %uMHz\r\n",SYS_FREQ/1000000UL);
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}
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/**
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* This function will initial FM3 Easy Kit board.
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*/
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void rt_hw_board_init()
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{
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// Configure the device for maximum performance, but do not change the PBDIV clock divisor.
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// Given the options, this function will change the program Flash wait states,
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// RAM wait state and enable prefetch cache, but will not change the PBDIV.
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// The PBDIV value is already set via the pragma FPBDIV option above.
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SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
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rt_hw_console_init();
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rt_hw_show_info();
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}
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