138 lines
12 KiB
C
138 lines
12 KiB
C
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/**************************************************************************//**
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* @file
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* @brief efm32g_dmactrl Register and Bit Field definitions
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* @author Energy Micro AS
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* @version 3.0.0
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******************************************************************************
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* @section License
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* <b>(C) Copyright 2012 Energy Micro AS, http://www.energymicro.com</b>
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******************************************************************************
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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*****************************************************************************/
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/**************************************************************************//**
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* @defgroup EFM32G_DMACTRL_BitFields
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* @{
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*****************************************************************************/
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#define _DMA_CTRL_DST_INC_MASK 0xC0000000UL /**< Data increment for destination, bit mask */
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#define _DMA_CTRL_DST_INC_SHIFT 30 /**< Data increment for destination, shift value */
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#define _DMA_CTRL_DST_INC_BYTE 0x00 /**< Byte/8-bit increment */
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#define _DMA_CTRL_DST_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
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#define _DMA_CTRL_DST_INC_WORD 0x02 /**< Word/32-bit increment */
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#define _DMA_CTRL_DST_INC_NONE 0x03 /**< No increment */
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#define DMA_CTRL_DST_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
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#define DMA_CTRL_DST_INC_HALFWORD 0x40000000UL /**< Half word/16-bit increment */
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#define DMA_CTRL_DST_INC_WORD 0x80000000UL /**< Word/32-bit increment */
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#define DMA_CTRL_DST_INC_NONE 0xC0000000UL /**< No increment */
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#define _DMA_CTRL_DST_SIZE_MASK 0x30000000UL /**< Data size for destination - MUST be the same as source, bit mask */
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#define _DMA_CTRL_DST_SIZE_SHIFT 28 /**< Data size for destination - MUST be the same as source, shift value */
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#define _DMA_CTRL_DST_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
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#define _DMA_CTRL_DST_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
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#define _DMA_CTRL_DST_SIZE_WORD 0x02 /**< Word/32-bit data size */
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#define _DMA_CTRL_DST_SIZE_RSVD 0x03 /**< Reserved */
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#define DMA_CTRL_DST_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
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#define DMA_CTRL_DST_SIZE_HALFWORD 0x10000000UL /**< Half word/16-bit data size */
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#define DMA_CTRL_DST_SIZE_WORD 0x20000000UL /**< Word/32-bit data size */
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#define DMA_CTRL_DST_SIZE_RSVD 0x30000000UL /**< Reserved - do not use */
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#define _DMA_CTRL_SRC_INC_MASK 0x0C000000UL /**< Data increment for source, bit mask */
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#define _DMA_CTRL_SRC_INC_SHIFT 26 /**< Data increment for source, shift value */
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#define _DMA_CTRL_SRC_INC_BYTE 0x00 /**< Byte/8-bit increment */
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#define _DMA_CTRL_SRC_INC_HALFWORD 0x01 /**< Half word/16-bit increment */
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#define _DMA_CTRL_SRC_INC_WORD 0x02 /**< Word/32-bit increment */
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#define _DMA_CTRL_SRC_INC_NONE 0x03 /**< No increment */
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#define DMA_CTRL_SRC_INC_BYTE 0x00000000UL /**< Byte/8-bit increment */
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#define DMA_CTRL_SRC_INC_HALFWORD 0x04000000UL /**< Half word/16-bit increment */
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#define DMA_CTRL_SRC_INC_WORD 0x08000000UL /**< Word/32-bit increment */
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#define DMA_CTRL_SRC_INC_NONE 0x0C000000UL /**< No increment */
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#define _DMA_CTRL_SRC_SIZE_MASK 0x03000000UL /**< Data size for source - MUST be the same as destination, bit mask */
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#define _DMA_CTRL_SRC_SIZE_SHIFT 24 /**< Data size for source - MUST be the same as destination, shift value */
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#define _DMA_CTRL_SRC_SIZE_BYTE 0x00 /**< Byte/8-bit data size */
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#define _DMA_CTRL_SRC_SIZE_HALFWORD 0x01 /**< Half word/16-bit data size */
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#define _DMA_CTRL_SRC_SIZE_WORD 0x02 /**< Word/32-bit data size */
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#define _DMA_CTRL_SRC_SIZE_RSVD 0x03 /**< Reserved */
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#define DMA_CTRL_SRC_SIZE_BYTE 0x00000000UL /**< Byte/8-bit data size */
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#define DMA_CTRL_SRC_SIZE_HALFWORD 0x01000000UL /**< Half word/16-bit data size */
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#define DMA_CTRL_SRC_SIZE_WORD 0x02000000UL /**< Word/32-bit data size */
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#define DMA_CTRL_SRC_SIZE_RSVD 0x03000000UL /**< Reserved - do not use */
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#define _DMA_CTRL_DST_PROT_CTRL_MASK 0x00E00000UL /**< Protection flag for destination, bit mask */
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#define _DMA_CTRL_DST_PROT_CTRL_SHIFT 21 /**< Protection flag for destination, shift value */
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#define DMA_CTRL_DST_PROT_PRIVILEGED 0x00200000UL /**< Privileged mode for destination */
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#define DMA_CTRL_DST_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */
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#define _DMA_CTRL_SRC_PROT_CTRL_MASK 0x001C0000UL /**< Protection flag for source, bit mask */
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#define _DMA_CTRL_SRC_PROT_CTRL_SHIFT 18 /**< Protection flag for source, shift value */
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#define DMA_CTRL_SRC_PROT_PRIVILEGED 0x00040000UL /**< Privileged mode for destination */
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#define DMA_CTRL_SRC_PROT_NON_PRIVILEGED 0x00000000UL /**< Non-privileged mode for estination */
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#define _DMA_CTRL_PROT_NON_PRIVILEGED 0x00 /**< Protection bits to indicate non-privileged access */
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#define _DMA_CTRL_PROT_PRIVILEGED 0x01 /**< Protection bits to indicate privileged access */
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#define _DMA_CTRL_R_POWER_MASK 0x0003C000UL /**< DMA arbitration mask */
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#define _DMA_CTRL_R_POWER_SHIFT 14 /**< Number of DMA cycles before controller does new arbitration in 2^R */
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#define _DMA_CTRL_R_POWER_1 0x00 /**< Arbitrate after each transfer */
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#define _DMA_CTRL_R_POWER_2 0x01 /**< Arbitrate after every 2 transfers */
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#define _DMA_CTRL_R_POWER_4 0x02 /**< Arbitrate after every 4 transfers */
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#define _DMA_CTRL_R_POWER_8 0x03 /**< Arbitrate after every 8 transfers */
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#define _DMA_CTRL_R_POWER_16 0x04 /**< Arbitrate after every 16 transfers */
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#define _DMA_CTRL_R_POWER_32 0x05 /**< Arbitrate after every 32 transfers */
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#define _DMA_CTRL_R_POWER_64 0x06 /**< Arbitrate after every 64 transfers */
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#define _DMA_CTRL_R_POWER_128 0x07 /**< Arbitrate after every 128 transfers */
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#define _DMA_CTRL_R_POWER_256 0x08 /**< Arbitrate after every 256 transfers */
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#define _DMA_CTRL_R_POWER_512 0x09 /**< Arbitrate after every 512 transfers */
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#define _DMA_CTRL_R_POWER_1024 0x0a /**< Arbitrate after every 1024 transfers */
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#define DMA_CTRL_R_POWER_1 0x00000000UL /**< Arbitrate after each transfer */
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#define DMA_CTRL_R_POWER_2 0x00004000UL /**< Arbitrate after every 2 transfers */
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#define DMA_CTRL_R_POWER_4 0x00008000UL /**< Arbitrate after every 4 transfers */
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#define DMA_CTRL_R_POWER_8 0x0000c000UL /**< Arbitrate after every 8 transfers */
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#define DMA_CTRL_R_POWER_16 0x00010000UL /**< Arbitrate after every 16 transfers */
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#define DMA_CTRL_R_POWER_32 0x00014000UL /**< Arbitrate after every 32 transfers */
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#define DMA_CTRL_R_POWER_64 0x00018000UL /**< Arbitrate after every 64 transfers */
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#define DMA_CTRL_R_POWER_128 0x0001c000UL /**< Arbitrate after every 128 transfers */
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#define DMA_CTRL_R_POWER_256 0x00020000UL /**< Arbitrate after every 256 transfers */
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#define DMA_CTRL_R_POWER_512 0x00024000UL /**< Arbitrate after every 512 transfers */
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#define DMA_CTRL_R_POWER_1024 0x00028000UL /**< Arbitrate after every 1024 transfers */
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#define _DMA_CTRL_N_MINUS_1_MASK 0x00003FF0UL /**< Number of DMA transfers minus 1, bit mask. See PL230 documentation */
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#define _DMA_CTRL_N_MINUS_1_SHIFT 4 /**< Number of DMA transfers minus 1, shift mask. See PL230 documentation */
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#define _DMA_CTRL_NEXT_USEBURST_MASK 0x00000008UL /**< DMA useburst_set[C] is 1 when using scatter-gather DMA and using alternate data */
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#define _DMA_CTRL_NEXT_USEBURST_SHIFT 3 /**< DMA useburst shift */
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#define _DMA_CTRL_CYCLE_CTRL_MASK 0x00000007UL /**< DMA Cycle control bit mask - basic/auto/ping-poing/scath-gath */
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#define _DMA_CTRL_CYCLE_CTRL_SHIFT 0 /**< DMA Cycle control bit shift */
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#define _DMA_CTRL_CYCLE_CTRL_INVALID 0x00 /**< Invalid cycle type */
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#define _DMA_CTRL_CYCLE_CTRL_BASIC 0x01 /**< Basic cycle type */
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#define _DMA_CTRL_CYCLE_CTRL_AUTO 0x02 /**< Auto cycle type */
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#define _DMA_CTRL_CYCLE_CTRL_PINGPONG 0x03 /**< PingPong cycle type */
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#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x04 /**< Memory scatter gather cycle type */
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#define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x05 /**< Memory scatter gather using alternate structure */
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#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x06 /**< Peripheral scatter gather cycle type */
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#define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x07 /**< Peripheral scatter gather cycle type using alternate structure */
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#define DMA_CTRL_CYCLE_CTRL_INVALID 0x00000000UL /**< Invalid cycle type */
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#define DMA_CTRL_CYCLE_CTRL_BASIC 0x00000001UL /**< Basic cycle type */
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#define DMA_CTRL_CYCLE_CTRL_AUTO 0x00000002UL /**< Auto cycle type */
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#define DMA_CTRL_CYCLE_CTRL_PINGPONG 0x00000003UL /**< PingPong cycle type */
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#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER 0x000000004UL /**< Memory scatter gather cycle type */
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#define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT 0x000000005UL /**< Memory scatter gather using alternate structure */
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#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER 0x000000006UL /**< Peripheral scatter gather cycle type */
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#define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT 0x000000007UL /**< Peripheral scatter gather cycle type using alternate structure */
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/** @} End of group EFM32G_DMA */
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