68 lines
2.8 KiB
C
68 lines
2.8 KiB
C
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/*
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* File : drv_sdram.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2015 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2015-08-03 xiaonong The first version for STM32F7
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*/
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#ifndef __DRV_SDRAM_H__
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#define __DRV_SDRAM_H__
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#include <rtthread.h>
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#include <board.h>
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/** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Constants STM32746G_DISCOVERY_SDRAM Exported Constants
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* @{
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*/
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#define SDRAM_DEVICE_ADDR ((uint32_t)EXT_SDRAM_BEGIN)
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#define SDRAM_DEVICE_SIZE ((uint32_t)EXT_SDRAM_SIZE) /* SDRAM device size in MBytes */
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/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
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#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
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#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2
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/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
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#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */
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#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
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/* DMA definitions for SDRAM DMA transfer */
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#define SDRAM_DMA_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
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#define SDRAM_DMA_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
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#define SDRAM_DMA_CHANNEL DMA_CHANNEL_0
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#define SDRAM_DMA_STREAM DMA2_Stream0
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#define SDRAM_DMA_IRQn DMA2_Stream0_IRQn
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#define SDRAM_DMA_IRQHandler DMA2_Stream0_IRQHandler
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/**
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* @brief FMC SDRAM Mode definition register defines
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*/
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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rt_err_t sdram_hw_init(void);
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rt_err_t sdram_hw_deinit(void);
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rt_err_t SDRAM_WriteDataDMA(uint32_t Address, uint32_t *Data, uint32_t DataSize);
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rt_err_t SDRAM_WriteData(uint32_t Address, uint32_t *Data, uint32_t DataSize);
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rt_err_t SDRAM_ReadDataDMA(uint32_t Address, uint32_t *Data, uint32_t DataSize);
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rt_err_t SDRAM_ReadData(uint32_t Address, uint32_t *Data, uint32_t DataSize);
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#endif
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