370 lines
12 KiB
C
370 lines
12 KiB
C
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/*
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* @brief I2C master ROM API declarations and functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2014
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "hw_i2cmd.h"
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#define DRVVERSION 0x0100
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/* Private data structure used for the I2C master driver, holds the driver and
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peripheral context */
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typedef struct {
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void *pUserData; /*!< Pointer to user data used by driver instance, use NULL if not used */
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LPC_I2C_T *base; /*!< Base address of I2C peripheral to use */
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i2cMasterCompleteCB pXferCompCB; /*!< Transfer complete callback */
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i2cMasterTransmitStartCB pTranStartCb; /*!< Transmit data start callback */
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i2cMasterReceiveStartCB pTranRecvCb; /*!< Receive data start callback */
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ROM_I2CM_XFER_T *pXfer; /*!< Pointer to current transfer */
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ErrorCode_t pendingStatus; /*!< Pending master transfer status before clocking transfer */
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uint16_t sendIdx;
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uint16_t recvIdx;
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} I2CM_DATACONTEXT_T;
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#define _rom_i2cmEnable(pI2C) (pI2C->CFG |= I2C_CFG_MSTEN);
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#define _rom_i2cmGetMasterState(pI2C) ((pI2C->STAT & I2C_STAT_MSTSTATE) >> 1)
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/* Sets I2C Clock Divider registers */
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static void _rom_i2cmSetClockDiv(LPC_I2C_T *pI2C, uint32_t clkdiv)
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{
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if ((clkdiv >= 1) && (clkdiv <= 65536)) {
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pI2C->CLKDIV = clkdiv - 1;
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}
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else {
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pI2C->CLKDIV = 0;
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}
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}
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/* Sets HIGH and LOW duty cycle registers */
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static void _rom_i2cmSetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL)
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{
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/* Limit to usable range of timing values */
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if (sclH < 2) {
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sclH = 2;
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}
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else if (sclH > 9) {
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sclH = 9;
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}
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if (sclL < 2) {
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sclL = 2;
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}
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else if (sclL > 9) {
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sclL = 9;
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}
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pI2C->MSTTIME = (((sclH - 2) & 0x07) << 4) | ((sclL - 2) & 0x07);
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}
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// **********************************************************
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uint32_t i2cm_get_mem_size(void)
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{
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return sizeof(I2CM_DATACONTEXT_T);
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}
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ROM_I2CM_HANDLE_T i2cm_init(void *mem, const ROM_I2CM_INIT_T *pInit)
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{
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I2CM_DATACONTEXT_T *pDrv;
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/* Verify alignment is at least 4 bytes */
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if (((uint32_t) mem & 0x3) != 0) {
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return NULL;
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}
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pDrv = (I2CM_DATACONTEXT_T *) mem;
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memset(pDrv, 0, sizeof(I2CM_DATACONTEXT_T));
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/* Save base of peripheral and pointer to user data */
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pDrv->pUserData = pInit->pUserData;
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pDrv->base = (LPC_I2C_T *) pInit->base;
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/* Pick a safe clock divider until clock rate is setup */
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_rom_i2cmSetClockDiv(pDrv->base, 8);
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/* Clear pending master statuses */
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pDrv->base->STAT = (I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR);
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/* Enable I2C master interface */
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_rom_i2cmEnable(pDrv->base);
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return pDrv;
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}
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uint32_t i2cm_set_clock_rate(ROM_I2CM_HANDLE_T pHandle, uint32_t inRate, uint32_t i2cRate)
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{
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uint32_t scl, div;
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I2CM_DATACONTEXT_T *pDrv = (I2CM_DATACONTEXT_T *) pHandle;
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/* Determine the best I2C clock dividers to generate the target I2C master clock */
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/* The maximum SCL and SCH dividers are 7, for a maximum divider set of 14 */
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/* The I2C master divider is between 1 and 65536. */
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/* Pick a main I2C divider that allows centered SCL/SCH dividers */
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div = inRate / (i2cRate << 3);
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if (div == 0) {
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div = 1;
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}
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_rom_i2cmSetClockDiv(pDrv->base, div);
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/* Determine SCL/SCH dividers */
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scl = inRate / (div * i2cRate);
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_rom_i2cmSetDutyCycle(pDrv->base, (scl >> 1), (scl - (scl >> 1)));
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return inRate / (div * scl);
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}
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void i2cm_register_callback(ROM_I2CM_HANDLE_T pHandle, uint32_t cbIndex, void *pCB)
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{
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I2CM_DATACONTEXT_T *pDrv = (I2CM_DATACONTEXT_T *) pHandle;
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if (cbIndex == ROM_I2CM_DATACOMPLETE_CB) {
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pDrv->pXferCompCB = (i2cMasterCompleteCB) pCB;
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}
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else if (cbIndex == ROM_I2CM_DATATRANSMITSTART_CB) {
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pDrv->pTranStartCb = (i2cMasterTransmitStartCB) pCB;
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}
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else if (cbIndex == ROM_I2CM_DATATRECEIVESTART_CB) {
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pDrv->pTranRecvCb = (i2cMasterReceiveStartCB) pCB;
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}
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}
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ErrorCode_t i2cm_transfer(ROM_I2CM_HANDLE_T pHandle, ROM_I2CM_XFER_T *pXfer)
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{
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I2CM_DATACONTEXT_T *pDrv = (I2CM_DATACONTEXT_T *) pHandle;
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/* Is transfer NULL? */
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if (pXfer == NULL) {
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return ERR_I2C_PARAM;
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}
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/* I2C master controller should be pending and idle */
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if ((pDrv->base->STAT & I2C_STAT_MSTPENDING) == 0) {
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pXfer->status = ERR_I2C_GENERAL_FAILURE;
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return ERR_I2C_GENERAL_FAILURE;
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}
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if (_rom_i2cmGetMasterState(pDrv->base) != I2C_STAT_MSTCODE_IDLE) {
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pXfer->status = ERR_I2C_GENERAL_FAILURE;
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return ERR_I2C_GENERAL_FAILURE;
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}
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/* Save transfer descriptor */
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pDrv->pXfer = pXfer;
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pXfer->status = ERR_I2C_BUSY;
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pDrv->sendIdx = 0;
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pDrv->recvIdx = 0;
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/* Pending status for completion of trasnfer */
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pDrv->pendingStatus = ERR_I2C_GENERAL_FAILURE;
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/* Clear controller state */
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pDrv->base->STAT = (I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR);
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/* Will always transisiton to idle at start or end of transfer */
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if (pXfer->txSz) {
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/* Call transmit start callback to setup TX DMA if needed */
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if (pDrv->pTranStartCb) {
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pDrv->pTranStartCb(pHandle, pXfer);
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}
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/* Start transmit state */
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pDrv->base->MSTDAT = (uint32_t) (pXfer->slaveAddr << 1);
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pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTART;
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}
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else if (pXfer->rxSz) {
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/* Start receive state with start ot repeat start */
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pDrv->base->MSTDAT = (uint32_t) (pXfer->slaveAddr << 1) | 0x1;
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pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTART;
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/* Call receive start callback to setup RX DMA if needed */
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if (pDrv->pTranRecvCb) {
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pDrv->pTranRecvCb(pHandle, pXfer);
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}
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}
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else {
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/* No data - either via data callbacks or a slave query only */
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pDrv->base->MSTDAT = (uint32_t) (pXfer->slaveAddr << 1);
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pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTART;
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}
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/* Enable supported master interrupts */
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pDrv->base->INTENSET = (I2C_INTENSET_MSTPENDING | I2C_INTENSET_MSTRARBLOSS |
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I2C_INTENSET_MSTSTSTPERR);
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/* Does the driver need to block? */
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if ((pXfer->flags & ROM_I2CM_FLAG_BLOCKING) != 0) {
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while (pXfer->status == ERR_I2C_BUSY) {
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i2cm_transfer_handler(pHandle);
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}
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}
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return pXfer->status;
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}
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// Otime = "optimize for speed of code execution"
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// ...add this pragma 1 line above the interrupt service routine function.
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void i2cm_transfer_handler(ROM_I2CM_HANDLE_T pHandle)
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{
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I2CM_DATACONTEXT_T *pDrv = (I2CM_DATACONTEXT_T *) pHandle;
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ROM_I2CM_XFER_T *pXfer = pDrv->pXfer;
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uint32_t status = pDrv->base->STAT;
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if (status & I2C_STAT_MSTRARBLOSS) {
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/* Master Lost Arbitration */
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/* Set transfer status as Arbitration Lost */
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pDrv->pendingStatus = ERR_I2C_LOSS_OF_ARBRITRATION;
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/* Clear Status Flags */
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pDrv->base->STAT = I2C_STAT_MSTRARBLOSS;
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pDrv->base->INTENCLR = (I2C_INTENSET_MSTPENDING | I2C_INTENSET_MSTRARBLOSS |
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I2C_INTENSET_MSTSTSTPERR);
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pXfer->status = pDrv->pendingStatus;
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if (pDrv->pXferCompCB != NULL) {
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pDrv->pXferCompCB(pHandle, pXfer);
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}
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}
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else if (status & I2C_STAT_MSTSTSTPERR) {
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/* Master Start Stop Error */
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/* Set transfer status as Bus Error */
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pDrv->pendingStatus = ERR_I2C_GENERAL_FAILURE;
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/* Clear Status Flags */
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pDrv->base->STAT = I2C_STAT_MSTSTSTPERR;
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pDrv->base->INTENCLR = (I2C_INTENSET_MSTPENDING | I2C_INTENSET_MSTRARBLOSS |
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I2C_INTENSET_MSTSTSTPERR);
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pXfer->status = pDrv->pendingStatus;
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if (pDrv->pXferCompCB != NULL) {
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pDrv->pXferCompCB(pHandle, pXfer);
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}
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}
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else if (status & I2C_STAT_MSTPENDING) {
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/* Master is Pending */
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/* Branch based on Master State Code */
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switch (_rom_i2cmGetMasterState(pDrv->base)) {
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case I2C_STAT_MSTCODE_IDLE: /* Master idle */
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/* Idle state is only called on completion of transfer */
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/* Disable interrupts */
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pDrv->base->INTENCLR = (I2C_INTENSET_MSTPENDING | I2C_INTENSET_MSTRARBLOSS |
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I2C_INTENSET_MSTSTSTPERR);
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/* Update status and call transfer completion callback */
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pXfer->status = pDrv->pendingStatus;
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if (pDrv->pXferCompCB != NULL) {
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pDrv->pXferCompCB(pHandle, pXfer);
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}
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break;
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case I2C_STAT_MSTCODE_RXREADY: /* Receive data is available */
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if (((pXfer->flags & ROM_I2CM_FLAG_DMARX) != 0) && (pXfer->rxSz > 0)) {
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/* Use DMA for receive */
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pDrv->base->MSTCTL = I2C_MSTCTL_MSTDMA;
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pXfer->flags &= ~ROM_I2CM_FLAG_DMARX;
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pXfer->rxSz = 0;
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return;
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}
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else if (pXfer->rxSz) {
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uint8_t *p8 = pXfer->rxBuff;
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p8[pDrv->recvIdx] = (uint8_t) pDrv->base->MSTDAT & 0xFF;
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pDrv->recvIdx++;
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pXfer->rxSz--;
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}
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if (pXfer->rxSz) {
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pDrv->base->MSTCTL = I2C_MSTCTL_MSTCONTINUE;
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}
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else {
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/* Last byte to receive, send stop after byte received */
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pDrv->base->MSTCTL = I2C_MSTCTL_MSTCONTINUE | I2C_MSTCTL_MSTSTOP;
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pDrv->pendingStatus = LPC_OK;
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}
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break;
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case I2C_STAT_MSTCODE_TXREADY: /* Master Transmit available */
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if (((pXfer->flags & ROM_I2CM_FLAG_DMATX) != 0) && (pXfer->txSz > 0)) {
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/* Use DMA for transmit */
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pDrv->base->MSTCTL = I2C_MSTCTL_MSTDMA;
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pXfer->flags &= ~ROM_I2CM_FLAG_DMATX;
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pXfer->txSz = 0;
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return;
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}
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else if (pXfer->txSz) {
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uint8_t *p8 = (uint8_t *) pXfer->txBuff;
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/* If Tx data available transmit data and continue */
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pDrv->base->MSTDAT = (uint32_t) p8[pDrv->sendIdx];
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pDrv->base->MSTCTL = I2C_MSTCTL_MSTCONTINUE;
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pDrv->sendIdx++;
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pXfer->txSz--;
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}
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else if (pXfer->rxSz == 0) {
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pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTOP;
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|
pDrv->pendingStatus = LPC_OK;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
/* Start receive state with repeat start */
|
||
|
|
pDrv->base->MSTDAT = (uint32_t) (pXfer->slaveAddr << 1) | 0x1;
|
||
|
|
pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTART;
|
||
|
|
|
||
|
|
/* Call receive start callback to setup RX DMA if needed */
|
||
|
|
if (pDrv->pTranRecvCb) {
|
||
|
|
pDrv->pTranRecvCb(pHandle, pXfer);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
|
||
|
|
case I2C_STAT_MSTCODE_NACKADR: /* Slave address was NACK'ed */
|
||
|
|
/* Set transfer status as NACK on address */
|
||
|
|
pDrv->pendingStatus = ERR_I2C_SLAVE_NOT_ADDRESSED;
|
||
|
|
pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTOP;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case I2C_STAT_MSTCODE_NACKDAT: /* Slave data was NACK'ed */
|
||
|
|
/* Set transfer status as NACK on data */
|
||
|
|
pDrv->pendingStatus = ERR_I2C_NAK;
|
||
|
|
pDrv->base->MSTCTL = I2C_MSTCTL_MSTSTOP;
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
/* Illegal I2C master state machine case. This should never happen.
|
||
|
|
Disable and re-enable controller to clear state machine */
|
||
|
|
pDrv->pendingStatus = ERR_I2C_GENERAL_FAILURE;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
uint32_t i2cm_get_driver_version(void)
|
||
|
|
{
|
||
|
|
return DRVVERSION;
|
||
|
|
}
|
||
|
|
|
||
|
|
// *********************************************************
|