rtt-f030/bsp/stm32f429-apollo/drivers/drv_nand.h

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __DRV_NAND_H
#define __DRV_NAND_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include <rtthread.h>
#include <board.h>
#include "stm32f4xx.h"
#include <rtdevice.h>
     
//********************************************************************************
//<2F><><EFBFBD><EFBFBD>˵<EFBFBD><CBB5>
//V1.1 20160520
//1,<2C><><EFBFBD><EFBFBD>Ӳ<EFBFBD><D3B2>ECC֧<43><D6A7>(<28><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>NAND_ECC_SECTOR_SIZE<5A><45>СΪ<D0A1><CEAA>λ<EFBFBD><CEBB><EFBFBD>ж<EFBFBD>дʱ<D0B4><CAB1><EFBFBD><EFBFBD>)
//2,<2C><><EFBFBD><EFBFBD>NAND_Delay<61><79><EFBFBD><EFBFBD>,<2C><><EFBFBD>ڵȴ<DAB5>tADL/tWHR
//3,<2C><><EFBFBD><EFBFBD>NAND_WritePageConst<73><74><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ѱ<EFBFBD><D1B0><EFBFBD><EFBFBD>.
//V1.2 20160525
//1,ȥ<><C8A5>NAND_SEC_SIZE<5A>궨<EFBFBD>壬<EFBFBD><E5A3AC>NAND_ECC_SECTOR_SIZE<5A><45><EFBFBD><EFBFBD>
//2,ȥ<><C8A5>nand_dev<65>ṹ<EFBFBD><E1B9B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>secbufָ<66>룬<EFBFBD>ò<EFBFBD><C3B2><EFBFBD>
////////////////////////////////////////////////////////////////////////////////// 	
 
#define NAND_MAX_PAGE_SIZE			4096		//<2F><><EFBFBD><EFBFBD>NAND FLASH<53><48><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>PAGE<47><45>С<EFBFBD><D0A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>SPARE<52><45><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD><C4AC>4096<39>ֽ<EFBFBD>
#define NAND_ECC_SECTOR_SIZE		512			//ִ<><D6B4>ECC<43><43><EFBFBD><EFBFBD><EFBFBD>ĵ<EFBFBD>Ԫ<EFBFBD><D4AA>С<EFBFBD><D0A1>Ĭ<EFBFBD><C4AC>512<31>ֽ<EFBFBD>

//NAND<4E><44><EFBFBD>Խṹ<D4BD><E1B9B9>
typedef struct
{
    uint16_t page_totalsize;     	//ÿҳ<C3BF>ܴ<EFBFBD>С<EFBFBD><D0A1>main<69><6E><EFBFBD><EFBFBD>spare<72><65><EFBFBD>ܺ<EFBFBD>
    uint16_t page_mainsize;      	//ÿҳ<C3BF><D2B3>main<69><6E><EFBFBD><EFBFBD>С
    uint16_t page_sparesize;     	//ÿҳ<C3BF><D2B3>spare<72><65><EFBFBD><EFBFBD>С
    uint8_t  block_pagenum;      	//ÿ<><C3BF><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ҳ<EFBFBD><D2B3><EFBFBD><EFBFBD>
    uint16_t plane_blocknum;     	//ÿ<><C3BF>plane<6E><65><EFBFBD><EFBFBD><EFBFBD>Ŀ<EFBFBD><C4BF><EFBFBD><EFBFBD><EFBFBD>
    uint16_t block_totalnum;     	//<2F>ܵĿ<DCB5><C4BF><EFBFBD><EFBFBD><EFBFBD>
    uint16_t good_blocknum;      	//<2F>ÿ<EFBFBD><C3BF><EFBFBD><EFBFBD><EFBFBD>    
    uint16_t valid_blocknum;     	//<2F><>Ч<EFBFBD><D0A7><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(<28><><EFBFBD>ļ<EFBFBD>ϵͳʹ<CDB3>õĺÿ<C4BA><C3BF><EFBFBD><EFBFBD><EFBFBD>)
    uint32_t id;             		//NAND FLASH ID
    uint16_t *lut;      			   	//LUT<55><54><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>߼<EFBFBD><DFBC><EFBFBD>-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ת<EFBFBD><D7AA>
	uint32_t ecc_hard;				//Ӳ<><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ECCֵ
	uint32_t ecc_hdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];//ECCӲ<43><D3B2><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>  	
	uint32_t ecc_rdbuf[NAND_MAX_PAGE_SIZE/NAND_ECC_SECTOR_SIZE];//ECC<43><43>ȡ<EFBFBD><C8A1>ֵ<EFBFBD><D6B5><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
}nand_attriute;      

extern nand_attriute nand_dev;				//nand<6E><64>Ҫ<EFBFBD><D2AA><EFBFBD><EFBFBD><EFBFBD>ṹ<EFBFBD><E1B9B9> 

//λ<><CEBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,ʵ<><CAB5>51<35><31><EFBFBD>Ƶ<EFBFBD>GPIO<49><4F><EFBFBD>ƹ<EFBFBD><C6B9><EFBFBD>
//<2F><><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5>˼<EFBFBD><CBBC>,<2C>ο<EFBFBD><<CM3Ȩ<33><C8A8>ָ<EFBFBD><D6B8>>><3E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(87ҳ~92ҳ).M4ͬM3<4D><33><EFBFBD><EFBFBD>,ֻ<>ǼĴ<C7BC><C4B4><EFBFBD><EFBFBD><EFBFBD>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>.
//IO<49>ڲ<EFBFBD><DAB2><EFBFBD><EFBFBD>궨<EFBFBD><EAB6A8>
#define GPIOD_IDR_Addr    (GPIOD_BASE+16) //0x40020C10 
#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2)) 
#define MEM_ADDR(addr)  *((volatile unsigned long  *)(addr)) 
#define BIT_ADDR(addr, bitnum)   MEM_ADDR(BITBAND(addr, bitnum)) 
#define PDin(n)    BIT_ADDR(GPIOD_IDR_Addr,n)  //<2F><><EFBFBD><EFBFBD> 

#define NAND_RB  				 PDin(6) 	//NAND Flash<73><68><EFBFBD><EFBFBD>/æ<><C3A6><EFBFBD><EFBFBD> 

#define NAND_ADDRESS			((rt_uint32_t)0x80000000)	//nand flash<73>ķ<EFBFBD><C4B7>ʵ<EFBFBD>ַ,<2C><>NCE3,<2C><>ַΪ:0X8000 0000
#define NAND_CMD				(uint32_t)(0x010000)		//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#define NAND_ADDR				(uint32_t)(0x020000)		//<2F><><EFBFBD>͵<EFBFBD>ַ


//*((volatile rt_uint8_t *) 0X80000000)
//*((volatile rt_uint8_t *) 0X80010000)
//*((volatile rt_uint8_t *) 0X80020000)


//NAND FLASH<53><48><EFBFBD><EFBFBD>
#define NAND_READID         	0X90    	//<2F><>IDָ<44><D6B8>
#define NAND_FEATURE			0XEF    	//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ָ<EFBFBD><D6B8>
#define NAND_RESET          	0XFF    	//<2F><>λNAND
#define NAND_READSTA        	0X70   	 	//<2F><>״̬
#define NAND_AREA_A         	0X00   
#define NAND_AREA_TRUE1     	0X30  
#define NAND_WRITE0        	 	0X80
#define NAND_WRITE_TURE1    	0X10
#define NAND_ERASE0        	 	0X60
#define NAND_ERASE1         	0XD0
#define NAND_MOVEDATA_CMD0  	0X00
#define NAND_MOVEDATA_CMD1  	0X35
#define NAND_MOVEDATA_CMD2  	0X85
#define NAND_MOVEDATA_CMD3  	0X10

//NAND FLASH״̬
#define NSTA_READY       	   	0X40		//nand<6E>Ѿ<EFBFBD>׼<EFBFBD><D7BC><EFBFBD><EFBFBD>
#define NSTA_ERROR				0X01		//nand<6E><64><EFBFBD><EFBFBD>
#define NSTA_TIMEOUT        	0X02		//<2F><>ʱ
#define NSTA_ECC1BITERR       	0X03		//ECC 1bit<69><74><EFBFBD><EFBFBD>
#define NSTA_ECC2BITERR       	0X04		//ECC 2bit<69><74><EFBFBD>ϴ<EFBFBD><CFB4><EFBFBD>


//NAND FLASH<53>ͺźͶ<C5BA>Ӧ<EFBFBD><D3A6>ID<49><44>
#define MT29F4G08ABADA			0XDC909556	//MT29F4G08ABADA
#define MT29F16G08ABABA			0X48002689	//MT29F16G08ABABA

 struct stm32f4_nand
{
    rt_uint8_t id[5];
    struct rt_mutex lock;
    struct rt_completion comp;
};


void NAND_Init(void);
uint8_t NAND_ModeSet(uint8_t mode);
uint32_t NAND_ReadID(void);
uint8_t NAND_ReadStatus(void);
uint8_t NAND_WaitForReady(void);
static rt_uint8_t nand_reset(void);
uint8_t NAND_WaitRB(__IO uint8_t rb);
void NAND_Delay(volatile rt_uint32_t i);
uint8_t NAND_ReadPage(uint32_t PageNum,uint16_t ColNum,uint8_t *pBuffer,uint16_t NumByteToRead);
uint8_t NAND_ReadPageComp(uint32_t PageNum,uint16_t ColNum,uint32_t CmpVal,uint16_t NumByteToRead,uint16_t *NumByteEqual);
uint8_t NAND_WritePage(uint32_t PageNum,uint16_t ColNum,uint8_t *pBuffer,uint16_t NumByteToWrite);
uint8_t NAND_WritePageConst(uint32_t PageNum,uint16_t ColNum,uint32_t cval,uint16_t NumByteToWrite);
uint8_t NAND_CopyPageWithoutWrite(uint32_t Source_PageNum,uint32_t Dest_PageNum);
uint8_t NAND_CopyPageWithWrite(uint32_t Source_PageNum,uint32_t Dest_PageNum,uint16_t ColNum,uint8_t *pBuffer,uint16_t NumByteToWrite);
uint8_t NAND_ReadSpare(uint32_t PageNum,uint16_t ColNum,uint8_t *pBuffer,uint16_t NumByteToRead);
uint8_t NAND_WriteSpare(uint32_t PageNum,uint16_t ColNum,uint8_t *pBuffer,uint16_t NumByteToRead);
uint8_t NAND_EraseBlock(uint32_t BlockNum);
void NAND_EraseChip(void);

uint16_t NAND_ECC_Get_OE(uint8_t oe,uint32_t eccval);
uint8_t NAND_ECC_Correction(uint8_t* data_buf,uint32_t eccrd,uint32_t ecccl);
int nand_hy27uf_hw_init(void);

#ifdef __cplusplus
}
#endif

#endif