512 lines
18 KiB
C
512 lines
18 KiB
C
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/*
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* File : x1000_cpm.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2017-02-03 Urey the first version
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*/
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#ifndef _X1000_CPM_H_
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#define _X1000_CPM_H_
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#define CPM_CPCCR (0x00)
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#define CPM_CPCSR (0xd4)
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#define CPM_DDRCDR (0x2c)
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#define CPM_I2SCDR (0x60)
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#define CPM_I2SCDR1 (0x70)
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#define CPM_LPCDR (0x64)
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#define CPM_MSC0CDR (0x68)
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#define CPM_MSC1CDR (0xa4)
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#define CPM_USBCDR (0x50)
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#define CPM_MACCDR (0x54)
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#define CPM_UHCCDR (0x6c)
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#define CPM_SFCCDR (0x74)
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#define CPM_CIMCDR (0x7c)
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#define CPM_PCMCDR (0x84)
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#define CPM_PCMCDR1 (0xe0)
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#define CPM_MPHYC (0xe8)
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#define CPM_INTR (0xb0)
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#define CPM_INTRE (0xb4)
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#define CPM_DRCG (0xd0)
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#define CPM_CPSPPR (0x38)
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#define CPM_CPPSR (0x34)
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#define CPM_USBPCR (0x3c)
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#define CPM_USBRDT (0x40)
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#define CPM_USBVBFIL (0x44)
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#define CPM_USBPCR1 (0x48)
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#define CPM_CPAPCR (0x10)
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#define CPM_CPMPCR (0x14)
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#define CPM_LCR (0x04)
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#define CPM_PSWC0ST (0x90)
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#define CPM_PSWC1ST (0x94)
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#define CPM_PSWC2ST (0x98)
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#define CPM_PSWC3ST (0x9c)
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#define CPM_CLKGR (0x20)
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#define CPM_CLKGR0 (0x20)
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#define CPM_MESTSEL (0xec)
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#define CPM_SRBC (0xc4)
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#define CPM_ERNG (0xd8)
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#define CPM_RNG (0xdc)
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#define CPM_SLBC (0xc8)
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#define CPM_SLPC (0xcc)
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#define CPM_OPCR (0x24)
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#define CPM_RSR (0x08)
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/*
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* CPM registers common define
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*/
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/* Clock control register(CPCCR) */
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#define CPCCR_SEL_SRC_LSB 30
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#define CPCCR_SEL_SRC_MASK BITS_H2L(31, CPCCR_SEL_SRC_LSB)
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#define CPCCR_SEL_CPLL_LSB 28
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#define CPCCR_SEL_CPLL_MASK BITS_H2L(29, CPCCR_SEL_CPLL_LSB)
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#define CPCCR_SEL_H0PLL_LSB 26
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#define CPCCR_SEL_H0PLL_MASK BITS_H2L(27, CPCCR_SEL_H0PLL_LSB)
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#define CPCCR_SEL_H2PLL_LSB 24
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#define CPCCR_SEL_H2PLL_MASK BITS_H2L(25, CPCCR_SEL_H2PLL_LSB)
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#define CPCCR_CE_CPU BIT22
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#define CPCCR_CE_AHB0 BIT21
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#define CPCCR_CE_AHB2 BIT20
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#define CPCCR_CE (CPCCR_CE_CPU | CPCCR_CE_AHB0 | CPCCR_CE_AHB2)
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#define CPCCR_PDIV_LSB 16
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#define CPCCR_PDIV_MASK BITS_H2L(19, CPCCR_PDIV_LSB)
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#define CPCCR_H2DIV_LSB 12
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#define CPCCR_H2DIV_MASK BITS_H2L(15, CPCCR_H2DIV_LSB)
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#define CPCCR_H0DIV_LSB 8
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#define CPCCR_H0DIV_MASK BITS_H2L(11, CPCCR_H0DIV_LSB)
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#define CPCCR_L2DIV_LSB 4
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#define CPCCR_L2DIV_MASK BITS_H2L(7, CPCCR_L2DIV_LSB)
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#define CPCCR_CDIV_LSB 0
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#define CPCCR_CDIV_MASK BITS_H2L(3, CPCCR_CDIV_LSB)
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#define CPM_SRC_SEL_APLL 1
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#define CPM_PLL_SEL_SRC 1
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#define CPM_PLL_SEL_MPLL 2
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/* Clock Status register(CPCSR) */
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#define CPCSR_SRC_MUX BIT31
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#define CPCSR_CPU_MUX BIT30
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#define CPCSR_AHB0_MUX BIT29
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#define CPCSR_AHB2_MUX BIT28
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#define CPCSR_DDR_MUX BIT27
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#define CPCSR_H2DIV_BUSY BIT2
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#define CPCSR_H0DIV_BUSY BIT1
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#define CPCSR_CDIV_BUSY BIT0
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#define CPCSR_DIV_BUSY (CPCSR_H2DIV_BUSY | CPCSR_H0DIV_BUSY | CPCSR_CDIV_BUSY)
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/* DDR clock divider register(DDCDR) */
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#define DDCDR_DCS_LSB 30
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#define DDCDR_DCS_MASK BITS_H2L(31, DDCDR_DCS_LSB)
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#define DDCDR_DCS_STOP (0 << DDCDR_DCS_LSB)
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#define DDCDR_DCS_APLL (1 << DDCDR_DCS_LSB)
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#define DDCDR_DCS_MPLL (2 << DDCDR_DCS_LSB)
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#define DDCDR_CE_DDR BIT29
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#define DDCDR_DDR_BUSY BIT28
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#define DDCDR_DDR_STOP BIT27
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#define DDCDR_GATE_EN BIT26
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#define DDCDR_DDR_CHANGE_EN BIT25
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#define DDCDR_DDR BIT24
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#define DDCDR_DDRDIV_LSB 0
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#define DDCDR_DDRDIV_MASK BITS_H2L(3, DDCDR_DDRDIV_LSB)
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/*MACPHY clock divider Register (MACCDR)*/
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#define MACCDR_MACPCS BIT31
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#define MACCDR_CE_MAC BIT29
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#define MACCDR_MAC_BUSY BIT28
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#define MACCDR_MAC_STOP BIT27
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#define MACCDR_MACCDR_LSB BIT0
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#define MACCDR_MACCDR_MASK BITS_H2L(7,MACCDR_MACCDR_LSB)
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/* I2S device clock divider register(I2SCDR) */
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#define I2SCDR_I2PCS BIT31
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#define I2SCDR_I2CS BIT30
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#define I2SCDR_I2SDIV_M_LSB 13
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#define I2SCDR_I2SDIV_M_MASK BITS_H2L(21,I2SCDR_I2SDIV_M_LSB)
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#define I2SCDR_I2SDIV_N_LSB 0 /* I2SCDR bit */
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#define I2SCDR_I2SDIV_N_MASK BITS_H2L(7, I2SCDR_I2SDIV_N_LSB)
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/* I2S device clock divider register(I2SCDR1) */
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#define I2SCDR1_NEN BIT31
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#define I2SCDR1_DEN BIT30
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#define I2SCDR1_I2SDIV_D_LSB 0
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#define I2SCDR1_I2SDIV_D_MASK BITS_H2L(12,I2SCDR1_I2SDIV_D_LSB)
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/* LCD pix clock divider register(LPCDR) */
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#define LPCDR_LPCS_LSB 31
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#define LPCDR_LPCS_APLL (0 << LPCDR_LPCS_LSB)
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#define LPCDR_LPCS_MPLL (1 << LPCDR_LPCS_LSB)
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#define LPCDR_CE_LCD BIT28
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#define LPCDR_LCD_BUSY BIT27
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#define LPCDR_LCD_STOP BIT26
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#define LPCDR_PIXDIV_LSB 0 /* LPCDR bit */
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#define LPCDR_PIXDIV_MASK BITS_H2L(7, LPCDR_PIXDIV_LSB)
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/* MSC clock divider register(MSCCDR) */
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#define MSCCDR_MPCS_LSB 31 /* MPCS bit */
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#define MSCCDR_MPCS_APLL (0 << MSCCDR_MPCS_LSB)
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#define MSCCDR_MPCS_MPLL (1 << MSCCDR_MPCS_LSB)
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#define MSCCDR_CE_MSC BIT29
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#define MSCCDR_MSC_BUSY BIT28
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#define MSCCDR_MSC_STOP BIT27
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#define MSCCDR_S_CLK0_SEL BIT15
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#define MSCCDR_MSCDIV_LSB 0 /* MSCCDR bit */
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#define MSCCDR_MSCDIV_MASK BITS_H2L(7, MSCCDR_MSCDIV_LSB)
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/* OTG PHY clock divider register(USBCDR) */
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#define USBCDR_UCS BIT31
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#define USBCDR_UPCS BIT30
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#define USBCDR_CE_USB BIT29
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#define USBCDR_USB_BUSY BIT28
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#define USBCDR_USB_STOP BIT27
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#define USBCDR_OTGDIV_LSB 0 /* USBCDR bit */
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#define USBCDR_OTGDIV_MASK BITS_H2L(7, USBCDR_OTGDIV_LSB)
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/* SSI clock divider register(SSICDR) */
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#define SSICDR_SPCS BIT31
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#define SSICDR_SCS BIT30
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#define SSICDR_CE_SSI BIT29
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#define SSICDR_SSI_BUSY BIT28
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#define SSICDR_SSI_STOP BIT27
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#define SSICDR_SSIDIV_LSB 0 /* SSICDR bit */
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#define SSICDR_SSIDIV_MASK BITS_H2L(7, SSICDR_SSIDIV_LSB)
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/* CIM mclk clock divider register(CIMCDR) */
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#define CIMCDR_CIMPCS_APLL (0 << 31)
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#define CIMCDR_CIMPCS_MPLL BIT31
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#define CIMCDR_CE_CIM BIT29
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#define CIMCDR_CIM_BUSY BIT28
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#define CIMCDR_CIM_STOP BIT27
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#define CIMCDR_CIMDIV_LSB 0 /* CIMCDR bit */
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#define CIMCDR_CIMDIV_MASK BITS_H2L(7, CIMCDR_CIMDIV_LSB)
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/* PCM device clock divider register(PCMCDR) */
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#define PCMCDR_PCMPCS_LSB 30
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#define PCMCDR_PCMPCS_MASK BITS_H2L(31,PCMCDR_PCMPCS_LSB)
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#define PCMCDR_PCMPCS_SCLK_A 0 << PCMCDR_PCMPCS_LSB
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#define PCMCDR_PCMPCS_EXTCLK 1 << PCMCDR_PCMPCS_LSB
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#define PCMCDR_PCMPCS_MPLL 2 << PCMCDR_PCMPCS_LSB
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#define PCMCDR_CE_PCM BIT29
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#define PCMCDR_PCMDIV_M_LSB 13
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#define PCMCDR_PCMDIV_M_MASK BITS_H2L(21,PCMCDR_PCMDIV_M_LSB)
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#define PCMCDR_PCMDIV_N_LSB 0
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#define PCMCDR_PCMDIV_N_MASK BITS_H2L(12,PCMCDR_PCMDIV_N_LSB)
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/* PCM device clock divider register(PCMCDR1) */
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#define PCMCDR1_PCM_NEN BIT31
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#define PCMCDR1_PCM_DEN BIT30
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#define PCMCDR1_PCMDIV_D_LSB 0
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#define PCMCDR1_PCMDIV_D_MASK BITS_H2L(12,PCMCDR1_PCMDIV_D_LSB)
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/* MAC PHY Control Register (MPHYC) */
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#define MPHYC_MODE_SEL BIT31 //useless now
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#define MPHYC_MAC_SPEED_LSB 29
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#define MPHYC_MAC_SPEED_MASK BITS_H2L(30,MPHYC_MAC_SPEED_LSB)
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#define MPHYC_SOFT_RST BIT3
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#define MPHYC_PHY_INTF_LSB 0
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#define MPHYC_PHY_INTF_MASK BITS_H2L(2,MPHYC_PHY_INTF_MASK) //useless now
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/* CPM Interrupt Register (CPM_INTR)*/
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#define CPM_INTR_VBUS_INTR BIT1
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#define CPM_INTR_ADEV_INTR BIT0
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/* CPM Interrupt Enable Register (CPM_INTRE)*/
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#define CPM_INTRE_VBUS_INTRE BIT1
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#define CPM_INTRE_ADEV_INTRE BIT0
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/* CPM scratch pad protected register(CPSPPR) */
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#define CPSPPR_CPSPR_WRITABLE (0x00005a5a)
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/* OTG parameter control register(USBPCR) */
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#define USBPCR_USB_MODE BIT31
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#define USBPCR_AVLD_REG BIT30
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#define USBPCR_INCRM BIT27 /* INCR_MASK bit */
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#define USBPCR_TXRISE_TUNE BIT26
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#define USBPCR_COMMONONN BIT25
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#define USBPCR_VBUSVLDEXT BIT24
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#define USBPCR_VBUSVLDEXTSEL BIT23
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#define USBPCR_POR BIT22
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#define USBPCR_SIDDQ BIT21
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#define USBPCR_OTG_DISABLE BIT20
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#define USBPCR_TXPREEMPHTUNE BIT6
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#define USBPCR_IDPULLUP_LSB 28 /* IDPULLUP_MASK bit */
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#define USBPCR_IDPULLUP_MASK BITS_H2L(29, USBPCR_IDPULLUP_LSB)
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#define USBPCR_COMPDISTUNE_LSB 17
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#define USBPCR_COMPDISTUNE_MASK BITS_H2L(19, USBPCR_COMPDISTUNE_LSB)
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#define USBPCR_OTGTUNE_LSB 14
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#define USBPCR_OTGTUNE_MASK BITS_H2L(16, USBPCR_OTGTUNE_LSB)
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#define USBPCR_SQRXTUNE_LSB 11
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#define USBPCR_SQRXTUNE_MASK BITS_H2L(13, USBPCR_SQRXTUNE_LSB)
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#define USBPCR_TXFSLSTUNE_LSB 7
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#define USBPCR_TXFSLSTUNE_MASK BITS_H2L(10, USBPCR_TXFSLSTUNE_LSB)
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#define USBPCR_TXRISETUNE_LSB 4
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#define USBPCR_TXRISETUNE_MASK BITS_H2L(5, USBPCR_TXRISETUNE_LSB)
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#define USBPCR_TXVREFTUNE_LSB 0
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#define USBPCR_TXVREFTUNE_MASK BITS_H2L(3, USBPCR_TXVREFTUNE_LSB)
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/* OTG reset detect timer register(USBRDT) */
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#define USBRDT_HB_MASK BIT26
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#define USBRDT_VBFIL_LD_EN BIT25
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#define USBRDT_IDDIG_EN BIT24
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#define USBRDT_IDDIG_REG BIT23
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#define USBRDT_USBRDT_LSB 0
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#define USBRDT_USBRDT_MASK BITS_H2L(22, USBRDT_USBRDT_LSB)
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/* OTG parameter control register(USBPCR1) */
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#define USBPCR1_REG BIT31
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#define USBPCR1_USB_SEL BIT28
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#define USBPCR1_REFCLKSEL_LSB 26
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#define USBPCR1_REFCLKSEL_MASK BITS_H2L(27, USBPCR1_REFCLKSEL_LSB)
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#define USBPCR1_REFCLKDIV_LSB 24
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#define USBPCR1_REFCLKDIV_MASK BITS_H2L(25, USBPCR1_REFCLKDIV_LSB)
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#define USBPCR1_PORT_RST BIT21
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#define USBPCR1_WORD_IF0 BIT19
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#define USBPCR1_WORD_IF1 BIT18
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/* APLL control register (CPXPCR) */
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#define CPAPCR_BS BIT31
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#define CPAPCR_M_LSB 24
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#define CPAPCR_M_MASK BITS_H2L(30, CPAPCR_M_LSB)
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#define CPAPCR_N_LSB 18
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#define CPAPCR_N_MASK BITS_H2L(22, CPAPCR_N_LSB)
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#define CPAPCR_OD_LSB 16
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#define CPAPCR_OD_MASK BITS_H2L(17, CPAPCR_OD_LSB)
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#define CPAPCR_LOCK BIT15 /* LOCK bit */
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#define CPAPCR_ON BIT10
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#define CPAPCR_BP BIT9
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#define CPAPCR_EN BIT8
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#define CPAPCR_PLLST_LSB 0
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#define CPAPCR_PLLST_MASK BITS_H2L(7,CPAPCR_PLLST_LSB)
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#define CPM_CPAPCR_EN CPAPCR_EN
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#define CPM_CPAPCR_ON CPAPCR_ON
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/* MPLL control register (CPXPCR) */
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#define CPMPCR_BS BIT31
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#define CPMPCR_M_LSB 24
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#define CPMPCR_M_MASK BITS_H2L(30, CPAPCR_M_LSB)
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#define CPMPCR_N_LSB 18
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#define CPMPCR_N_MASK BITS_H2L(22, CPAPCR_N_LSB)
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#define CPMPCR_OD_LSB 16
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#define CPMPCR_OD_MASK BITS_H2L(17, CPAPCR_OD_LSB)
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#define CPMPCR_EN BIT7
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#define CPMPCR_BP BIT6
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#define CPMPCR_LOCK BIT1 /* LOCK bit */
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#define CPMPCR_ON BIT0
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#define CPM_CPMPCR_EN CPMPCR_EN
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#define CPM_CPMPCR_ON CPMPCR_ON
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/* Low power control register(LCR) */
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#define LCR_PST_LSB 8
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#define LCD_PST_MASK BITS_H2L(19,LCR_PST_LSB)
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#define LCR_LPM_LSB 0
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#define LCR_LPM_MASK BITS_H2L(1,LCR_LPM_LSB)
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/* Clock gate register 0(CGR0) */
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#define CLKGR0_DDR BIT31
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#define CLKGR0_CPU BIT30
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#define CLKGR0_AHB0 BIT29
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#define CLKGR0_APB0 BIT28
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#define CLKGR0_RTC BIT27
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#define CLKGR0_PCM BIT26
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#define CLKGR0_MAC BIT25
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#define CLKGR0_AES BIT24
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#define CLKGR0_LCD BIT23
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#define CLKGR0_CIM BIT22
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#define CLKGR0_PDMA BIT21
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#define CLKGR0_OST BIT20
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#define CLKGR0_SSI BIT19
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#define CLKGR0_TCU BIT18
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#define CLKGR0_DMIC BIT17
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#define CLKGR0_UART2 BIT16
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#define CLKGR0_UART1 BIT15
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#define CLKGR0_UART0 BIT14
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#define CLKGR0_SADC BIT13
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#define CLKGR0_JPEG BIT12
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#define CLKGR0_AIC BIT11
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#define CLKGR0_I2C3 BIT10
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#define CLKGR0_I2C2 BIT9
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#define CLKGR0_I2C1 BIT8
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#define CLKGR0_I2C0 BIT7
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#define CLKGR0_SCC BIT6
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#define CLKGR0_MSC1 BIT5
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#define CLKGR0_MSC0 BIT4
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#define CLKGR0_OTG BIT3
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#define CLKGR0_SFC BIT2
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#define CLKGR0_EFUSE BIT1
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#define CLKGR0_NEMC BIT0
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/* CPM MEST SEL Register */
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#define MEST_SEL_TST8 BIT8
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#define MEST_SEL_TST7 BIT7
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#define MEST_SEL_TST4 BIT4
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#define MEST_SEL_TST3 BIT3
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#define MEST_SEL_TST1 BIT1
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#define MEST_SEL_TST0 BIT0
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/*Soft Reset and Bus Control Register (SRBC)*/
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#define SRBC_JPEG_SR BIT31
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#define SRBC_JPEG_STP BIT30
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#define SRBC_JPEG_ACK BIT29
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#define SRBC_LCD_SR BIT25
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#define SRBC_LCD_STP BIT24
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#define SRBC_LCD_ACK BIT23
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#define SRBC_CIM_STP BIT21
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#define SRBC_CIM_ACK BIT20
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#define SRBC_CPU_STP BIT15
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#define SRBC_CPU_ACK BIT14
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#define SRBC_OTG_SR BIT12
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#define SRBC_AHB2_STP BIT8
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#define SRBC_AHB2_ACK BIT7
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#define SRBC_DDR_STP BIT6
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#define SRBC_DDR_ACK BIT5
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/* Oscillator and power control register(OPCR) */
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#define OPCR_IDLE_DIS BIT31
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#define OPCR_MASK_INT BIT30
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#define OPCR_MASK_VPU BIT29 //ONLY FOR DEBUG
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#define OPCR_GATE_SCLK_ABUS BIT28
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#define OPCR_L2C_PD BIT25
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#define OPCR_REQ_MODE BIT24
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#define OPCR_GATE_USBPHY_CLK BIT23
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#define OPCR_DIS_STOP_MUX BIT22
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#define OPCR_O1ST_LSB 8
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#define OPCR_O1ST_MASK BITS_H2L(19, OPCR_O1ST_LSB)
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#define OPCR_OTGPHY0_ENABLE BIT7 /* otg */
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#define OPCR_OTGPHY1_ENABLE BIT6 /* uhc */
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#define OPCR_USBPHY_ENABLE (OPCR_OTGPHY0_ENABLE | OPCR_OTGPHY1_ENABLE)
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#define OPCR_O1SE BIT4
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#define OPCR_PD BIT3
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#define OPCR_ERCS BIT2
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#define OPCR_BUSMODE BIT1
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/* Reset status register(RSR) */
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#define RSR_HR BIT3
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#define RSR_P0R BIT2
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#define RSR_WR BIT1
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#define RSR_PR BIT0
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#ifndef __ASSEMBLY__
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#define REG_CPM_CPCCR REG32(CPM_BASE + CPM_CPCCR)
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#define REG_CPM_CPCSR REG32(CPM_BASE + CPM_CPCSR)
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#define REG_CPM_DDCDR REG32(CPM_BASE + CPM_DDCDR)
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#define REG_CPM_MACCDR REG32(CPM_BASE + CPM_MACCDR)
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#define REG_CPM_I2SCDR REG32(CPM_BASE + CPM_I2SCDR)
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#define REG_CPM_I2SCDR1 REG32(CPM_BASE + CPM_I2SCDR1)
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#define REG_CPM_LPCDR REG32(CPM_BASE + CPM_LPCDR)
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#define REG_CPM_MSC0CDR REG32(CPM_BASE + CPM_MSC0CDR)
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#define REG_CPM_MSC1CDR REG32(CPM_BASE + CPM_MSC1CDR)
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#define REG_CPM_USBCDR REG32(CPM_BASE + CPM_USBCDR)
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#define REG_CPM_SSICDR REG32(CPM_BASE + CPM_SSICDR)
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#define REG_CPM_CIMCDR REG32(CPM_BASE + CPM_CIMCDR)
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#define REG_CPM_PCMCDR REG32(CPM_BASE + CPM_PCMCDR)
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#define REG_CPM_PCMCDR1 REG32(CPM_BASE + CPM_PCMCDR1)
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#define REG_CPM_MPHYC REG32(CPM_BASE + CPM_MPHYC)
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#define REG_CPM_INTRCDR REG32(CPM_BASE + CPM_INTRCDR)
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#define REG_CPM_INTRECDR REG32(CPM_BASE + CPM_INTRECDR)
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#define REG_CPM_CPSPR REG32(CPM_BASE + CPM_CPSPR)
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#define REG_CPM_CPSPPR REG32(CPM_BASE + CPM_CPSPPR)
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#define REG_CPM_USBPCR REG32(CPM_BASE + CPM_USBPCR)
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#define REG_CPM_USBRDT REG32(CPM_BASE + CPM_USBRDT)
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#define REG_CPM_USBVBFIL REG32(CPM_BASE + CPM_USBVBFIL)
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#define REG_CPM_USBPCR1 REG32(CPM_BASE + CPM_USBPCR1)
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#define REG_CPM_CPAPCR REG32(CPM_BASE + CPM_CPAPCR)
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#define REG_CPM_CPMPCR REG32(CPM_BASE + CPM_CPMPCR)
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#define REG_CPM_LCR REG32(CPM_BASE + CPM_LCR)
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#define REG_CPM_PSWC0ST REG32(CPM_BASE + CPM_PSWC0ST)
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#define REG_CPM_PSWC1ST REG32(CPM_BASE + CPM_PSWC1ST)
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#define REG_CPM_PSWC2ST REG32(CPM_BASE + CPM_PSWC2ST)
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#define REG_CPM_PSWC3ST REG32(CPM_BASE + CPM_PSWC3ST)
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#define REG_CPM_CLKGR0 REG32(CPM_BASE + CPM_CLKGR0)
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#define REG_CPM_SRBC REG32(CPM_BASE + CPM_SRBC)
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#define REG_CPM_SLBC REG32(CPM_BASE + CPM_SLBC)
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#define REG_CPM_SLPC REG32(CPM_BASE + CPM_SLPC)
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#define REG_CPM_OPCR REG32(CPM_BASE + CPM_OPCR)
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#define REG_CPM_RSR REG32(CPM_BASE + CPM_RSR)
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|
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#define _REG_CPM_MSCCDR(n) REG_CPM_MSC##n##CDR
|
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|
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#define REG_CPM_MSCCDR(n) _REG_CPM_MSCCDR(n)
|
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|
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|
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|
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/* CPM read write */
|
||
|
|
#define cpm_inl(off) readl(CPM_BASE + off)
|
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|
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#define cpm_outl(val,off) writel(val, CPM_BASE + off)
|
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#define cpm_test_bit(bit,off) (cpm_inl(off) & 0x1<<(bit))
|
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#define cpm_set_bit(bit,off) (cpm_outl((cpm_inl(off) | 0x1<<(bit)),off))
|
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|
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#define cpm_clear_bit(bit,off) (cpm_outl(cpm_inl(off) & ~(0x1 << bit), off))
|
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#endif /* __ASSEMBLY__ */
|
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#endif /* _X1000_CPM_H_ */
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