342 lines
10 KiB
C
342 lines
10 KiB
C
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/**
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* \file
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*
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* \brief PLL management
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*
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* Copyright (c) 2010-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef CLK_PLL_H_INCLUDED
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#define CLK_PLL_H_INCLUDED
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#include "parts.h"
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#include "conf_clock.h"
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#if SAM3S
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# include "sam3s/pll.h"
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#elif SAM3XA
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# include "sam3x/pll.h"
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#elif SAM3U
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# include "sam3u/pll.h"
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#elif SAM3N
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# include "sam3n/pll.h"
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#elif SAM4S
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# include "sam4s/pll.h"
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#elif SAM4E
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# include "sam4e/pll.h"
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#elif SAM4C
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# include "sam4c/pll.h"
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#elif SAM4CM
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# include "sam4cm/pll.h"
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#elif SAM4CP
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# include "sam4cp/pll.h"
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#elif SAM4L
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# include "sam4l/pll.h"
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#elif SAM4N
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# include "sam4n/pll.h"
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#elif SAMG
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# include "samg/pll.h"
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#elif SAMV71
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# include "samv71/pll.h"
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#elif SAMV70
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# include "samv70/pll.h"
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#elif SAME70
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# include "same70/pll.h"
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#elif SAMS70
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# include "sams70/pll.h"
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#elif (UC3A0 || UC3A1)
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# include "uc3a0_a1/pll.h"
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#elif UC3A3
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# include "uc3a3_a4/pll.h"
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#elif UC3B
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# include "uc3b0_b1/pll.h"
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#elif UC3C
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# include "uc3c/pll.h"
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#elif UC3D
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# include "uc3d/pll.h"
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#elif (UC3L0128 || UC3L0256 || UC3L3_L4)
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# include "uc3l/pll.h"
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#elif XMEGA
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# include "xmega/pll.h"
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#else
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# error Unsupported chip type
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#endif
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/**
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* \ingroup clk_group
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* \defgroup pll_group PLL Management
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*
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* This group contains functions and definitions related to configuring
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* and enabling/disabling on-chip PLLs. A PLL will take an input signal
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* (the \em source), optionally divide the frequency by a configurable
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* \em divider, and then multiply the frequency by a configurable \em
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* multiplier.
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*
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* Some devices don't support input dividers; specifying any other
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* divisor than 1 on these devices will result in an assertion failure.
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* Other devices may have various restrictions to the frequency range of
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* the input and output signals.
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*
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* \par Example: Setting up PLL0 with default parameters
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*
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* The following example shows how to configure and enable PLL0 using
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* the default parameters specified using the configuration symbols
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* listed above.
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* \code
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pll_enable_config_defaults(0); \endcode
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*
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* To configure, enable PLL0 using the default parameters and to disable
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* a specific feature like Wide Bandwidth Mode (a UC3A3-specific
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* PLL option.), you can use this initialization process.
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* \code
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struct pll_config pllcfg;
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if (pll_is_locked(pll_id)) {
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return; // Pll already running
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}
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pll_enable_source(CONFIG_PLL0_SOURCE);
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pll_config_defaults(&pllcfg, 0);
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pll_config_set_option(&pllcfg, PLL_OPT_WBM_DISABLE);
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pll_enable(&pllcfg, 0);
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pll_wait_for_lock(0); \endcode
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*
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* When the last function call returns, PLL0 is ready to be used as the
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* main system clock source.
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*
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* \section pll_group_config Configuration Symbols
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*
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* Each PLL has a set of default parameters determined by the following
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* configuration symbols in the application's configuration file:
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* - \b CONFIG_PLLn_SOURCE: The default clock source connected to the
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* input of PLL \a n. Must be one of the values defined by the
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* #pll_source enum.
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* - \b CONFIG_PLLn_MUL: The default multiplier (loop divider) of PLL
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* \a n.
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* - \b CONFIG_PLLn_DIV: The default input divider of PLL \a n.
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*
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* These configuration symbols determine the result of calling
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* pll_config_defaults() and pll_get_default_rate().
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*
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* @{
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*/
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//! \name Chip-specific PLL characteristics
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//@{
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/**
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* \def PLL_MAX_STARTUP_CYCLES
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* \brief Maximum PLL startup time in number of slow clock cycles
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*/
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/**
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* \def NR_PLLS
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* \brief Number of on-chip PLLs
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*/
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/**
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* \def PLL_MIN_HZ
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* \brief Minimum frequency that the PLL can generate
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*/
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/**
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* \def PLL_MAX_HZ
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* \brief Maximum frequency that the PLL can generate
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*/
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/**
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* \def PLL_NR_OPTIONS
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* \brief Number of PLL option bits
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*/
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//@}
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/**
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* \enum pll_source
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* \brief PLL clock source
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*/
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//! \name PLL configuration
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//@{
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/**
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* \struct pll_config
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* \brief Hardware-specific representation of PLL configuration.
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*
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* This structure contains one or more device-specific values
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* representing the current PLL configuration. The contents of this
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* structure is typically different from platform to platform, and the
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* user should not access any fields except through the PLL
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* configuration API.
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*/
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/**
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* \fn void pll_config_init(struct pll_config *cfg,
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* enum pll_source src, unsigned int div, unsigned int mul)
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* \brief Initialize PLL configuration from standard parameters.
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*
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* \note This function may be defined inline because it is assumed to be
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* called very few times, and usually with constant parameters. Inlining
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* it will in such cases reduce the code size significantly.
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*
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* \param cfg The PLL configuration to be initialized.
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* \param src The oscillator to be used as input to the PLL.
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* \param div PLL input divider.
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* \param mul PLL loop divider (i.e. multiplier).
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*
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* \return A configuration which will make the PLL run at
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* (\a mul / \a div) times the frequency of \a src
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*/
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/**
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* \def pll_config_defaults(cfg, pll_id)
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* \brief Initialize PLL configuration using default parameters.
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*
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* After this function returns, \a cfg will contain a configuration
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* which will make the PLL run at (CONFIG_PLLx_MUL / CONFIG_PLLx_DIV)
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* times the frequency of CONFIG_PLLx_SOURCE.
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*
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* \param cfg The PLL configuration to be initialized.
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* \param pll_id Use defaults for this PLL.
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*/
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/**
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* \def pll_get_default_rate(pll_id)
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* \brief Get the default rate in Hz of \a pll_id
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*/
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/**
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* \fn void pll_config_set_option(struct pll_config *cfg,
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* unsigned int option)
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* \brief Set the PLL option bit \a option in the configuration \a cfg.
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*
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* \param cfg The PLL configuration to be changed.
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* \param option The PLL option bit to be set.
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*/
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/**
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* \fn void pll_config_clear_option(struct pll_config *cfg,
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* unsigned int option)
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* \brief Clear the PLL option bit \a option in the configuration \a cfg.
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*
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* \param cfg The PLL configuration to be changed.
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* \param option The PLL option bit to be cleared.
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*/
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/**
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* \fn void pll_config_read(struct pll_config *cfg, unsigned int pll_id)
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* \brief Read the currently active configuration of \a pll_id.
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*
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* \param cfg The configuration object into which to store the currently
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* active configuration.
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* \param pll_id The ID of the PLL to be accessed.
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*/
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/**
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* \fn void pll_config_write(const struct pll_config *cfg,
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* unsigned int pll_id)
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* \brief Activate the configuration \a cfg on \a pll_id
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*
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* \param cfg The configuration object representing the PLL
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* configuration to be activated.
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* \param pll_id The ID of the PLL to be updated.
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*/
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//@}
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//! \name Interaction with the PLL hardware
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//@{
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/**
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* \fn void pll_enable(const struct pll_config *cfg,
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* unsigned int pll_id)
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* \brief Activate the configuration \a cfg and enable PLL \a pll_id.
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*
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* \param cfg The PLL configuration to be activated.
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* \param pll_id The ID of the PLL to be enabled.
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*/
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/**
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* \fn void pll_disable(unsigned int pll_id)
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* \brief Disable the PLL identified by \a pll_id.
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*
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* After this function is called, the PLL identified by \a pll_id will
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* be disabled. The PLL configuration stored in hardware may be affected
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* by this, so if the caller needs to restore the same configuration
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* later, it should either do a pll_config_read() before disabling the
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* PLL, or remember the last configuration written to the PLL.
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*
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* \param pll_id The ID of the PLL to be disabled.
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*/
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/**
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* \fn bool pll_is_locked(unsigned int pll_id)
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* \brief Determine whether the PLL is locked or not.
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*
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* \param pll_id The ID of the PLL to check.
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*
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* \retval true The PLL is locked and ready to use as a clock source
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* \retval false The PLL is not yet locked, or has not been enabled.
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*/
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/**
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* \fn void pll_enable_source(enum pll_source src)
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* \brief Enable the source of the pll.
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* The source is enabled, if the source is not already running.
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*
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* \param src The ID of the PLL source to enable.
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*/
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/**
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* \fn void pll_enable_config_defaults(unsigned int pll_id)
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* \brief Enable the pll with the default configuration.
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* PLL is enabled, if the PLL is not already locked.
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*
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* \param pll_id The ID of the PLL to enable.
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*/
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/**
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* \brief Wait for PLL \a pll_id to become locked
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*
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* \todo Use a timeout to avoid waiting forever and hanging the system
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*
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* \param pll_id The ID of the PLL to wait for.
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*
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* \retval STATUS_OK The PLL is now locked.
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* \retval ERR_TIMEOUT Timed out waiting for PLL to become locked.
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*/
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static inline int pll_wait_for_lock(unsigned int pll_id)
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{
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Assert(pll_id < NR_PLLS);
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while (!pll_is_locked(pll_id)) {
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/* Do nothing */
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}
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return 0;
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}
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//@}
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//! @}
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#endif /* CLK_PLL_H_INCLUDED */
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