457 lines
13 KiB
C
457 lines
13 KiB
C
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/*****************************************************************************
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*
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* Copyright Andes Technology Corporation 2007-2008
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* All Rights Reserved.
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*
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* Revision History:
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*
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* Mar.16.2008 Created.
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****************************************************************************/
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#include "hal.h"
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#include "sspd_rts.h"
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#include "bsp_hal.h"
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#define RTS_PRESSED_Z1_MIN 0x10
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#define RTS_PRESSED_Z2_MAX 0xfe0
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typedef struct _SSPD_RTS_CONTEXT{
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hal_bh_t hisr;
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hal_semaphore_t *usr_ievent;
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struct ts_data *usr_idata;
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} SSPD_RTS_CONTEXT;
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SSPD_RTS_CONTEXT rts_ctxt;
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#define SSPD_HISR_STACK_SIZE 1024
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static uint32_t sspd_rts_hisr_stack[SSPD_HISR_STACK_SIZE];
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static void _sspd_rts_lisr(int vector){
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int x = 0, y = 0, z1 = 0, z2 = 0, p = 0;
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DEBUG(0, 1, "Enter\n");
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if (vector != RTS_LISR_VECTOR)
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hal_system_error(HAL_ERR_UNHANDLED_INTERRUPT);
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/* Disable #PENIRQ interrupt */
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uint32_t prv_msk = hal_intc_irq_mask(RTS_LISR_VECTOR);
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/* Clear #PENIRQ interrupt status */
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hal_intc_irq_clean(RTS_LISR_VECTOR);
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/* Enable higher priority interrupt */
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GIE_ENABLE();
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//FIXME
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#if 0
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#if(NO_EXTERNAL_INT_CTL==0)
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/* Disable #PENIRQ interrupt temporarily */
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CLRB32(INTC_HW1_ER, RTS_LISR_VECTOR);
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/* Clear #PENIRQ interrupt status */
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SETB32(INTC_HW1_CLR, RTS_LISR_VECTOR);
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#else
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/* FIXME add clear ts interrupt */
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#endif
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#endif
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_sspd_rts_probe(&x, &y, &z1, &z2, &p);
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_sspd_rts_probe(&x, &y, &z1, &z2, &p);
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_sspd_rts_probe(&x, &y, &z1, &z2, &p);
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rts_ctxt.usr_idata->x = x;
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rts_ctxt.usr_idata->y = y;
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rts_ctxt.usr_idata->z1 = z1;
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rts_ctxt.usr_idata->z2 = z2;
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DEBUG(0, 1, "%4d, %4d, %4d, %4d\n", x, y, z1, z2);
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if (z1 < 100) {
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/* Disable GIE to prevent nested self */
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GIE_DISABLE();
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/*
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* Clear #PENIRQ interrupt status again because _sspd_rts_probe would trigger #PENIRQ interrupt
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* Please reference ADS7846 Spec.
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*/
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hal_intc_irq_clean(RTS_LISR_VECTOR);
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/* Re-enable touch interrupt */
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hal_intc_irq_unmask(prv_msk);
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return;
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}
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hal_raise_bh(&rts_ctxt.hisr);
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// TODO
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// It is a walk around since interrupt priority
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// we should change the hisr
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hal_intc_irq_unmask(prv_msk);
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hal_intc_irq_disable(RTS_LISR_VECTOR);
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}
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static inline void ts_hisr(void *param){
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hal_bh_t *bh = param;
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while (1){
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DEBUG(0, 1, "before\n");
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hal_pend_semaphore(&bh->sem, HAL_SUSPEND);
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DEBUG(0, 1, "after\n");
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hal_post_semaphore(rts_ctxt.usr_ievent);
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#ifndef CONFIG_PLAT_QEMU
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hal_sleep(300);
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#endif
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hal_intc_irq_clean(RTS_LISR_VECTOR);
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HAL_INTC_IRQ_ATOMIC_ENABLE(RTS_LISR_VECTOR);
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// SETB32(INTC_HW1_ER, RTS_LISR_VECTOR);
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// SETB32(INTC_HW1_CLR, RTS_LISR_VECTOR);
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}
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}
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static void _sspd_rts_set_sclk(int sclk){
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int sclk_div; /* serial clock rate divisor */
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if (sclk > RTS_ADS7846_DCLK_MAX){
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DEBUG(1, 1, "Warning : SCLK exceed allowable range! Truncation is performed.\n");
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sclk = RTS_ADS7846_DCLK_MAX;
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}
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/*
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* sclk source:
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* PLL3 (SSPCLK = PLL3/6) AG101 internal clk
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* GPIO25 (SSPCLK = GPIO25) AG101 external clk
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* OSCCLK (SSPCLK = OSCCLK * 6 / 6) Leopard
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*
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* calculate sclk_div from internal PLL3
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*
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* sclk_div = (SSPCLK / sclk / 2) - 1
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* = ((PLL3 / 6) / sclk / 2) - 1
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* = ((OSCCLK * 30 / 6) / sclk / 2) - 1
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*/
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/*
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* setup PMU SSP clock source
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*
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* PMU_SSPCLKSEL: MFPSR[6]
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* 0: SSPCLK
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* 1: GPIO25
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*
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* PMU_AC97CLKOUTSEL: MFPSR[13]
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* 0: GPIO
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* 1: AC97CLK out
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*/
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/* [2008-03-20] SSP1 only works with internal clock source on AG101 and Leopard EVBs. */
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#if 0 /*(MB_SSP_EXT_CLK) */
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sclk_div = (24768000 / (sclk << 1)) - 1;
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SSPD_TRACE(("\nSSPCLK: GPIO25\n"));
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SETB32(PMU_MFPSR, PMU_SSPCLKSEL_BIT);
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#else
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sclk_div = (MB_OSCCLK / (2 * sclk)) - 1;
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DEBUG(1, 1, "SSPCLK: PLL\n");
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CLRB32(PMU_MFPSR, PMU_SSPCLKSEL_BIT);
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#endif
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DEBUG(1, 1, "sclk : %d, sclk_div : 0x%04x\n", sclk, sclk_div);
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/*
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* setup SSP SCLKDIV
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* PDL : (padding data length) not used
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* SDL : (serial data length) 8-1 (8 bits)
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* SCLKDIV : sclk_div
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*/
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#ifndef CONFIG_PLAT_QEMU
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OUT32(SSPC_CR1, ((7 << SSPC_C1_SDL_SHIFT) & SSPC_C1_SDL_MASK) | /* bit data length */
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((sclk_div << SSPC_C1_SCLKDIV_SHIFT) & SSPC_C1_SCLKDIV_MASK)); /* sclkdiv */
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#else
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OUT32(SSPC_CR1, ((23 << SSPC_C1_SDL_SHIFT) & SSPC_C1_SDL_MASK) | /* bit data length */
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((sclk_div << SSPC_C1_SCLKDIV_SHIFT) & SSPC_C1_SCLKDIV_MASK)); /* sclkdiv */
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#endif
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}
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int _sspd_rts_init(struct ts_dev *ts){
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int status = HAL_SUCCESS;
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int core_intl;
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core_intl = hal_global_int_ctl(HAL_DISABLE_INTERRUPTS);
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/* SSP controler initialization - SPI */
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/* Disable all SSP interrupts, and set DMA trigger FIFO threshold to 0. */
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OUT32(SSPC_INTCR, 0);
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/* check ts interrupt vector*/
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if (ts->penirq){
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status = hal_register_isr(RTS_LISR_VECTOR, _sspd_rts_lisr, (void*)0);
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if (status != HAL_SUCCESS){
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DEBUG(1, 1, "Failed to register SSPD driver LISR!\n");
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return status;
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}
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rts_ctxt.usr_ievent = ts->event_obj;
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rts_ctxt.usr_idata = ts->event_data;
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rts_ctxt.hisr.th.fn = ts_hisr;
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rts_ctxt.hisr.th.ptos = &sspd_rts_hisr_stack[SSPD_HISR_STACK_SIZE];
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rts_ctxt.hisr.th.stack_size = sizeof(sspd_rts_hisr_stack);
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rts_ctxt.hisr.th.prio = CONFIG_TSD_HISR_PRIORITY;
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rts_ctxt.hisr.th.name = "TS BH";
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rts_ctxt.hisr.th.arg = &rts_ctxt.hisr;
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status = hal_create_bh(&rts_ctxt.hisr);
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if (status != HAL_SUCCESS){
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DEBUG(1, 1, "Failed to create SSPD-RTS driver HISR!\n");
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return status;
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}
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/* INTC */
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/* - Disable #PENIRQ interrupt */
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hal_intc_irq_disable(RTS_LISR_VECTOR);
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/* - Clear #PENIRQ interrupt status */
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hal_intc_irq_clean(RTS_LISR_VECTOR);
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/* - Setup #PENIRQ interrupt trigger mode - edge trigger */
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/* - Setup #PENIRQ interrupt trigger level - assert low */
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hal_intc_irq_config(RTS_LISR_VECTOR, IRQ_EDGE_TRIGGER, IRQ_ACTIVE_LOW);
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if (ts->penirq_en){
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/* - Enable #PENIRQ interrupt */
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hal_intc_irq_enable(RTS_LISR_VECTOR);
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}
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}
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/* Reset SSP controller */
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SETB32(SSPC_CR2, SSPC_C2_SSPRST_BIT);
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/* Disable SSP data out */
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CLRR32(SSPC_CR2, SSPC_C2_SSPEN_MASK | SSPC_C2_TXDOE_MASK);
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/* setup sspc clock */
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_sspd_rts_set_sclk(RTS_ADS7846_DCLK_DEFAULT);
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_nds_kwait(RTS_RESET_WAIT);
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/* Set SSP frame format to SPI */
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OUT32(SSPC_CR0, ((0 << SSPC_C0_SCLKPH_BIT) & SSPC_C0_SCLKPH_MASK) | /* phase (1 not working for 16clk mode) */
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((0 << SSPC_C0_SCLKPO_BIT) & SSPC_C0_SCLKPO_MASK) | /* polarity */
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((SSPC_SSP_MASTER << SSPC_C0_OPM_SHIFT) & SSPC_C0_OPM_MASK) | /* operation mode */
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((0 << SSPC_C0_LBM_BIT) & SSPC_C0_LBM_MASK) | /* loopback */
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((SSPC_MOTO_SPI << SSPC_C0_FFMT_SHIFT) & SSPC_C0_FFMT_MASK)); /* frame format */
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/* Clear FIFO garbage */
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SETR32(SSPC_CR2, SSPC_C2_RXFCLR_MASK | SSPC_C2_TXFCLR_MASK);
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/* Restore CPU interrupt controller to previous level */
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hal_global_int_ctl(core_intl);
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return status;
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}
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int _sspd_rts_probe(int *x, int *y, int *z1, int *z2, int *pressed){
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uint32_t data[12];
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int t, i;
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/* Clear FIFO garbage */
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SETR32(SSPC_CR2, SSPC_C2_RXFCLR_MASK | SSPC_C2_TXFCLR_MASK);
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/* Enable SSP */
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SETB32(SSPC_CR2, SSPC_C2_SSPEN_BIT);
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/* Disable SSP data out temporarily */
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CLRB32(SSPC_CR2, SSPC_C2_TXDOE_BIT);
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/* [hw-limit] Wait until the ssp controller get ready */
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// _nds_kwait(RTS_DIN_WAIT);
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t = 0;
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while (((IN32(SSPC_SR) & SSPC_SR_BUSY_MASK) != 0) && (t++ < RTS_DIN_TIMEOUT))
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;
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DEBUG(0, 1, "[RTS] SR : 0x%08lx\n", IN32(SSPC_SR));
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/*
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* ------------------------------------------------------------------------
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* Timing of 16-clock-cycle per conversion
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*
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* power-up read y read x power down (full cycle)
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* --------- --------- --------- ---------------
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* dout (bytes) ctrl 0 ctrl 0 ctrl 0 ctrl 0 0 ____
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* din (bytes) 0 msb lsb msb lsb msb lsb msb lsb ____
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* ^^^^ ^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^^ ^^^^^^^^
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* don't care x1 or y1 x2 or y2 don't care
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*
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* x = (x1 + x2) / 2 (if averaging was expected)
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* y = (y1 + y2) / 2 (if averaging was expected)
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*
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* Note: Watch out SSP FIFO depth (12 for AG101/Leopard)
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* ------------------------------------------------------------------------
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*/
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/* SPI dout ... */
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#ifndef CONFIG_PLAT_QEMU
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/* power up */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RY);
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OUT32(SSPC_DR, 0);
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/* read y */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RY);
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OUT32(SSPC_DR, 0);
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/* read x */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RX);
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OUT32(SSPC_DR, 0);
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/* read z1 */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RZ1);
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OUT32(SSPC_DR, 0);
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/* read z2 && power down */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RZ2_PD);
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OUT32(SSPC_DR, 0);
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OUT32(SSPC_DR, 0);
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#else
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/* power up */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RY << 16);
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OUT32(SSPC_DR, 0);
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/* read y */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RY << 16);
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OUT32(SSPC_DR, 0);
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/* read x */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RX << 16);
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OUT32(SSPC_DR, 0);
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/* read z1 */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RZ1 << 16);
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OUT32(SSPC_DR, 0);
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/* read z2 && power down */
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OUT32(SSPC_DR, RTS_ADS7846_CTL_RZ2_PD << 16);
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OUT32(SSPC_DR, 0);
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OUT32(SSPC_DR, 0);
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#endif
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|
|
/* Enable SSP-TX out */
|
||
|
|
SETB32(SSPC_CR2, SSPC_C2_TXDOE_BIT);
|
||
|
|
|
||
|
|
/* SPI din ... */
|
||
|
|
for (i = 0; i < 11; ++i){
|
||
|
|
|
||
|
|
/* Wait until data ready */
|
||
|
|
t = 0;
|
||
|
|
while ((IN32(SSPC_SR) & SSPC_SR_RFVE_MASK) == 0){
|
||
|
|
if ( ++t > RTS_DIN_TIMEOUT){
|
||
|
|
|
||
|
|
DEBUG(1, 1, "rts spi timeout at data[%d]\n", i);
|
||
|
|
goto _timeout;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* Read data byte */
|
||
|
|
data[i] = IN32(SSPC_DR);
|
||
|
|
DEBUG(0, 1, "[RTS] data[%d] %d, 0x%x\n", i, data[i], data[i]);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Disable SSP data out */
|
||
|
|
CLRR32(SSPC_CR2, SSPC_C2_SSPEN_MASK | SSPC_C2_TXDOE_MASK);
|
||
|
|
|
||
|
|
/* Compose final data (12-bits or 8-bits) */
|
||
|
|
#if ((RTS_ADS7846_RY & RTS_ADS7846_MODE_MASK) == (RTS_ADS7846_8_BITS << RTS_ADS7846_MODE_SHIFT))
|
||
|
|
*y = RTS_ADS7846_8BITS_DATA(data[3], data[4]);
|
||
|
|
*x = RTS_ADS7846_8BITS_DATA(data[5], data[6]);
|
||
|
|
*z1 = RTS_ADS7846_8BITS_DATA(data[7], data[8]);
|
||
|
|
*z2 = RTS_ADS7846_8BITS_DATA(data[9], data[10]);
|
||
|
|
#else
|
||
|
|
*y = RTS_ADS7846_12BITS_DATA(data[3], data[4]);
|
||
|
|
*x = RTS_ADS7846_12BITS_DATA(data[5], data[6]);
|
||
|
|
*z1 = RTS_ADS7846_12BITS_DATA(data[7], data[8]);
|
||
|
|
*z2 = RTS_ADS7846_12BITS_DATA(data[9], data[10]);
|
||
|
|
#endif
|
||
|
|
#ifndef CONFIG_PLAT_QEMU
|
||
|
|
DEBUG(0, 1, "[RTS] y - %04d, msb(0x%02lx) lsb(0x%02lx)\n", *y, (data[3] & 0xff), (data[4] & 0xff));
|
||
|
|
DEBUG(0, 1, "[RTS] x - %04d, msb(0x%02lx) lsb(0x%02lx)\n", *x, (data[5] & 0xff), (data[6] & 0xff));
|
||
|
|
DEBUG(0, 1, "[RTS] z1 - %04d, msb(0x%02lx) lsb(0x%02lx)\n", *z1, (data[7] & 0xff), (data[8] & 0xff));
|
||
|
|
DEBUG(0, 1, "[RTS] z2 - %04d, msb(0x%02lx) lsb(0x%02lx)\n", *z2, (data[9] & 0xff), (data[10] & 0xff));
|
||
|
|
#else
|
||
|
|
DEBUG(0, 1, "[RTS] y - %d, msb(0x%x)%d, lsb(0x%x)%d\n", *y, data[3],data[3], data[4], data[4]);
|
||
|
|
DEBUG(0, 1, "[RTS] x - %d, msb(0x%x)%d, lsb(0x%x)%d\n", *x, data[5],data[5], data[6], data[6]);
|
||
|
|
DEBUG(0, 1, "[RTS] z1 - %d, msb(0x%x)%d, lsb(0x%x)%d\n", *z1, data[7],data[7], data[8], data[8]);
|
||
|
|
DEBUG(0, 1, "[RTS] z2 - %d, msb(0x%x)%d, lsb(0x%x)%d\n", *z2, data[9],data[9], data[10], data[10]);
|
||
|
|
#endif
|
||
|
|
if ((*z1 < RTS_PRESSED_Z1_MIN) && (*z2 >= RTS_PRESSED_Z2_MAX))
|
||
|
|
*pressed = 0;
|
||
|
|
else
|
||
|
|
*pressed = 1;
|
||
|
|
|
||
|
|
return HAL_SUCCESS;
|
||
|
|
|
||
|
|
_timeout:
|
||
|
|
|
||
|
|
return HAL_FAILURE;
|
||
|
|
}
|
||
|
|
|
||
|
|
void ts_adjust(struct ts_dev *ts, int ts_x, int ts_y, int *x, int *y)
|
||
|
|
{
|
||
|
|
*x = (ts->lcd_width * (ts_x - ts->left)) / (ts->right - ts->left);
|
||
|
|
*y = (ts->lcd_height * (ts_y - ts->top)) / (ts->bottom - ts->top);
|
||
|
|
DEBUG(0, 0, "adj (x, y) = (%4d, %4d)\n", *x, *y);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ts_raw_value(struct ts_dev *ts, int *x, int *y)
|
||
|
|
{
|
||
|
|
hal_pend_semaphore(&ts->sem, HAL_SUSPEND);
|
||
|
|
|
||
|
|
*x = ts->data.x;
|
||
|
|
*y = ts->data.y;
|
||
|
|
DEBUG(0, 0, "raw (x, y) = (%4d, %4d)\n", *x, *y);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ts_value(struct ts_dev *ts, int *x, int *y)
|
||
|
|
{
|
||
|
|
int raw_x, raw_y;
|
||
|
|
ts_raw_value(ts, &raw_x, &raw_y);
|
||
|
|
ts_adjust(ts, raw_x, raw_y, x, y);
|
||
|
|
}
|
||
|
|
|
||
|
|
void ts_calibrate(struct ts_dev *ts,
|
||
|
|
void (*draw_cross)(void *param, int x, int y),
|
||
|
|
int count)
|
||
|
|
{
|
||
|
|
int i = 0;
|
||
|
|
int left = 0, right = 0, top = 0, bottom = 0;
|
||
|
|
|
||
|
|
for (i = 0; i < count; i++) {
|
||
|
|
|
||
|
|
int raw_x = 0, raw_y = 0;
|
||
|
|
|
||
|
|
DEBUG(0, 0, "(left, top) = ");
|
||
|
|
draw_cross(NULL, ts->lcd_width * 1 / 5, ts->lcd_height * 1 / 5);
|
||
|
|
ts_raw_value(ts, &raw_x, &raw_y);
|
||
|
|
left = ((left * i) + raw_x) / (i + 1);
|
||
|
|
top = ((top * i) + raw_y) / (i + 1);
|
||
|
|
DEBUG(0, 0, "(%4d, %4d) || (x, y) = (%4d, %4d)\n", left, top, raw_x, raw_y);
|
||
|
|
|
||
|
|
DEBUG(0, 0, "(right, bottom) = ");
|
||
|
|
draw_cross(NULL, ts->lcd_width * 4 / 5, ts->lcd_height * 4 / 5);
|
||
|
|
ts_raw_value(ts, &raw_x, &raw_y);
|
||
|
|
right = ((right * i) + raw_x) / (i + 1);
|
||
|
|
bottom = ((bottom * i) + raw_y) / (i + 1);
|
||
|
|
DEBUG(0, 0, "(%4d, %4d) || (x, y) = (%4d, %4d)\n", right, bottom, raw_x, raw_y);
|
||
|
|
}
|
||
|
|
|
||
|
|
ts->left = left - (right - left) / 3;
|
||
|
|
ts->right = right + (right - left) / 3;
|
||
|
|
ts->top = top - (bottom - top) / 3;
|
||
|
|
ts->bottom = bottom + (bottom - top) / 3;
|
||
|
|
}
|